Lines Matching full:sub
53 u64 aio_rb_cnt(struct uniphier_aio_sub *sub) in aio_rb_cnt() argument
55 return rb_cnt(sub->wr_offs, sub->rd_offs, sub->compr_bytes); in aio_rb_cnt()
58 u64 aio_rbt_cnt_to_end(struct uniphier_aio_sub *sub) in aio_rbt_cnt_to_end() argument
60 return rb_cnt_to_end(sub->wr_offs, sub->rd_offs, sub->compr_bytes); in aio_rbt_cnt_to_end()
63 u64 aio_rb_space(struct uniphier_aio_sub *sub) in aio_rb_space() argument
65 return rb_space(sub->wr_offs, sub->rd_offs, sub->compr_bytes); in aio_rb_space()
68 u64 aio_rb_space_to_end(struct uniphier_aio_sub *sub) in aio_rb_space_to_end() argument
70 return rb_space_to_end(sub->wr_offs, sub->rd_offs, sub->compr_bytes); in aio_rb_space_to_end()
193 * @sub: the AIO substream pointer
200 int aio_init(struct uniphier_aio_sub *sub) in aio_init() argument
202 struct device *dev = &sub->aio->chip->pdev->dev; in aio_init()
203 struct regmap *r = sub->aio->chip->regmap; in aio_init()
205 regmap_write(r, A2RBNMAPCTR0(sub->swm->rb.hw), in aio_init()
206 MAPCTR0_EN | sub->swm->rb.map); in aio_init()
207 regmap_write(r, A2CHNMAPCTR0(sub->swm->ch.hw), in aio_init()
208 MAPCTR0_EN | sub->swm->ch.map); in aio_init()
210 switch (sub->swm->type) { in aio_init()
214 if (sub->swm->dir == PORT_DIR_INPUT) { in aio_init()
215 regmap_write(r, A2IIFNMAPCTR0(sub->swm->iif.hw), in aio_init()
216 MAPCTR0_EN | sub->swm->iif.map); in aio_init()
217 regmap_write(r, A2IPORTNMAPCTR0(sub->swm->iport.hw), in aio_init()
218 MAPCTR0_EN | sub->swm->iport.map); in aio_init()
220 regmap_write(r, A2OIFNMAPCTR0(sub->swm->oif.hw), in aio_init()
221 MAPCTR0_EN | sub->swm->oif.map); in aio_init()
222 regmap_write(r, A2OPORTNMAPCTR0(sub->swm->oport.hw), in aio_init()
223 MAPCTR0_EN | sub->swm->oport.map); in aio_init()
227 regmap_write(r, A2OIFNMAPCTR0(sub->swm->oif.hw), in aio_init()
228 MAPCTR0_EN | sub->swm->oif.map); in aio_init()
229 regmap_write(r, A2OPORTNMAPCTR0(sub->swm->oport.hw), in aio_init()
230 MAPCTR0_EN | sub->swm->oport.map); in aio_init()
231 regmap_write(r, A2CHNMAPCTR0(sub->swm->och.hw), in aio_init()
232 MAPCTR0_EN | sub->swm->och.map); in aio_init()
233 regmap_write(r, A2IIFNMAPCTR0(sub->swm->iif.hw), in aio_init()
234 MAPCTR0_EN | sub->swm->iif.map); in aio_init()
237 dev_err(dev, "Unknown port type %d.\n", sub->swm->type); in aio_init()
246 * @sub: the AIO substream pointer
250 void aio_port_reset(struct uniphier_aio_sub *sub) in aio_port_reset() argument
252 struct regmap *r = sub->aio->chip->regmap; in aio_port_reset()
254 if (sub->swm->dir == PORT_DIR_OUTPUT) { in aio_port_reset()
255 regmap_write(r, AOUTRSTCTR0, BIT(sub->swm->oport.map)); in aio_port_reset()
256 regmap_write(r, AOUTRSTCTR1, BIT(sub->swm->oport.map)); in aio_port_reset()
258 regmap_update_bits(r, IPORTMXRSTCTR(sub->swm->iport.map), in aio_port_reset()
261 regmap_update_bits(r, IPORTMXRSTCTR(sub->swm->iport.map), in aio_port_reset()
269 * @sub: the AIO substream pointer, PCM substream only
277 static int aio_port_set_ch(struct uniphier_aio_sub *sub) in aio_port_set_ch() argument
279 struct regmap *r = sub->aio->chip->regmap; in aio_port_set_ch()
293 switch (params_channels(&sub->params)) { in aio_port_set_ch()
308 regmap_update_bits(r, OPORTMXTYSLOTCTR(sub->swm->oport.map, i), in aio_port_set_ch()
310 regmap_update_bits(r, OPORTMXTYSLOTCTR(sub->swm->oport.map, i), in aio_port_set_ch()
319 * @sub: the AIO substream pointer, PCM substream only
329 static int aio_port_set_rate(struct uniphier_aio_sub *sub, int rate) in aio_port_set_rate() argument
331 struct regmap *r = sub->aio->chip->regmap; in aio_port_set_rate()
332 struct device *dev = &sub->aio->chip->pdev->dev; in aio_port_set_rate()
335 if (sub->swm->dir == PORT_DIR_OUTPUT) { in aio_port_set_rate()
381 regmap_update_bits(r, OPORTMXCTR1(sub->swm->oport.map), in aio_port_set_rate()
429 regmap_update_bits(r, IPORTMXCTR1(sub->swm->iport.map), in aio_port_set_rate()
438 * @sub: the AIO substream pointer, PCM substream only
448 static int aio_port_set_fmt(struct uniphier_aio_sub *sub) in aio_port_set_fmt() argument
450 struct regmap *r = sub->aio->chip->regmap; in aio_port_set_fmt()
451 struct device *dev = &sub->aio->chip->pdev->dev; in aio_port_set_fmt()
454 if (sub->swm->dir == PORT_DIR_OUTPUT) { in aio_port_set_fmt()
455 switch (sub->aio->fmt) { in aio_port_set_fmt()
467 sub->aio->fmt); in aio_port_set_fmt()
472 regmap_update_bits(r, OPORTMXCTR1(sub->swm->oport.map), in aio_port_set_fmt()
476 switch (sub->aio->fmt) { in aio_port_set_fmt()
488 sub->aio->fmt); in aio_port_set_fmt()
494 regmap_update_bits(r, IPORTMXCTR1(sub->swm->iport.map), in aio_port_set_fmt()
505 * @sub: the AIO substream pointer
513 static int aio_port_set_clk(struct uniphier_aio_sub *sub) in aio_port_set_clk() argument
515 struct uniphier_aio_chip *chip = sub->aio->chip; in aio_port_set_clk()
516 struct device *dev = &sub->aio->chip->pdev->dev; in aio_port_set_clk()
517 struct regmap *r = sub->aio->chip->regmap; in aio_port_set_clk()
530 if (sub->swm->dir == PORT_DIR_OUTPUT) { in aio_port_set_clk()
531 if (sub->swm->type == PORT_TYPE_I2S) { in aio_port_set_clk()
532 if (sub->aio->pll_out >= ARRAY_SIZE(v_pll)) { in aio_port_set_clk()
534 sub->aio->pll_out); in aio_port_set_clk()
537 if (sub->aio->plldiv >= ARRAY_SIZE(v_div)) { in aio_port_set_clk()
539 sub->aio->plldiv); in aio_port_set_clk()
543 v = v_pll[sub->aio->pll_out] | in aio_port_set_clk()
545 v_div[sub->aio->plldiv]; in aio_port_set_clk()
547 switch (chip->plls[sub->aio->pll_out].freq) { in aio_port_set_clk()
557 } else if (sub->swm->type == PORT_TYPE_EVE) { in aio_port_set_clk()
562 } else if (sub->swm->type == PORT_TYPE_SPDIF) { in aio_port_set_clk()
563 if (sub->aio->pll_out >= ARRAY_SIZE(v_pll)) { in aio_port_set_clk()
565 sub->aio->pll_out); in aio_port_set_clk()
568 v = v_pll[sub->aio->pll_out] | in aio_port_set_clk()
572 switch (chip->plls[sub->aio->pll_out].freq) { in aio_port_set_clk()
588 regmap_write(r, OPORTMXCTR2(sub->swm->oport.map), v); in aio_port_set_clk()
594 regmap_write(r, IPORTMXCTR2(sub->swm->iport.map), v); in aio_port_set_clk()
602 * @sub: the AIO substream pointer
612 int aio_port_set_param(struct uniphier_aio_sub *sub, int pass_through, in aio_port_set_param() argument
615 struct regmap *r = sub->aio->chip->regmap; in aio_port_set_param()
621 if (sub->swm->type == PORT_TYPE_EVE || in aio_port_set_param()
622 sub->swm->type == PORT_TYPE_CONV) { in aio_port_set_param()
628 ret = aio_port_set_ch(sub); in aio_port_set_param()
632 ret = aio_port_set_rate(sub, rate); in aio_port_set_param()
636 ret = aio_port_set_fmt(sub); in aio_port_set_param()
641 ret = aio_port_set_clk(sub); in aio_port_set_param()
645 if (sub->swm->dir == PORT_DIR_OUTPUT) { in aio_port_set_param()
656 regmap_write(r, OPORTMXCTR3(sub->swm->oport.map), v); in aio_port_set_param()
658 regmap_write(r, IPORTMXACLKSEL0EX(sub->swm->iport.map), in aio_port_set_param()
660 regmap_write(r, IPORTMXEXNOE(sub->swm->iport.map), in aio_port_set_param()
669 * @sub: the AIO substream pointer
674 void aio_port_set_enable(struct uniphier_aio_sub *sub, int enable) in aio_port_set_enable() argument
676 struct regmap *r = sub->aio->chip->regmap; in aio_port_set_enable()
678 if (sub->swm->dir == PORT_DIR_OUTPUT) { in aio_port_set_enable()
679 regmap_write(r, OPORTMXPATH(sub->swm->oport.map), in aio_port_set_enable()
680 sub->swm->oif.map); in aio_port_set_enable()
682 regmap_update_bits(r, OPORTMXMASK(sub->swm->oport.map), in aio_port_set_enable()
693 regmap_write(r, AOUTENCTR0, BIT(sub->swm->oport.map)); in aio_port_set_enable()
695 regmap_write(r, AOUTENCTR1, BIT(sub->swm->oport.map)); in aio_port_set_enable()
697 regmap_update_bits(r, IPORTMXMASK(sub->swm->iport.map), in aio_port_set_enable()
705 IPORTMXCTR2(sub->swm->iport.map), in aio_port_set_enable()
710 IPORTMXCTR2(sub->swm->iport.map), in aio_port_set_enable()
718 * @sub: the AIO substream pointer
722 int aio_port_get_volume(struct uniphier_aio_sub *sub) in aio_port_get_volume() argument
724 struct regmap *r = sub->aio->chip->regmap; in aio_port_get_volume()
727 regmap_read(r, OPORTMXTYVOLGAINSTATUS(sub->swm->oport.map, 0), &v); in aio_port_get_volume()
734 * @sub: the AIO substream pointer
741 void aio_port_set_volume(struct uniphier_aio_sub *sub, int vol) in aio_port_set_volume() argument
743 struct regmap *r = sub->aio->chip->regmap; in aio_port_set_volume()
744 int oport_map = sub->swm->oport.map; in aio_port_set_volume()
747 if (sub->swm->dir == PORT_DIR_INPUT) in aio_port_set_volume()
750 cur = aio_port_get_volume(sub); in aio_port_set_volume()
752 fs = params_rate(&sub->params); in aio_port_set_volume()
776 * @sub: the AIO substream pointer
785 int aio_if_set_param(struct uniphier_aio_sub *sub, int pass_through) in aio_if_set_param() argument
787 struct regmap *r = sub->aio->chip->regmap; in aio_if_set_param()
790 if (sub->swm->dir == PORT_DIR_OUTPUT) { in aio_if_set_param()
795 switch (params_channels(&sub->params)) { in aio_if_set_param()
811 regmap_write(r, PBOUTMXCTR0(sub->swm->oif.map), v); in aio_if_set_param()
812 regmap_write(r, PBOUTMXCTR1(sub->swm->oif.map), 0); in aio_if_set_param()
814 regmap_write(r, PBINMXCTR(sub->swm->iif.map), in aio_if_set_param()
817 (sub->swm->iport.map << PBINMXCTR_PBINSEL_SHIFT) | in aio_if_set_param()
827 * @sub: the AIO substream pointer
835 int aio_oport_set_stream_type(struct uniphier_aio_sub *sub, in aio_oport_set_stream_type() argument
838 struct regmap *r = sub->aio->chip->regmap; in aio_oport_set_stream_type()
882 regmap_write(r, OPORTMXREPET(sub->swm->oport.map), repet); in aio_oport_set_stream_type()
883 regmap_write(r, OPORTMXPAUDAT(sub->swm->oport.map), pause); in aio_oport_set_stream_type()
890 * @sub: the AIO substream pointer
896 void aio_src_reset(struct uniphier_aio_sub *sub) in aio_src_reset() argument
898 struct regmap *r = sub->aio->chip->regmap; in aio_src_reset()
900 if (sub->swm->dir != PORT_DIR_OUTPUT) in aio_src_reset()
903 regmap_write(r, AOUTSRCRSTCTR0, BIT(sub->swm->oport.map)); in aio_src_reset()
904 regmap_write(r, AOUTSRCRSTCTR1, BIT(sub->swm->oport.map)); in aio_src_reset()
909 * @sub: the AIO substream pointer
918 int aio_src_set_param(struct uniphier_aio_sub *sub, in aio_src_set_param() argument
921 struct regmap *r = sub->aio->chip->regmap; in aio_src_set_param()
924 if (sub->swm->dir != PORT_DIR_OUTPUT) in aio_src_set_param()
927 regmap_write(r, OPORTMXSRC1CTR(sub->swm->oport.map), in aio_src_set_param()
953 regmap_write(r, OPORTMXRATE_I(sub->swm->oport.map), in aio_src_set_param()
956 regmap_update_bits(r, OPORTMXRATE_I(sub->swm->oport.map), in aio_src_set_param()
963 int aio_srcif_set_param(struct uniphier_aio_sub *sub) in aio_srcif_set_param() argument
965 struct regmap *r = sub->aio->chip->regmap; in aio_srcif_set_param()
967 regmap_write(r, PBINMXCTR(sub->swm->iif.map), in aio_srcif_set_param()
970 (sub->swm->oport.map << PBINMXCTR_PBINSEL_SHIFT) | in aio_srcif_set_param()
977 int aio_srcch_set_param(struct uniphier_aio_sub *sub) in aio_srcch_set_param() argument
979 struct regmap *r = sub->aio->chip->regmap; in aio_srcch_set_param()
981 regmap_write(r, CDA2D_CHMXCTRL1(sub->swm->och.map), in aio_srcch_set_param()
984 regmap_write(r, CDA2D_CHMXSRCAMODE(sub->swm->och.map), in aio_srcch_set_param()
989 regmap_write(r, CDA2D_CHMXDSTAMODE(sub->swm->och.map), in aio_srcch_set_param()
993 (sub->swm->och.map << CDA2D_CHMXAMODE_RSSEL_SHIFT)); in aio_srcch_set_param()
998 void aio_srcch_set_enable(struct uniphier_aio_sub *sub, int enable) in aio_srcch_set_enable() argument
1000 struct regmap *r = sub->aio->chip->regmap; in aio_srcch_set_enable()
1009 v | BIT(sub->swm->och.map)); in aio_srcch_set_enable()
1012 int aiodma_ch_set_param(struct uniphier_aio_sub *sub) in aiodma_ch_set_param() argument
1014 struct regmap *r = sub->aio->chip->regmap; in aiodma_ch_set_param()
1017 regmap_write(r, CDA2D_CHMXCTRL1(sub->swm->ch.map), in aiodma_ch_set_param()
1023 (sub->swm->rb.map << CDA2D_CHMXAMODE_RSSEL_SHIFT); in aiodma_ch_set_param()
1024 if (sub->swm->dir == PORT_DIR_OUTPUT) in aiodma_ch_set_param()
1025 regmap_write(r, CDA2D_CHMXSRCAMODE(sub->swm->ch.map), v); in aiodma_ch_set_param()
1027 regmap_write(r, CDA2D_CHMXDSTAMODE(sub->swm->ch.map), v); in aiodma_ch_set_param()
1032 void aiodma_ch_set_enable(struct uniphier_aio_sub *sub, int enable) in aiodma_ch_set_enable() argument
1034 struct regmap *r = sub->aio->chip->regmap; in aiodma_ch_set_enable()
1038 CDA2D_STRT0_STOP_START | BIT(sub->swm->ch.map)); in aiodma_ch_set_enable()
1041 BIT(sub->swm->rb.map), in aiodma_ch_set_enable()
1042 BIT(sub->swm->rb.map)); in aiodma_ch_set_enable()
1045 CDA2D_STRT0_STOP_STOP | BIT(sub->swm->ch.map)); in aiodma_ch_set_enable()
1048 BIT(sub->swm->rb.map), in aiodma_ch_set_enable()
1053 static u64 aiodma_rb_get_rp(struct uniphier_aio_sub *sub) in aiodma_rb_get_rp() argument
1055 struct regmap *r = sub->aio->chip->regmap; in aiodma_rb_get_rp()
1060 CDA2D_RDPTRLOAD_LSFLAG_STORE | BIT(sub->swm->rb.map)); in aiodma_rb_get_rp()
1063 regmap_read(r, CDA2D_RBMXRDPTR(sub->swm->rb.map), &pos_l); in aiodma_rb_get_rp()
1065 regmap_read(r, CDA2D_RBMXRDPTR(sub->swm->rb.map), &pos_l); in aiodma_rb_get_rp()
1066 regmap_read(r, CDA2D_RBMXRDPTRU(sub->swm->rb.map), &pos_u); in aiodma_rb_get_rp()
1072 static void aiodma_rb_set_rp(struct uniphier_aio_sub *sub, u64 pos) in aiodma_rb_set_rp() argument
1074 struct regmap *r = sub->aio->chip->regmap; in aiodma_rb_set_rp()
1078 regmap_write(r, CDA2D_RBMXRDPTR(sub->swm->rb.map), (u32)pos); in aiodma_rb_set_rp()
1079 regmap_write(r, CDA2D_RBMXRDPTRU(sub->swm->rb.map), (u32)(pos >> 32)); in aiodma_rb_set_rp()
1080 regmap_write(r, CDA2D_RDPTRLOAD, BIT(sub->swm->rb.map)); in aiodma_rb_set_rp()
1083 regmap_read(r, CDA2D_RBMXRDPTR(sub->swm->rb.map), &tmp); in aiodma_rb_set_rp()
1086 static u64 aiodma_rb_get_wp(struct uniphier_aio_sub *sub) in aiodma_rb_get_wp() argument
1088 struct regmap *r = sub->aio->chip->regmap; in aiodma_rb_get_wp()
1093 CDA2D_WRPTRLOAD_LSFLAG_STORE | BIT(sub->swm->rb.map)); in aiodma_rb_get_wp()
1096 regmap_read(r, CDA2D_RBMXWRPTR(sub->swm->rb.map), &pos_l); in aiodma_rb_get_wp()
1098 regmap_read(r, CDA2D_RBMXWRPTR(sub->swm->rb.map), &pos_l); in aiodma_rb_get_wp()
1099 regmap_read(r, CDA2D_RBMXWRPTRU(sub->swm->rb.map), &pos_u); in aiodma_rb_get_wp()
1105 static void aiodma_rb_set_wp(struct uniphier_aio_sub *sub, u64 pos) in aiodma_rb_set_wp() argument
1107 struct regmap *r = sub->aio->chip->regmap; in aiodma_rb_set_wp()
1111 regmap_write(r, CDA2D_RBMXWRPTR(sub->swm->rb.map), in aiodma_rb_set_wp()
1113 regmap_write(r, CDA2D_RBMXWRPTRU(sub->swm->rb.map), in aiodma_rb_set_wp()
1115 regmap_write(r, CDA2D_WRPTRLOAD, BIT(sub->swm->rb.map)); in aiodma_rb_set_wp()
1118 regmap_read(r, CDA2D_RBMXWRPTR(sub->swm->rb.map), &tmp); in aiodma_rb_set_wp()
1121 int aiodma_rb_set_threshold(struct uniphier_aio_sub *sub, u64 size, u32 th) in aiodma_rb_set_threshold() argument
1123 struct regmap *r = sub->aio->chip->regmap; in aiodma_rb_set_threshold()
1128 regmap_write(r, CDA2D_RBMXBTH(sub->swm->rb.map), th); in aiodma_rb_set_threshold()
1129 regmap_write(r, CDA2D_RBMXRTH(sub->swm->rb.map), th); in aiodma_rb_set_threshold()
1134 int aiodma_rb_set_buffer(struct uniphier_aio_sub *sub, u64 start, u64 end, in aiodma_rb_set_buffer() argument
1137 struct regmap *r = sub->aio->chip->regmap; in aiodma_rb_set_buffer()
1144 regmap_write(r, CDA2D_RBMXCNFG(sub->swm->rb.map), 0); in aiodma_rb_set_buffer()
1145 regmap_write(r, CDA2D_RBMXBGNADRS(sub->swm->rb.map), in aiodma_rb_set_buffer()
1147 regmap_write(r, CDA2D_RBMXBGNADRSU(sub->swm->rb.map), in aiodma_rb_set_buffer()
1149 regmap_write(r, CDA2D_RBMXENDADRS(sub->swm->rb.map), in aiodma_rb_set_buffer()
1151 regmap_write(r, CDA2D_RBMXENDADRSU(sub->swm->rb.map), in aiodma_rb_set_buffer()
1154 regmap_write(r, CDA2D_RBADRSLOAD, BIT(sub->swm->rb.map)); in aiodma_rb_set_buffer()
1156 ret = aiodma_rb_set_threshold(sub, size, 2 * period); in aiodma_rb_set_buffer()
1160 if (sub->swm->dir == PORT_DIR_OUTPUT) { in aiodma_rb_set_buffer()
1161 aiodma_rb_set_rp(sub, start); in aiodma_rb_set_buffer()
1162 aiodma_rb_set_wp(sub, end - period); in aiodma_rb_set_buffer()
1164 regmap_update_bits(r, CDA2D_RBMXIE(sub->swm->rb.map), in aiodma_rb_set_buffer()
1168 aiodma_rb_set_rp(sub, end - period); in aiodma_rb_set_buffer()
1169 aiodma_rb_set_wp(sub, start); in aiodma_rb_set_buffer()
1171 regmap_update_bits(r, CDA2D_RBMXIE(sub->swm->rb.map), in aiodma_rb_set_buffer()
1176 sub->threshold = 2 * period; in aiodma_rb_set_buffer()
1177 sub->rd_offs = 0; in aiodma_rb_set_buffer()
1178 sub->wr_offs = 0; in aiodma_rb_set_buffer()
1179 sub->rd_org = 0; in aiodma_rb_set_buffer()
1180 sub->wr_org = 0; in aiodma_rb_set_buffer()
1181 sub->rd_total = 0; in aiodma_rb_set_buffer()
1182 sub->wr_total = 0; in aiodma_rb_set_buffer()
1187 void aiodma_rb_sync(struct uniphier_aio_sub *sub, u64 start, u64 size, in aiodma_rb_sync() argument
1190 if (sub->swm->dir == PORT_DIR_OUTPUT) { in aiodma_rb_sync()
1191 sub->rd_offs = aiodma_rb_get_rp(sub) - start; in aiodma_rb_sync()
1193 if (sub->use_mmap) { in aiodma_rb_sync()
1194 sub->threshold = 2 * period; in aiodma_rb_sync()
1195 aiodma_rb_set_threshold(sub, size, 2 * period); in aiodma_rb_sync()
1197 sub->wr_offs = sub->rd_offs - period; in aiodma_rb_sync()
1198 if (sub->rd_offs < period) in aiodma_rb_sync()
1199 sub->wr_offs += size; in aiodma_rb_sync()
1201 aiodma_rb_set_wp(sub, sub->wr_offs + start); in aiodma_rb_sync()
1203 sub->wr_offs = aiodma_rb_get_wp(sub) - start; in aiodma_rb_sync()
1205 if (sub->use_mmap) { in aiodma_rb_sync()
1206 sub->threshold = 2 * period; in aiodma_rb_sync()
1207 aiodma_rb_set_threshold(sub, size, 2 * period); in aiodma_rb_sync()
1209 sub->rd_offs = sub->wr_offs - period; in aiodma_rb_sync()
1210 if (sub->wr_offs < period) in aiodma_rb_sync()
1211 sub->rd_offs += size; in aiodma_rb_sync()
1213 aiodma_rb_set_rp(sub, sub->rd_offs + start); in aiodma_rb_sync()
1216 sub->rd_total += sub->rd_offs - sub->rd_org; in aiodma_rb_sync()
1217 if (sub->rd_offs < sub->rd_org) in aiodma_rb_sync()
1218 sub->rd_total += size; in aiodma_rb_sync()
1219 sub->wr_total += sub->wr_offs - sub->wr_org; in aiodma_rb_sync()
1220 if (sub->wr_offs < sub->wr_org) in aiodma_rb_sync()
1221 sub->wr_total += size; in aiodma_rb_sync()
1223 sub->rd_org = sub->rd_offs; in aiodma_rb_sync()
1224 sub->wr_org = sub->wr_offs; in aiodma_rb_sync()
1227 bool aiodma_rb_is_irq(struct uniphier_aio_sub *sub) in aiodma_rb_is_irq() argument
1229 struct regmap *r = sub->aio->chip->regmap; in aiodma_rb_is_irq()
1232 regmap_read(r, CDA2D_RBMXIR(sub->swm->rb.map), &ir); in aiodma_rb_is_irq()
1234 if (sub->swm->dir == PORT_DIR_OUTPUT) in aiodma_rb_is_irq()
1240 void aiodma_rb_clear_irq(struct uniphier_aio_sub *sub) in aiodma_rb_clear_irq() argument
1242 struct regmap *r = sub->aio->chip->regmap; in aiodma_rb_clear_irq()
1244 if (sub->swm->dir == PORT_DIR_OUTPUT) in aiodma_rb_clear_irq()
1245 regmap_write(r, CDA2D_RBMXIR(sub->swm->rb.map), in aiodma_rb_clear_irq()
1248 regmap_write(r, CDA2D_RBMXIR(sub->swm->rb.map), in aiodma_rb_clear_irq()