Lines Matching +full:stream +full:- +full:match +full:- +full:mask
1 // SPDX-License-Identifier: GPL-2.0-only
3 * tegra30_i2s.c - Tegra30 I2S driver
6 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
10 * Copyright (c) 2009-2010, NVIDIA Corporation.
36 #define DRV_NAME "tegra30-i2s"
42 regcache_cache_only(i2s->regmap, true); in tegra30_i2s_runtime_suspend()
44 clk_disable_unprepare(i2s->clk_i2s); in tegra30_i2s_runtime_suspend()
54 ret = clk_prepare_enable(i2s->clk_i2s); in tegra30_i2s_runtime_resume()
60 regcache_cache_only(i2s->regmap, false); in tegra30_i2s_runtime_resume()
69 unsigned int mask = 0, val = 0; in tegra30_i2s_set_fmt() local
75 return -EINVAL; in tegra30_i2s_set_fmt()
78 mask |= TEGRA30_I2S_CTRL_MASTER_ENABLE; in tegra30_i2s_set_fmt()
86 return -EINVAL; in tegra30_i2s_set_fmt()
89 mask |= TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK | in tegra30_i2s_set_fmt()
113 return -EINVAL; in tegra30_i2s_set_fmt()
116 pm_runtime_get_sync(dai->dev); in tegra30_i2s_set_fmt()
117 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val); in tegra30_i2s_set_fmt()
118 pm_runtime_put(dai->dev); in tegra30_i2s_set_fmt()
127 struct device *dev = dai->dev; in tegra30_i2s_hw_params()
129 unsigned int mask, val, reg; in tegra30_i2s_hw_params() local
134 return -EINVAL; in tegra30_i2s_hw_params()
136 mask = TEGRA30_I2S_CTRL_BIT_SIZE_MASK; in tegra30_i2s_hw_params()
143 return -EINVAL; in tegra30_i2s_hw_params()
146 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val); in tegra30_i2s_hw_params()
153 bitcnt = (i2sclock / (2 * srate)) - 1; in tegra30_i2s_hw_params()
155 return -EINVAL; in tegra30_i2s_hw_params()
157 ret = clk_set_rate(i2s->clk_i2s, i2sclock); in tegra30_i2s_hw_params()
168 regmap_write(i2s->regmap, TEGRA30_I2S_TIMING, val); in tegra30_i2s_hw_params()
181 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { in tegra30_i2s_hw_params()
189 i2s->soc_data->set_audio_cif(i2s->regmap, reg, &cif_conf); in tegra30_i2s_hw_params()
193 regmap_write(i2s->regmap, TEGRA30_I2S_OFFSET, val); in tegra30_i2s_hw_params()
200 tegra30_ahub_enable_tx_fifo(i2s->playback_fifo_cif); in tegra30_i2s_start_playback()
201 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, in tegra30_i2s_start_playback()
208 tegra30_ahub_disable_tx_fifo(i2s->playback_fifo_cif); in tegra30_i2s_stop_playback()
209 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, in tegra30_i2s_stop_playback()
215 tegra30_ahub_enable_rx_fifo(i2s->capture_fifo_cif); in tegra30_i2s_start_capture()
216 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, in tegra30_i2s_start_capture()
223 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, in tegra30_i2s_stop_capture()
225 tegra30_ahub_disable_rx_fifo(i2s->capture_fifo_cif); in tegra30_i2s_stop_capture()
237 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in tegra30_i2s_trigger()
245 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in tegra30_i2s_trigger()
251 return -EINVAL; in tegra30_i2s_trigger()
262 unsigned int mask, val; in tegra30_i2s_set_tdm() local
264 dev_dbg(dai->dev, "%s: txmask=0x%08x rxmask=0x%08x slots=%d width=%d\n", in tegra30_i2s_set_tdm()
267 mask = TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK | in tegra30_i2s_set_tdm()
273 ((slots - 1) << TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT); in tegra30_i2s_set_tdm()
275 pm_runtime_get_sync(dai->dev); in tegra30_i2s_set_tdm()
276 regmap_update_bits(i2s->regmap, TEGRA30_I2S_SLOT_CTRL, mask, val); in tegra30_i2s_set_tdm()
278 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CH_CTRL, in tegra30_i2s_set_tdm()
280 pm_runtime_put(dai->dev); in tegra30_i2s_set_tdm()
289 dai->capture_dma_data = &i2s->capture_dma_data; in tegra30_i2s_probe()
290 dai->playback_dma_data = &i2s->playback_dma_data; in tegra30_i2s_probe()
390 { .compatible = "nvidia,tegra124-i2s", .data = &tegra124_i2s_config },
391 { .compatible = "nvidia,tegra30-i2s", .data = &tegra30_i2s_config },
398 const struct of_device_id *match; in tegra30_i2s_platform_probe() local
403 i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_i2s), GFP_KERNEL); in tegra30_i2s_platform_probe()
405 ret = -ENOMEM; in tegra30_i2s_platform_probe()
408 dev_set_drvdata(&pdev->dev, i2s); in tegra30_i2s_platform_probe()
410 match = of_match_device(tegra30_i2s_of_match, &pdev->dev); in tegra30_i2s_platform_probe()
411 if (!match) { in tegra30_i2s_platform_probe()
412 dev_err(&pdev->dev, "Error: No device match found\n"); in tegra30_i2s_platform_probe()
413 ret = -ENODEV; in tegra30_i2s_platform_probe()
416 i2s->soc_data = (struct tegra30_i2s_soc_data *)match->data; in tegra30_i2s_platform_probe()
418 i2s->dai = tegra30_i2s_dai_template; in tegra30_i2s_platform_probe()
419 i2s->dai.name = dev_name(&pdev->dev); in tegra30_i2s_platform_probe()
421 ret = of_property_read_u32_array(pdev->dev.of_node, in tegra30_i2s_platform_probe()
422 "nvidia,ahub-cif-ids", cif_ids, in tegra30_i2s_platform_probe()
427 i2s->playback_i2s_cif = cif_ids[0]; in tegra30_i2s_platform_probe()
428 i2s->capture_i2s_cif = cif_ids[1]; in tegra30_i2s_platform_probe()
430 i2s->clk_i2s = clk_get(&pdev->dev, NULL); in tegra30_i2s_platform_probe()
431 if (IS_ERR(i2s->clk_i2s)) { in tegra30_i2s_platform_probe()
432 dev_err(&pdev->dev, "Can't retrieve i2s clock\n"); in tegra30_i2s_platform_probe()
433 ret = PTR_ERR(i2s->clk_i2s); in tegra30_i2s_platform_probe()
443 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, in tegra30_i2s_platform_probe()
445 if (IS_ERR(i2s->regmap)) { in tegra30_i2s_platform_probe()
446 dev_err(&pdev->dev, "regmap init failed\n"); in tegra30_i2s_platform_probe()
447 ret = PTR_ERR(i2s->regmap); in tegra30_i2s_platform_probe()
450 regcache_cache_only(i2s->regmap, true); in tegra30_i2s_platform_probe()
452 pm_runtime_enable(&pdev->dev); in tegra30_i2s_platform_probe()
453 if (!pm_runtime_enabled(&pdev->dev)) { in tegra30_i2s_platform_probe()
454 ret = tegra30_i2s_runtime_resume(&pdev->dev); in tegra30_i2s_platform_probe()
459 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; in tegra30_i2s_platform_probe()
460 i2s->playback_dma_data.maxburst = 4; in tegra30_i2s_platform_probe()
461 ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif, in tegra30_i2s_platform_probe()
462 i2s->playback_dma_chan, in tegra30_i2s_platform_probe()
463 sizeof(i2s->playback_dma_chan), in tegra30_i2s_platform_probe()
464 &i2s->playback_dma_data.addr); in tegra30_i2s_platform_probe()
466 dev_err(&pdev->dev, "Could not alloc TX FIFO: %d\n", ret); in tegra30_i2s_platform_probe()
469 ret = tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif, in tegra30_i2s_platform_probe()
470 i2s->playback_fifo_cif); in tegra30_i2s_platform_probe()
472 dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret); in tegra30_i2s_platform_probe()
476 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; in tegra30_i2s_platform_probe()
477 i2s->capture_dma_data.maxburst = 4; in tegra30_i2s_platform_probe()
478 ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif, in tegra30_i2s_platform_probe()
479 i2s->capture_dma_chan, in tegra30_i2s_platform_probe()
480 sizeof(i2s->capture_dma_chan), in tegra30_i2s_platform_probe()
481 &i2s->capture_dma_data.addr); in tegra30_i2s_platform_probe()
483 dev_err(&pdev->dev, "Could not alloc RX FIFO: %d\n", ret); in tegra30_i2s_platform_probe()
486 ret = tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif, in tegra30_i2s_platform_probe()
487 i2s->capture_i2s_cif); in tegra30_i2s_platform_probe()
489 dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret); in tegra30_i2s_platform_probe()
493 ret = snd_soc_register_component(&pdev->dev, &tegra30_i2s_component, in tegra30_i2s_platform_probe()
494 &i2s->dai, 1); in tegra30_i2s_platform_probe()
496 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret); in tegra30_i2s_platform_probe()
497 ret = -ENOMEM; in tegra30_i2s_platform_probe()
501 ret = tegra_pcm_platform_register_with_chan_names(&pdev->dev, in tegra30_i2s_platform_probe()
502 &i2s->dma_config, i2s->playback_dma_chan, in tegra30_i2s_platform_probe()
503 i2s->capture_dma_chan); in tegra30_i2s_platform_probe()
505 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret); in tegra30_i2s_platform_probe()
512 snd_soc_unregister_component(&pdev->dev); in tegra30_i2s_platform_probe()
514 tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif); in tegra30_i2s_platform_probe()
516 tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif); in tegra30_i2s_platform_probe()
518 tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif); in tegra30_i2s_platform_probe()
520 tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif); in tegra30_i2s_platform_probe()
522 if (!pm_runtime_status_suspended(&pdev->dev)) in tegra30_i2s_platform_probe()
523 tegra30_i2s_runtime_suspend(&pdev->dev); in tegra30_i2s_platform_probe()
525 pm_runtime_disable(&pdev->dev); in tegra30_i2s_platform_probe()
527 clk_put(i2s->clk_i2s); in tegra30_i2s_platform_probe()
534 struct tegra30_i2s *i2s = dev_get_drvdata(&pdev->dev); in tegra30_i2s_platform_remove()
536 pm_runtime_disable(&pdev->dev); in tegra30_i2s_platform_remove()
537 if (!pm_runtime_status_suspended(&pdev->dev)) in tegra30_i2s_platform_remove()
538 tegra30_i2s_runtime_suspend(&pdev->dev); in tegra30_i2s_platform_remove()
540 tegra_pcm_platform_unregister(&pdev->dev); in tegra30_i2s_platform_remove()
541 snd_soc_unregister_component(&pdev->dev); in tegra30_i2s_platform_remove()
543 tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif); in tegra30_i2s_platform_remove()
544 tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif); in tegra30_i2s_platform_remove()
546 tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif); in tegra30_i2s_platform_remove()
547 tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif); in tegra30_i2s_platform_remove()
549 clk_put(i2s->clk_i2s); in tegra30_i2s_platform_remove()
559 regcache_mark_dirty(i2s->regmap); in tegra30_i2s_suspend()
574 ret = regcache_sync(i2s->regmap); in tegra30_i2s_resume()