Lines Matching refs:TEGRA186_MUX_ROUTES
411 #define TEGRA186_MUX_ROUTES(name) \ macro
476 TEGRA186_MUX_ROUTES("ADMAIF1")
477 TEGRA186_MUX_ROUTES("ADMAIF2")
478 TEGRA186_MUX_ROUTES("ADMAIF3")
479 TEGRA186_MUX_ROUTES("ADMAIF4")
480 TEGRA186_MUX_ROUTES("ADMAIF5")
481 TEGRA186_MUX_ROUTES("ADMAIF6")
482 TEGRA186_MUX_ROUTES("ADMAIF7")
483 TEGRA186_MUX_ROUTES("ADMAIF8")
484 TEGRA186_MUX_ROUTES("ADMAIF9")
485 TEGRA186_MUX_ROUTES("ADMAIF10")
486 TEGRA186_MUX_ROUTES("ADMAIF11")
487 TEGRA186_MUX_ROUTES("ADMAIF12")
488 TEGRA186_MUX_ROUTES("ADMAIF13")
489 TEGRA186_MUX_ROUTES("ADMAIF14")
490 TEGRA186_MUX_ROUTES("ADMAIF15")
491 TEGRA186_MUX_ROUTES("ADMAIF16")
492 TEGRA186_MUX_ROUTES("ADMAIF17")
493 TEGRA186_MUX_ROUTES("ADMAIF18")
494 TEGRA186_MUX_ROUTES("ADMAIF19")
495 TEGRA186_MUX_ROUTES("ADMAIF20")
496 TEGRA186_MUX_ROUTES("I2S1")
497 TEGRA186_MUX_ROUTES("I2S2")
498 TEGRA186_MUX_ROUTES("I2S3")
499 TEGRA186_MUX_ROUTES("I2S4")
500 TEGRA186_MUX_ROUTES("I2S5")
501 TEGRA186_MUX_ROUTES("I2S6")
502 TEGRA186_MUX_ROUTES("DSPK1")
503 TEGRA186_MUX_ROUTES("DSPK2")