Lines Matching +full:sun6i +full:- +full:a31 +full:- +full:codec
1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
22 #include <sound/soc-dai.h>
82 #define SUN4I_I2S_CHAN_SEL(num_chan) (((num_chan) - 1) << 0)
90 /* Defines required for sun8i-h3 support */
103 #define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8)
113 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan) ((chan - 1) << 4)
115 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan) (chan - 1)
122 #define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4)
130 * struct sun4i_i2s_quirks - Differences between SoC variants.
204 /* TODO - extend divide ratio supported by newer SoCs */
216 /* TODO - extend divide ratio supported by newer SoCs */
239 return i2s->mclk_freq; in sun4i_i2s_get_bclk_parent_rate()
244 return clk_get_rate(i2s->mod_clk); in sun8i_i2s_get_bclk_parent_rate()
253 const struct sun4i_i2s_clk_div *dividers = i2s->variant->bclk_dividers; in sun4i_i2s_get_bclk_div()
257 for (i = 0; i < i2s->variant->num_bclk_dividers; i++) { in sun4i_i2s_get_bclk_div()
260 if (bdiv->div == div) in sun4i_i2s_get_bclk_div()
261 return bdiv->val; in sun4i_i2s_get_bclk_div()
264 return -EINVAL; in sun4i_i2s_get_bclk_div()
271 const struct sun4i_i2s_clk_div *dividers = i2s->variant->mclk_dividers; in sun4i_i2s_get_mclk_div()
275 for (i = 0; i < i2s->variant->num_mclk_dividers; i++) { in sun4i_i2s_get_mclk_div()
278 if (mdiv->div == div) in sun4i_i2s_get_mclk_div()
279 return mdiv->val; in sun4i_i2s_get_mclk_div()
282 return -EINVAL; in sun4i_i2s_get_mclk_div()
330 dev_err(dai->dev, "Unsupported sample rate: %u\n", rate); in sun4i_i2s_set_clk_rate()
331 return -EINVAL; in sun4i_i2s_set_clk_rate()
334 ret = clk_set_rate(i2s->mod_clk, clk_rate); in sun4i_i2s_set_clk_rate()
338 oversample_rate = i2s->mclk_freq / rate; in sun4i_i2s_set_clk_rate()
340 dev_err(dai->dev, "Unsupported oversample rate: %d\n", in sun4i_i2s_set_clk_rate()
342 return -EINVAL; in sun4i_i2s_set_clk_rate()
345 bclk_parent_rate = i2s->variant->get_bclk_parent_rate(i2s); in sun4i_i2s_set_clk_rate()
349 dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div); in sun4i_i2s_set_clk_rate()
350 return -EINVAL; in sun4i_i2s_set_clk_rate()
353 mclk_div = sun4i_i2s_get_mclk_div(i2s, clk_rate, i2s->mclk_freq); in sun4i_i2s_set_clk_rate()
355 dev_err(dai->dev, "Unsupported MCLK divider: %d\n", mclk_div); in sun4i_i2s_set_clk_rate()
356 return -EINVAL; in sun4i_i2s_set_clk_rate()
359 regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG, in sun4i_i2s_set_clk_rate()
363 regmap_field_write(i2s->field_clkdiv_mclk_en, 1); in sun4i_i2s_set_clk_rate()
371 return -EINVAL; in sun4i_i2s_get_sr()
374 return -EINVAL; in sun4i_i2s_get_sr()
376 return (width - 16) / 4; in sun4i_i2s_get_sr()
382 return -EINVAL; in sun4i_i2s_get_wss()
385 return -EINVAL; in sun4i_i2s_get_wss()
387 return (width - 16) / 4; in sun4i_i2s_get_wss()
393 return -EINVAL; in sun8i_i2s_get_sr_wss()
396 return -EINVAL; in sun8i_i2s_get_sr_wss()
398 return (width - 8) / 4 + 1; in sun8i_i2s_get_sr_wss()
407 regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210); in sun4i_i2s_set_chan_cfg()
408 regmap_write(i2s->regmap, SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210); in sun4i_i2s_set_chan_cfg()
411 regmap_update_bits(i2s->regmap, SUN4I_I2S_TX_CHAN_SEL_REG, in sun4i_i2s_set_chan_cfg()
414 regmap_update_bits(i2s->regmap, SUN4I_I2S_RX_CHAN_SEL_REG, in sun4i_i2s_set_chan_cfg()
428 if (i2s->slots) in sun8i_i2s_set_chan_cfg()
429 slots = i2s->slots; in sun8i_i2s_set_chan_cfg()
432 regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_MAP_REG, 0x76543210); in sun8i_i2s_set_chan_cfg()
433 regmap_write(i2s->regmap, SUN8I_I2S_RX_CHAN_MAP_REG, 0x76543210); in sun8i_i2s_set_chan_cfg()
436 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, in sun8i_i2s_set_chan_cfg()
439 regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG, in sun8i_i2s_set_chan_cfg()
443 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, in sun8i_i2s_set_chan_cfg()
446 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, in sun8i_i2s_set_chan_cfg()
450 switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) { in sun8i_i2s_set_chan_cfg()
463 return -EINVAL; in sun8i_i2s_set_chan_cfg()
466 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, in sun8i_i2s_set_chan_cfg()
470 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, in sun8i_i2s_set_chan_cfg()
489 if (i2s->slots) in sun4i_i2s_hw_params()
490 slots = i2s->slots; in sun4i_i2s_hw_params()
492 if (i2s->slot_width) in sun4i_i2s_hw_params()
493 slot_width = i2s->slot_width; in sun4i_i2s_hw_params()
495 ret = i2s->variant->set_chan_cfg(i2s, params); in sun4i_i2s_hw_params()
497 dev_err(dai->dev, "Invalid channel configuration\n"); in sun4i_i2s_hw_params()
506 dev_err(dai->dev, "Unsupported physical sample width: %d\n", in sun4i_i2s_hw_params()
508 return -EINVAL; in sun4i_i2s_hw_params()
510 i2s->playback_dma_data.addr_width = width; in sun4i_i2s_hw_params()
512 sr = i2s->variant->get_sr(i2s, word_size); in sun4i_i2s_hw_params()
514 return -EINVAL; in sun4i_i2s_hw_params()
516 wss = i2s->variant->get_wss(i2s, slot_width); in sun4i_i2s_hw_params()
518 return -EINVAL; in sun4i_i2s_hw_params()
520 regmap_field_write(i2s->field_fmt_wss, wss); in sun4i_i2s_hw_params()
521 regmap_field_write(i2s->field_fmt_sr, sr); in sun4i_i2s_hw_params()
551 return -EINVAL; in sun4i_i2s_set_soc_fmt()
554 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, in sun4i_i2s_set_soc_fmt()
574 return -EINVAL; in sun4i_i2s_set_soc_fmt()
577 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, in sun4i_i2s_set_soc_fmt()
593 return -EINVAL; in sun4i_i2s_set_soc_fmt()
595 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_set_soc_fmt()
631 return -EINVAL; in sun8i_i2s_set_soc_fmt()
634 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, in sun8i_i2s_set_soc_fmt()
667 return -EINVAL; in sun8i_i2s_set_soc_fmt()
670 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun8i_i2s_set_soc_fmt()
672 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, in sun8i_i2s_set_soc_fmt()
675 regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG, in sun8i_i2s_set_soc_fmt()
692 return -EINVAL; in sun8i_i2s_set_soc_fmt()
695 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun8i_i2s_set_soc_fmt()
707 ret = i2s->variant->set_fmt(i2s, fmt); in sun4i_i2s_set_fmt()
709 dev_err(dai->dev, "Unsupported format configuration\n"); in sun4i_i2s_set_fmt()
714 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, in sun4i_i2s_set_fmt()
720 i2s->format = fmt; in sun4i_i2s_set_fmt()
728 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, in sun4i_i2s_start_capture()
733 regmap_write(i2s->regmap, SUN4I_I2S_RX_CNT_REG, 0); in sun4i_i2s_start_capture()
736 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_start_capture()
741 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, in sun4i_i2s_start_capture()
749 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, in sun4i_i2s_start_playback()
754 regmap_write(i2s->regmap, SUN4I_I2S_TX_CNT_REG, 0); in sun4i_i2s_start_playback()
757 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_start_playback()
762 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, in sun4i_i2s_start_playback()
770 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_stop_capture()
775 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, in sun4i_i2s_stop_capture()
783 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_stop_playback()
788 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, in sun4i_i2s_stop_playback()
802 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in sun4i_i2s_trigger()
811 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in sun4i_i2s_trigger()
818 return -EINVAL; in sun4i_i2s_trigger()
830 return -EINVAL; in sun4i_i2s_set_sysclk()
832 i2s->mclk_freq = freq; in sun4i_i2s_set_sysclk()
844 return -EINVAL; in sun4i_i2s_set_tdm_slot()
846 i2s->slots = slots; in sun4i_i2s_set_tdm_slot()
847 i2s->slot_width = slot_width; in sun4i_i2s_set_tdm_slot()
865 &i2s->playback_dma_data, in sun4i_i2s_dai_probe()
866 &i2s->capture_dma_data); in sun4i_i2s_dai_probe()
894 .name = "sun4i-dai",
1014 ret = clk_prepare_enable(i2s->bus_clk); in sun4i_i2s_runtime_resume()
1020 regcache_cache_only(i2s->regmap, false); in sun4i_i2s_runtime_resume()
1021 regcache_mark_dirty(i2s->regmap); in sun4i_i2s_runtime_resume()
1023 ret = regcache_sync(i2s->regmap); in sun4i_i2s_runtime_resume()
1030 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_runtime_resume()
1034 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_runtime_resume()
1038 ret = clk_prepare_enable(i2s->mod_clk); in sun4i_i2s_runtime_resume()
1047 clk_disable_unprepare(i2s->bus_clk); in sun4i_i2s_runtime_resume()
1055 clk_disable_unprepare(i2s->mod_clk); in sun4i_i2s_runtime_suspend()
1058 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_runtime_suspend()
1062 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_runtime_suspend()
1065 regcache_cache_only(i2s->regmap, true); in sun4i_i2s_runtime_suspend()
1067 clk_disable_unprepare(i2s->bus_clk); in sun4i_i2s_runtime_suspend()
1170 i2s->field_clkdiv_mclk_en = in sun4i_i2s_init_regmap_fields()
1171 devm_regmap_field_alloc(dev, i2s->regmap, in sun4i_i2s_init_regmap_fields()
1172 i2s->variant->field_clkdiv_mclk_en); in sun4i_i2s_init_regmap_fields()
1173 if (IS_ERR(i2s->field_clkdiv_mclk_en)) in sun4i_i2s_init_regmap_fields()
1174 return PTR_ERR(i2s->field_clkdiv_mclk_en); in sun4i_i2s_init_regmap_fields()
1176 i2s->field_fmt_wss = in sun4i_i2s_init_regmap_fields()
1177 devm_regmap_field_alloc(dev, i2s->regmap, in sun4i_i2s_init_regmap_fields()
1178 i2s->variant->field_fmt_wss); in sun4i_i2s_init_regmap_fields()
1179 if (IS_ERR(i2s->field_fmt_wss)) in sun4i_i2s_init_regmap_fields()
1180 return PTR_ERR(i2s->field_fmt_wss); in sun4i_i2s_init_regmap_fields()
1182 i2s->field_fmt_sr = in sun4i_i2s_init_regmap_fields()
1183 devm_regmap_field_alloc(dev, i2s->regmap, in sun4i_i2s_init_regmap_fields()
1184 i2s->variant->field_fmt_sr); in sun4i_i2s_init_regmap_fields()
1185 if (IS_ERR(i2s->field_fmt_sr)) in sun4i_i2s_init_regmap_fields()
1186 return PTR_ERR(i2s->field_fmt_sr); in sun4i_i2s_init_regmap_fields()
1198 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); in sun4i_i2s_probe()
1200 return -ENOMEM; in sun4i_i2s_probe()
1204 regs = devm_ioremap_resource(&pdev->dev, res); in sun4i_i2s_probe()
1212 i2s->variant = of_device_get_match_data(&pdev->dev); in sun4i_i2s_probe()
1213 if (!i2s->variant) { in sun4i_i2s_probe()
1214 dev_err(&pdev->dev, "Failed to determine the quirks to use\n"); in sun4i_i2s_probe()
1215 return -ENODEV; in sun4i_i2s_probe()
1218 i2s->bus_clk = devm_clk_get(&pdev->dev, "apb"); in sun4i_i2s_probe()
1219 if (IS_ERR(i2s->bus_clk)) { in sun4i_i2s_probe()
1220 dev_err(&pdev->dev, "Can't get our bus clock\n"); in sun4i_i2s_probe()
1221 return PTR_ERR(i2s->bus_clk); in sun4i_i2s_probe()
1224 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, in sun4i_i2s_probe()
1225 i2s->variant->sun4i_i2s_regmap); in sun4i_i2s_probe()
1226 if (IS_ERR(i2s->regmap)) { in sun4i_i2s_probe()
1227 dev_err(&pdev->dev, "Regmap initialisation failed\n"); in sun4i_i2s_probe()
1228 return PTR_ERR(i2s->regmap); in sun4i_i2s_probe()
1231 i2s->mod_clk = devm_clk_get(&pdev->dev, "mod"); in sun4i_i2s_probe()
1232 if (IS_ERR(i2s->mod_clk)) { in sun4i_i2s_probe()
1233 dev_err(&pdev->dev, "Can't get our mod clock\n"); in sun4i_i2s_probe()
1234 return PTR_ERR(i2s->mod_clk); in sun4i_i2s_probe()
1237 if (i2s->variant->has_reset) { in sun4i_i2s_probe()
1238 i2s->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); in sun4i_i2s_probe()
1239 if (IS_ERR(i2s->rst)) { in sun4i_i2s_probe()
1240 dev_err(&pdev->dev, "Failed to get reset control\n"); in sun4i_i2s_probe()
1241 return PTR_ERR(i2s->rst); in sun4i_i2s_probe()
1245 if (!IS_ERR(i2s->rst)) { in sun4i_i2s_probe()
1246 ret = reset_control_deassert(i2s->rst); in sun4i_i2s_probe()
1248 dev_err(&pdev->dev, in sun4i_i2s_probe()
1250 return -EINVAL; in sun4i_i2s_probe()
1254 i2s->playback_dma_data.addr = res->start + in sun4i_i2s_probe()
1255 i2s->variant->reg_offset_txdata; in sun4i_i2s_probe()
1256 i2s->playback_dma_data.maxburst = 8; in sun4i_i2s_probe()
1258 i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG; in sun4i_i2s_probe()
1259 i2s->capture_dma_data.maxburst = 8; in sun4i_i2s_probe()
1261 pm_runtime_enable(&pdev->dev); in sun4i_i2s_probe()
1262 if (!pm_runtime_enabled(&pdev->dev)) { in sun4i_i2s_probe()
1263 ret = sun4i_i2s_runtime_resume(&pdev->dev); in sun4i_i2s_probe()
1268 ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s); in sun4i_i2s_probe()
1270 dev_err(&pdev->dev, "Could not initialise regmap fields\n"); in sun4i_i2s_probe()
1274 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); in sun4i_i2s_probe()
1276 dev_err(&pdev->dev, "Could not register PCM\n"); in sun4i_i2s_probe()
1280 ret = devm_snd_soc_register_component(&pdev->dev, in sun4i_i2s_probe()
1284 dev_err(&pdev->dev, "Could not register DAI\n"); in sun4i_i2s_probe()
1291 if (!pm_runtime_status_suspended(&pdev->dev)) in sun4i_i2s_probe()
1292 sun4i_i2s_runtime_suspend(&pdev->dev); in sun4i_i2s_probe()
1294 pm_runtime_disable(&pdev->dev); in sun4i_i2s_probe()
1295 if (!IS_ERR(i2s->rst)) in sun4i_i2s_probe()
1296 reset_control_assert(i2s->rst); in sun4i_i2s_probe()
1303 struct sun4i_i2s *i2s = dev_get_drvdata(&pdev->dev); in sun4i_i2s_remove()
1305 pm_runtime_disable(&pdev->dev); in sun4i_i2s_remove()
1306 if (!pm_runtime_status_suspended(&pdev->dev)) in sun4i_i2s_remove()
1307 sun4i_i2s_runtime_suspend(&pdev->dev); in sun4i_i2s_remove()
1309 if (!IS_ERR(i2s->rst)) in sun4i_i2s_remove()
1310 reset_control_assert(i2s->rst); in sun4i_i2s_remove()
1317 .compatible = "allwinner,sun4i-a10-i2s",
1321 .compatible = "allwinner,sun6i-a31-i2s",
1325 .compatible = "allwinner,sun8i-a83t-i2s",
1329 .compatible = "allwinner,sun8i-h3-i2s",
1333 .compatible = "allwinner,sun50i-a64-codec-i2s",
1349 .name = "sun4i-i2s",
1357 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");