62 #define BYT_DSP_BAR		0  macro
67 	{"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
69 	{"dmac1", BYT_DSP_BAR,  DMAC1_OFFSET, DMAC_SIZE,
71 	{"ssp0",  BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE,
73 	{"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE,
75 	{"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE,
77 	{"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
79 	{"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
81 	{"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT,
127 	status = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD);  in byt_dump()
128 	panic = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX);  in byt_dump()
135 	imrx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRX);  in byt_dump()
136 	imrd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRD);  in byt_dump()
166 	ipcx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX);  in byt_irq_handler()
167 	ipcd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD);  in byt_irq_handler()
172 		snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR,  in byt_irq_handler()
182 		snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR,  in byt_irq_handler()
197 	ipcx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX);  in byt_irq_thread()
198 	ipcd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD);  in byt_irq_thread()
240 	snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX,  in byt_send_msg()
246 	snd_sof_dsp_write64(sdev, BYT_DSP_BAR, SHIM_IPCX, SHIM_BYT_IPCX_BUSY);  in byt_send_msg()
303 	snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCD,  in byt_host_done()
309 	snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX,  in byt_host_done()
316 	snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCX,  in byt_dsp_done()
329 	snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR,  in byt_run()
332 		if (!(snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_CSR) &  in byt_run()
350 	snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR,  in byt_reset()
359 	snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR,  in byt_reset()
531 	sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size);  in tangier_pci_probe()
532 	if (!sdev->bar[BYT_DSP_BAR]) {  in tangier_pci_probe()
537 	dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]);  in tangier_pci_probe()
575 	snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX,  in tangier_pci_probe()
665 	snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x3);  in byt_reset_dsp_disable_int()
666 	snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x3);  in byt_reset_dsp_disable_int()
669 	snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR,  in byt_reset_dsp_disable_int()
684 	snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX,  in byt_resume()
699 	{"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
701 	{"dmac1", BYT_DSP_BAR,  DMAC1_OFFSET, DMAC_SIZE,
703 	{"dmac2", BYT_DSP_BAR,  DMAC2_OFFSET, DMAC_SIZE,
705 	{"ssp0",  BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE,
707 	{"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE,
709 	{"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE,
711 	{"ssp3", BYT_DSP_BAR, SSP3_OFFSET, SSP_SIZE,
713 	{"ssp4", BYT_DSP_BAR, SSP4_OFFSET, SSP_SIZE,
715 	{"ssp5", BYT_DSP_BAR, SSP5_OFFSET, SSP_SIZE,
717 	{"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
719 	{"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
721 	{"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE_CHT,
755 	sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size);  in byt_acpi_probe()
756 	if (!sdev->bar[BYT_DSP_BAR]) {  in byt_acpi_probe()
761 	dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]);  in byt_acpi_probe()
764 	sdev->mmio_bar = BYT_DSP_BAR;  in byt_acpi_probe()
765 	sdev->mailbox_bar = BYT_DSP_BAR;  in byt_acpi_probe()
814 	snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX,  in byt_acpi_probe()