11 #define LPAIF_I2SCTL_REG_ADDR(v, addr, port) \  argument
12 	(v->i2sctrl_reg_base + (addr) + v->i2sctrl_reg_stride * (port))
14 #define LPAIF_I2SCTL_REG(v, port)	LPAIF_I2SCTL_REG_ADDR(v, 0x0, (port))  argument
17 #define LPAIF_I2SCTL_LOOPBACK_ENABLE	1
20 #define LPAIF_I2SCTL_SPKEN_ENABLE	1
23 #define LPAIF_I2SCTL_MODE_SD0		1
46 #define LPAIF_I2SCTL_SPKMONO_MONO	1
49 #define LPAIF_I2SCTL_MICEN_ENABLE	1
54 #define LPAIF_I2SCTL_MICMONO_MONO	1
57 #define LPAIF_I2SCTL_WSSRC_EXTERNAL	1
60 #define LPAIF_I2SCTL_BITWIDTH_24	1
64 #define LPAIF_BIT_CLK_ENABLE		1
71 #define LPAIF_IRQ_REG_ADDR(v, addr, port) \  argument
72 	(v->irq_reg_base + (addr) + v->irq_reg_stride * (port))
76 #define LPAIF_IRQEN_REG(v, port)	LPAIF_IRQ_REG_ADDR(v, 0x0, (port))  argument
77 #define LPAIF_IRQSTAT_REG(v, port)	LPAIF_IRQ_REG_ADDR(v, 0x4, (port))  argument
78 #define LPAIF_IRQCLEAR_REG(v, port)	LPAIF_IRQ_REG_ADDR(v, 0xC, (port))  argument
81 #define LPASS_HDMITX_APP_IRQ_REG_ADDR(v, addr)  \  argument
82 	((v->hdmi_irq_reg_base) + (addr))
84 #define LPASS_HDMITX_APP_IRQEN_REG(v)			LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0x4)  argument
85 #define LPASS_HDMITX_APP_IRQSTAT_REG(v)			LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0x8)  argument
86 #define LPASS_HDMITX_APP_IRQCLEAR_REG(v)		LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0xC)  argument
90 #define LPAIF_IRQ_PER(chan)		(1 << (LPAIF_IRQ_BITSTRIDE * (chan)))
95 #define LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(chan)	(1 << (14 + chan))
96 #define LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(chan)	(1 << (24 + chan))
100 #define LPAIF_HDMI_RDMA_REG_ADDR(v, addr, chan) \  argument
101 	(v->hdmi_rdma_reg_base + (addr) + v->hdmi_rdma_reg_stride * (chan))
105 #define LPAIF_HDMI_RDMACTL_REG(v, chan)		LPAIF_HDMI_RDMA_REG_ADDR(v, 0x00, (chan))  argument
106 #define LPAIF_HDMI_RDMABASE_REG(v, chan)	LPAIF_HDMI_RDMA_REG_ADDR(v, 0x04, (chan))  argument
107 #define	LPAIF_HDMI_RDMABUFF_REG(v, chan)	LPAIF_HDMI_RDMA_REG_ADDR(v, 0x08, (chan))  argument
108 #define LPAIF_HDMI_RDMACURR_REG(v, chan)	LPAIF_HDMI_RDMA_REG_ADDR(v, 0x0C, (chan))  argument
109 #define	LPAIF_HDMI_RDMAPER_REG(v, chan)		LPAIF_HDMI_RDMA_REG_ADDR(v, 0x10, (chan))  argument
110 #define	LPAIF_HDMI_RDMAPERCNT_REG(v, chan)	LPAIF_HDMI_RDMA_REG_ADDR(v, 0x14, (chan))  argument
112 #define LPAIF_RDMA_REG_ADDR(v, addr, chan) \  argument
113 	(v->rdma_reg_base + (addr) + v->rdma_reg_stride * (chan))
117 #define LPAIF_RDMACTL_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x00, (chan))  argument
118 #define LPAIF_RDMABASE_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x04, (chan))  argument
119 #define	LPAIF_RDMABUFF_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x08, (chan))  argument
120 #define LPAIF_RDMACURR_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x0C, (chan))  argument
121 #define	LPAIF_RDMAPER_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x10, (chan))  argument
122 #define	LPAIF_RDMAPERCNT_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x14, (chan))  argument
124 #define LPAIF_WRDMA_REG_ADDR(v, addr, chan) \  argument
125 	(v->wrdma_reg_base + (addr) + \
126 	 v->wrdma_reg_stride * (chan - v->wrdma_channel_start))
128 #define LPAIF_WRDMACTL_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x00, (chan))  argument
129 #define LPAIF_WRDMABASE_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x04, (chan))  argument
130 #define	LPAIF_WRDMABUFF_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x08, (chan))  argument
131 #define LPAIF_WRDMACURR_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x0C, (chan))  argument
132 #define	LPAIF_WRDMAPER_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x10, (chan))  argument
133 #define	LPAIF_WRDMAPERCNT_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x14, (chan))  argument
135 #define LPAIF_INTFDMA_REG(v, chan, reg, dai_id)  \  argument
136 		((v->dai_driver[dai_id].id ==  LPASS_DP_RX) ? \
137 		LPAIF_HDMI_RDMA##reg##_REG(v, chan) : \
138 		 LPAIF_RDMA##reg##_REG(v, chan))
140 #define __LPAIF_DMA_REG(v, chan, dir, reg, dai_id)  \  argument
142 		(LPAIF_INTFDMA_REG(v, chan, reg, dai_id)) : \
143 		LPAIF_WRDMA##reg##_REG(v, chan))
145 #define LPAIF_DMACTL_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, CTL, dai_id)  argument
146 #define LPAIF_DMABASE_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, BASE, dai_id)  argument
147 #define	LPAIF_DMABUFF_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, BUFF, dai_id)  argument
148 #define LPAIF_DMACURR_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, CURR, dai_id)  argument
149 #define	LPAIF_DMAPER_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, PER, dai_id)  argument
150 #define	LPAIF_DMAPERCNT_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, PERCNT, dai_id)  argument
153 #define LPAIF_DMACTL_BURSTEN_INCR4	1
156 #define LPAIF_DMACTL_WPSCNT_TWO		1
169 #define LPAIF_DMACTL_FIFOWM_2		1
202 #define LPAIF_DMACTL_ENABLE_ON		1
205 #define LPAIF_DMACTL_DYNCLK_ON		1