1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
14 #include <sound/soc-dai.h>
16 #include "axg-fifo.h"
20  * capture frontend DAI. The logic behind this two types of fifo is very
48 	struct snd_soc_pcm_runtime *rtd = ss->private_data;  in axg_fifo_dai()
64 	return dai->dev;  in axg_fifo_dev()
67 static void __dma_enable(struct axg_fifo *fifo,  bool enable)  in __dma_enable()  argument
69 	regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_DMA_EN,  in __dma_enable()
76 	struct axg_fifo *fifo = axg_fifo_data(ss);  in axg_fifo_pcm_trigger()  local
82 		__dma_enable(fifo, true);  in axg_fifo_pcm_trigger()
87 		__dma_enable(fifo, false);  in axg_fifo_pcm_trigger()
90 		return -EINVAL;  in axg_fifo_pcm_trigger()
100 	struct axg_fifo *fifo = axg_fifo_data(ss);  in axg_fifo_pcm_pointer()  local
101 	struct snd_pcm_runtime *runtime = ss->runtime;  in axg_fifo_pcm_pointer()
104 	regmap_read(fifo->map, FIFO_STATUS2, &addr);  in axg_fifo_pcm_pointer()
106 	return bytes_to_frames(runtime, addr - (unsigned int)runtime->dma_addr);  in axg_fifo_pcm_pointer()
114 	struct snd_pcm_runtime *runtime = ss->runtime;  in axg_fifo_pcm_hw_params()
115 	struct axg_fifo *fifo = axg_fifo_data(ss);  in axg_fifo_pcm_hw_params()  local
122 	end_ptr = runtime->dma_addr + runtime->dma_bytes - AXG_FIFO_BURST;  in axg_fifo_pcm_hw_params()
123 	regmap_write(fifo->map, FIFO_START_ADDR, runtime->dma_addr);  in axg_fifo_pcm_hw_params()
124 	regmap_write(fifo->map, FIFO_FINISH_ADDR, end_ptr);  in axg_fifo_pcm_hw_params()
128 	regmap_write(fifo->map, FIFO_INT_ADDR, burst_num);  in axg_fifo_pcm_hw_params()
131 	 * Start the fifo request on the smallest of the following:  in axg_fifo_pcm_hw_params()
132 	 * - Half the fifo size  in axg_fifo_pcm_hw_params()
133 	 * - Half the period size  in axg_fifo_pcm_hw_params()
135 	threshold = min(period / 2, fifo->depth / 2);  in axg_fifo_pcm_hw_params()
139 	 * V = (threshold / burst) - 1  in axg_fifo_pcm_hw_params()
142 	regmap_field_write(fifo->field_threshold,  in axg_fifo_pcm_hw_params()
143 			   threshold ? threshold - 1 : 0);  in axg_fifo_pcm_hw_params()
146 	regmap_update_bits(fifo->map, FIFO_CTRL0,  in axg_fifo_pcm_hw_params()
158 	struct axg_fifo *fifo = axg_fifo_data(ss);  in g12a_fifo_pcm_hw_params()  local
159 	struct snd_pcm_runtime *runtime = ss->runtime;  in g12a_fifo_pcm_hw_params()
167 	regmap_write(fifo->map, FIFO_INIT_ADDR, runtime->dma_addr);  in g12a_fifo_pcm_hw_params()
176 	struct axg_fifo *fifo = axg_fifo_data(ss);  in axg_fifo_pcm_hw_free()  local
179 	regmap_update_bits(fifo->map, FIFO_CTRL0,  in axg_fifo_pcm_hw_free()
186 static void axg_fifo_ack_irq(struct axg_fifo *fifo, u8 mask)  in axg_fifo_ack_irq()  argument
188 	regmap_update_bits(fifo->map, FIFO_CTRL1,  in axg_fifo_ack_irq()
193 	regmap_update_bits(fifo->map, FIFO_CTRL1,  in axg_fifo_ack_irq()
201 	struct axg_fifo *fifo = axg_fifo_data(ss);  in axg_fifo_pcm_irq_block()  local
204 	regmap_read(fifo->map, FIFO_STATUS1, &status);  in axg_fifo_pcm_irq_block()
210 		dev_dbg(axg_fifo_dev(ss), "unexpected irq - STS 0x%02x\n",  in axg_fifo_pcm_irq_block()
214 	axg_fifo_ack_irq(fifo, status);  in axg_fifo_pcm_irq_block()
222 	struct axg_fifo *fifo = axg_fifo_data(ss);  in axg_fifo_pcm_open()  local
229 	 * Make sure the buffer and period size are multiple of the FIFO  in axg_fifo_pcm_open()
232 	ret = snd_pcm_hw_constraint_step(ss->runtime, 0,  in axg_fifo_pcm_open()
238 	ret = snd_pcm_hw_constraint_step(ss->runtime, 0,  in axg_fifo_pcm_open()
244 	ret = request_irq(fifo->irq, axg_fifo_pcm_irq_block, 0,  in axg_fifo_pcm_open()
249 	/* Enable pclk to access registers and clock the fifo ip */  in axg_fifo_pcm_open()
250 	ret = clk_prepare_enable(fifo->pclk);  in axg_fifo_pcm_open()
255 	regmap_update_bits(fifo->map, FIFO_CTRL1,  in axg_fifo_pcm_open()
260 	__dma_enable(fifo, false);  in axg_fifo_pcm_open()
263 	regmap_update_bits(fifo->map, FIFO_CTRL0,  in axg_fifo_pcm_open()
267 	axg_fifo_ack_irq(fifo, FIFO_INT_MASK);  in axg_fifo_pcm_open()
270 	ret = reset_control_deassert(fifo->arb);  in axg_fifo_pcm_open()
277 	clk_disable_unprepare(fifo->pclk);  in axg_fifo_pcm_open()
279 	free_irq(fifo->irq, ss);  in axg_fifo_pcm_open()
287 	struct axg_fifo *fifo = axg_fifo_data(ss);  in axg_fifo_pcm_close()  local
291 	ret = reset_control_assert(fifo->arb);  in axg_fifo_pcm_close()
293 	/* Disable fifo ip and register access */  in axg_fifo_pcm_close()
294 	clk_disable_unprepare(fifo->pclk);  in axg_fifo_pcm_close()
297 	free_irq(fifo->irq, ss);  in axg_fifo_pcm_close()
305 	struct snd_card *card = rtd->card->snd_card;  in axg_fifo_pcm_new()
306 	size_t size = axg_fifo_hw.buffer_bytes_max;  in axg_fifo_pcm_new()  local
308 	snd_pcm_set_managed_buffer(rtd->pcm->streams[type].substream,  in axg_fifo_pcm_new()
309 				   SNDRV_DMA_TYPE_DEV, card->dev,  in axg_fifo_pcm_new()
310 				   size, size);  in axg_fifo_pcm_new()
324 	struct device *dev = &pdev->dev;  in axg_fifo_probe()
326 	struct axg_fifo *fifo;  in axg_fifo_probe()  local
333 		return -ENODEV;  in axg_fifo_probe()
336 	fifo = devm_kzalloc(dev, sizeof(*fifo), GFP_KERNEL);  in axg_fifo_probe()
337 	if (!fifo)  in axg_fifo_probe()
338 		return -ENOMEM;  in axg_fifo_probe()
339 	platform_set_drvdata(pdev, fifo);  in axg_fifo_probe()
345 	fifo->map = devm_regmap_init_mmio(dev, regs, &axg_fifo_regmap_cfg);  in axg_fifo_probe()
346 	if (IS_ERR(fifo->map)) {  in axg_fifo_probe()
348 			PTR_ERR(fifo->map));  in axg_fifo_probe()
349 		return PTR_ERR(fifo->map);  in axg_fifo_probe()
352 	fifo->pclk = devm_clk_get(dev, NULL);  in axg_fifo_probe()
353 	if (IS_ERR(fifo->pclk)) {  in axg_fifo_probe()
354 		if (PTR_ERR(fifo->pclk) != -EPROBE_DEFER)  in axg_fifo_probe()
356 				PTR_ERR(fifo->pclk));  in axg_fifo_probe()
357 		return PTR_ERR(fifo->pclk);  in axg_fifo_probe()
360 	fifo->arb = devm_reset_control_get_exclusive(dev, NULL);  in axg_fifo_probe()
361 	if (IS_ERR(fifo->arb)) {  in axg_fifo_probe()
362 		if (PTR_ERR(fifo->arb) != -EPROBE_DEFER)  in axg_fifo_probe()
364 				PTR_ERR(fifo->arb));  in axg_fifo_probe()
365 		return PTR_ERR(fifo->arb);  in axg_fifo_probe()
368 	fifo->irq = of_irq_get(dev->of_node, 0);  in axg_fifo_probe()
369 	if (fifo->irq <= 0) {  in axg_fifo_probe()
370 		dev_err(dev, "failed to get irq: %d\n", fifo->irq);  in axg_fifo_probe()
371 		return fifo->irq;  in axg_fifo_probe()
374 	fifo->field_threshold =  in axg_fifo_probe()
375 		devm_regmap_field_alloc(dev, fifo->map, data->field_threshold);  in axg_fifo_probe()
376 	if (IS_ERR(fifo->field_threshold))  in axg_fifo_probe()
377 		return PTR_ERR(fifo->field_threshold);  in axg_fifo_probe()
379 	ret = of_property_read_u32(dev->of_node, "amlogic,fifo-depth",  in axg_fifo_probe()
380 				   &fifo->depth);  in axg_fifo_probe()
383 		if (ret != -EINVAL)  in axg_fifo_probe()
387 		 * DT. In such case, assume the smallest known fifo depth  in axg_fifo_probe()
389 		fifo->depth = 256;  in axg_fifo_probe()
390 		dev_warn(dev, "fifo depth not found, assume %u bytes\n",  in axg_fifo_probe()
391 			 fifo->depth);  in axg_fifo_probe()
394 	return devm_snd_soc_register_component(dev, data->component_drv,  in axg_fifo_probe()
395 					       data->dai_drv, 1);  in axg_fifo_probe()
399 MODULE_DESCRIPTION("Amlogic AXG/G12A fifo driver");