Lines Matching +full:0 +full:x1
12 #define AUDIO_TOP_CON0 0x0000
13 #define AUDIO_TOP_CON1 0x0004
14 #define AUDIO_TOP_CON3 0x000c
15 #define AFE_DAC_CON0 0x0010
16 #define AFE_DAC_CON1 0x0014
17 #define AFE_I2S_CON 0x0018
18 #define AFE_DAIBT_CON0 0x001c
19 #define AFE_CONN0 0x0020
20 #define AFE_CONN1 0x0024
21 #define AFE_CONN2 0x0028
22 #define AFE_CONN3 0x002c
23 #define AFE_CONN4 0x0030
24 #define AFE_I2S_CON1 0x0034
25 #define AFE_I2S_CON2 0x0038
26 #define AFE_MRGIF_CON 0x003c
27 #define AFE_DL1_BASE 0x0040
28 #define AFE_DL1_CUR 0x0044
29 #define AFE_DL1_END 0x0048
30 #define AFE_I2S_CON3 0x004c
31 #define AFE_DL2_BASE 0x0050
32 #define AFE_DL2_CUR 0x0054
33 #define AFE_DL2_END 0x0058
34 #define AFE_CONN5 0x005c
35 #define AFE_CONN_24BIT 0x006c
36 #define AFE_AWB_BASE 0x0070
37 #define AFE_AWB_END 0x0078
38 #define AFE_AWB_CUR 0x007c
39 #define AFE_VUL_BASE 0x0080
40 #define AFE_VUL_END 0x0088
41 #define AFE_VUL_CUR 0x008c
42 #define AFE_DAI_BASE 0x0090
43 #define AFE_DAI_END 0x0098
44 #define AFE_DAI_CUR 0x009c
45 #define AFE_CONN6 0x00bc
46 #define AFE_MEMIF_MSB 0x00cc
47 #define AFE_MEMIF_MON0 0x00d0
48 #define AFE_MEMIF_MON1 0x00d4
49 #define AFE_MEMIF_MON2 0x00d8
50 #define AFE_MEMIF_MON4 0x00e0
51 #define AFE_ADDA_DL_SRC2_CON0 0x0108
52 #define AFE_ADDA_DL_SRC2_CON1 0x010c
53 #define AFE_ADDA_UL_SRC_CON0 0x0114
54 #define AFE_ADDA_UL_SRC_CON1 0x0118
55 #define AFE_ADDA_TOP_CON0 0x0120
56 #define AFE_ADDA_UL_DL_CON0 0x0124
57 #define AFE_ADDA_SRC_DEBUG 0x012c
58 #define AFE_ADDA_SRC_DEBUG_MON0 0x0130
59 #define AFE_ADDA_SRC_DEBUG_MON1 0x0134
60 #define AFE_ADDA_NEWIF_CFG0 0x0138
61 #define AFE_ADDA_NEWIF_CFG1 0x013c
62 #define AFE_ADDA_NEWIF_CFG2 0x0140
63 #define AFE_DMA_CTL 0x0150
64 #define AFE_DMA_MON0 0x0154
65 #define AFE_DMA_MON1 0x0158
66 #define AFE_SIDETONE_DEBUG 0x01d0
67 #define AFE_SIDETONE_MON 0x01d4
68 #define AFE_SIDETONE_CON0 0x01e0
69 #define AFE_SIDETONE_COEFF 0x01e4
70 #define AFE_SIDETONE_CON1 0x01e8
71 #define AFE_SIDETONE_GAIN 0x01ec
72 #define AFE_SGEN_CON0 0x01f0
73 #define AFE_SINEGEN_CON_TDM 0x01fc
74 #define AFE_TOP_CON0 0x0200
75 #define AFE_ADDA_PREDIS_CON0 0x0260
76 #define AFE_ADDA_PREDIS_CON1 0x0264
77 #define AFE_MRGIF_MON0 0x0270
78 #define AFE_MRGIF_MON1 0x0274
79 #define AFE_MRGIF_MON2 0x0278
80 #define AFE_I2S_MON 0x027c
81 #define AFE_MOD_DAI_BASE 0x0330
82 #define AFE_MOD_DAI_END 0x0338
83 #define AFE_MOD_DAI_CUR 0x033c
84 #define AFE_VUL_D2_BASE 0x0350
85 #define AFE_VUL_D2_END 0x0358
86 #define AFE_VUL_D2_CUR 0x035c
87 #define AFE_DL3_BASE 0x0360
88 #define AFE_DL3_CUR 0x0364
89 #define AFE_DL3_END 0x0368
90 #define AFE_HDMI_OUT_CON0 0x0370
91 #define AFE_HDMI_BASE 0x0374
92 #define AFE_HDMI_CUR 0x0378
93 #define AFE_HDMI_END 0x037c
94 #define AFE_HDMI_CONN0 0x0390
95 #define AFE_IRQ3_MCU_CNT_MON 0x0398
96 #define AFE_IRQ4_MCU_CNT_MON 0x039c
97 #define AFE_IRQ_MCU_CON 0x03a0
98 #define AFE_IRQ_MCU_STATUS 0x03a4
99 #define AFE_IRQ_MCU_CLR 0x03a8
100 #define AFE_IRQ_MCU_CNT1 0x03ac
101 #define AFE_IRQ_MCU_CNT2 0x03b0
102 #define AFE_IRQ_MCU_EN 0x03b4
103 #define AFE_IRQ_MCU_MON2 0x03b8
104 #define AFE_IRQ_MCU_CNT5 0x03bc
105 #define AFE_IRQ1_MCU_CNT_MON 0x03c0
106 #define AFE_IRQ2_MCU_CNT_MON 0x03c4
107 #define AFE_IRQ1_MCU_EN_CNT_MON 0x03c8
108 #define AFE_IRQ5_MCU_CNT_MON 0x03cc
109 #define AFE_MEMIF_MINLEN 0x03d0
110 #define AFE_MEMIF_MAXLEN 0x03d4
111 #define AFE_MEMIF_PBUF_SIZE 0x03d8
112 #define AFE_IRQ_MCU_CNT7 0x03dc
113 #define AFE_IRQ7_MCU_CNT_MON 0x03e0
114 #define AFE_IRQ_MCU_CNT3 0x03e4
115 #define AFE_IRQ_MCU_CNT4 0x03e8
116 #define AFE_APLL1_TUNER_CFG 0x03f0
117 #define AFE_APLL2_TUNER_CFG 0x03f4
118 #define AFE_MEMIF_HD_MODE 0x03f8
119 #define AFE_MEMIF_HDALIGN 0x03fc
120 #define AFE_GAIN1_CON0 0x0410
121 #define AFE_GAIN1_CON1 0x0414
122 #define AFE_GAIN1_CON2 0x0418
123 #define AFE_GAIN1_CON3 0x041c
124 #define AFE_CONN7 0x0420
125 #define AFE_GAIN1_CUR 0x0424
126 #define AFE_GAIN2_CON0 0x0428
127 #define AFE_GAIN2_CON1 0x042c
128 #define AFE_GAIN2_CON2 0x0430
129 #define AFE_GAIN2_CON3 0x0434
130 #define AFE_CONN8 0x0438
131 #define AFE_GAIN2_CUR 0x043c
132 #define AFE_CONN9 0x0440
133 #define AFE_CONN10 0x0444
134 #define AFE_CONN11 0x0448
135 #define AFE_CONN12 0x044c
136 #define AFE_CONN13 0x0450
137 #define AFE_CONN14 0x0454
138 #define AFE_CONN15 0x0458
139 #define AFE_CONN16 0x045c
140 #define AFE_CONN17 0x0460
141 #define AFE_CONN18 0x0464
142 #define AFE_CONN19 0x0468
143 #define AFE_CONN20 0x046c
144 #define AFE_CONN21 0x0470
145 #define AFE_CONN22 0x0474
146 #define AFE_CONN23 0x0478
147 #define AFE_CONN24 0x047c
148 #define AFE_CONN_RS 0x0494
149 #define AFE_CONN_DI 0x0498
150 #define AFE_CONN25 0x04b0
151 #define AFE_CONN26 0x04b4
152 #define AFE_CONN27 0x04b8
153 #define AFE_CONN28 0x04bc
154 #define AFE_CONN29 0x04c0
155 #define AFE_SRAM_DELSEL_CON0 0x04f0
156 #define AFE_SRAM_DELSEL_CON1 0x04f4
157 #define AFE_ASRC_CON0 0x0500
158 #define AFE_ASRC_CON1 0x0504
159 #define AFE_ASRC_CON2 0x0508
160 #define AFE_ASRC_CON3 0x050c
161 #define AFE_ASRC_CON4 0x0510
162 #define AFE_ASRC_CON5 0x0514
163 #define AFE_ASRC_CON6 0x0518
164 #define AFE_ASRC_CON7 0x051c
165 #define AFE_ASRC_CON8 0x0520
166 #define AFE_ASRC_CON9 0x0524
167 #define AFE_ASRC_CON10 0x0528
168 #define AFE_ASRC_CON11 0x052c
169 #define PCM_INTF_CON1 0x0530
170 #define PCM_INTF_CON2 0x0538
171 #define PCM2_INTF_CON 0x053c
172 #define AFE_TDM_CON1 0x0548
173 #define AFE_TDM_CON2 0x054c
174 #define AFE_ASRC_CON13 0x0550
175 #define AFE_ASRC_CON14 0x0554
176 #define AFE_ASRC_CON15 0x0558
177 #define AFE_ASRC_CON16 0x055c
178 #define AFE_ASRC_CON17 0x0560
179 #define AFE_ASRC_CON18 0x0564
180 #define AFE_ASRC_CON19 0x0568
181 #define AFE_ASRC_CON20 0x056c
182 #define AFE_ASRC_CON21 0x0570
183 #define CLK_AUDDIV_0 0x05a0
184 #define CLK_AUDDIV_1 0x05a4
185 #define CLK_AUDDIV_2 0x05a8
186 #define CLK_AUDDIV_3 0x05ac
187 #define AUDIO_TOP_DBG_CON 0x05c8
188 #define AUDIO_TOP_DBG_MON0 0x05cc
189 #define AUDIO_TOP_DBG_MON1 0x05d0
190 #define AUDIO_TOP_DBG_MON2 0x05d4
191 #define AFE_ADDA2_TOP_CON0 0x0600
192 #define AFE_ASRC4_CON0 0x06c0
193 #define AFE_ASRC4_CON1 0x06c4
194 #define AFE_ASRC4_CON2 0x06c8
195 #define AFE_ASRC4_CON3 0x06cc
196 #define AFE_ASRC4_CON4 0x06d0
197 #define AFE_ASRC4_CON5 0x06d4
198 #define AFE_ASRC4_CON6 0x06d8
199 #define AFE_ASRC4_CON7 0x06dc
200 #define AFE_ASRC4_CON8 0x06e0
201 #define AFE_ASRC4_CON9 0x06e4
202 #define AFE_ASRC4_CON10 0x06e8
203 #define AFE_ASRC4_CON11 0x06ec
204 #define AFE_ASRC4_CON12 0x06f0
205 #define AFE_ASRC4_CON13 0x06f4
206 #define AFE_ASRC4_CON14 0x06f8
207 #define AFE_ASRC2_CON0 0x0700
208 #define AFE_ASRC2_CON1 0x0704
209 #define AFE_ASRC2_CON2 0x0708
210 #define AFE_ASRC2_CON3 0x070c
211 #define AFE_ASRC2_CON4 0x0710
212 #define AFE_ASRC2_CON5 0x0714
213 #define AFE_ASRC2_CON6 0x0718
214 #define AFE_ASRC2_CON7 0x071c
215 #define AFE_ASRC2_CON8 0x0720
216 #define AFE_ASRC2_CON9 0x0724
217 #define AFE_ASRC2_CON10 0x0728
218 #define AFE_ASRC2_CON11 0x072c
219 #define AFE_ASRC2_CON12 0x0730
220 #define AFE_ASRC2_CON13 0x0734
221 #define AFE_ASRC2_CON14 0x0738
222 #define AFE_ASRC3_CON0 0x0740
223 #define AFE_ASRC3_CON1 0x0744
224 #define AFE_ASRC3_CON2 0x0748
225 #define AFE_ASRC3_CON3 0x074c
226 #define AFE_ASRC3_CON4 0x0750
227 #define AFE_ASRC3_CON5 0x0754
228 #define AFE_ASRC3_CON6 0x0758
229 #define AFE_ASRC3_CON7 0x075c
230 #define AFE_ASRC3_CON8 0x0760
231 #define AFE_ASRC3_CON9 0x0764
232 #define AFE_ASRC3_CON10 0x0768
233 #define AFE_ASRC3_CON11 0x076c
234 #define AFE_ASRC3_CON12 0x0770
235 #define AFE_ASRC3_CON13 0x0774
236 #define AFE_ASRC3_CON14 0x0778
237 #define AFE_GENERAL_REG0 0x0800
238 #define AFE_GENERAL_REG1 0x0804
239 #define AFE_GENERAL_REG2 0x0808
240 #define AFE_GENERAL_REG3 0x080c
241 #define AFE_GENERAL_REG4 0x0810
242 #define AFE_GENERAL_REG5 0x0814
243 #define AFE_GENERAL_REG6 0x0818
244 #define AFE_GENERAL_REG7 0x081c
245 #define AFE_GENERAL_REG8 0x0820
246 #define AFE_GENERAL_REG9 0x0824
247 #define AFE_GENERAL_REG10 0x0828
248 #define AFE_GENERAL_REG11 0x082c
249 #define AFE_GENERAL_REG12 0x0830
250 #define AFE_GENERAL_REG13 0x0834
251 #define AFE_GENERAL_REG14 0x0838
252 #define AFE_GENERAL_REG15 0x083c
253 #define AFE_CBIP_CFG0 0x0840
254 #define AFE_CBIP_MON0 0x0844
255 #define AFE_CBIP_SLV_MUX_MON0 0x0848
256 #define AFE_CBIP_SLV_DECODER_MON0 0x084c
259 #define AFE_IRQ_STATUS_BITS 0x5f
263 #define AHB_IDLE_EN_INT_MASK 0x1
264 #define AHB_IDLE_EN_INT_MASK_SFT (0x1 << 30)
266 #define AHB_IDLE_EN_EXT_MASK 0x1
267 #define AHB_IDLE_EN_EXT_MASK_SFT (0x1 << 29)
269 #define PDN_TML_MASK 0x1
270 #define PDN_TML_MASK_SFT (0x1 << 27)
272 #define PDN_DAC_PREDIS_MASK 0x1
273 #define PDN_DAC_PREDIS_MASK_SFT (0x1 << 26)
275 #define PDN_DAC_MASK 0x1
276 #define PDN_DAC_MASK_SFT (0x1 << 25)
278 #define PDN_ADC_MASK 0x1
279 #define PDN_ADC_MASK_SFT (0x1 << 24)
281 #define PDN_TDM_CK_MASK 0x1
282 #define PDN_TDM_CK_MASK_SFT (0x1 << 20)
284 #define PDN_APLL_TUNER_MASK 0x1
285 #define PDN_APLL_TUNER_MASK_SFT (0x1 << 19)
287 #define PDN_APLL2_TUNER_MASK 0x1
288 #define PDN_APLL2_TUNER_MASK_SFT (0x1 << 18)
290 #define APB3_SEL_MASK 0x1
291 #define APB3_SEL_MASK_SFT (0x1 << 14)
293 #define APB_R2T_MASK 0x1
294 #define APB_R2T_MASK_SFT (0x1 << 13)
296 #define APB_W2T_MASK 0x1
297 #define APB_W2T_MASK_SFT (0x1 << 12)
299 #define PDN_24M_MASK 0x1
300 #define PDN_24M_MASK_SFT (0x1 << 9)
302 #define PDN_22M_MASK 0x1
303 #define PDN_22M_MASK_SFT (0x1 << 8)
305 #define PDN_ADDA4_ADC_MASK 0x1
306 #define PDN_ADDA4_ADC_MASK_SFT (0x1 << 7)
308 #define PDN_I2S_MASK 0x1
309 #define PDN_I2S_MASK_SFT (0x1 << 6)
311 #define PDN_AFE_MASK 0x1
312 #define PDN_AFE_MASK_SFT (0x1 << 2)
316 #define PDN_ADC_HIRES_TML_MASK 0x1
317 #define PDN_ADC_HIRES_TML_MASK_SFT (0x1 << 17)
319 #define PDN_ADC_HIRES_MASK 0x1
320 #define PDN_ADC_HIRES_MASK_SFT (0x1 << 16)
322 #define I2S4_BCLK_SW_CG_MASK 0x1
323 #define I2S4_BCLK_SW_CG_MASK_SFT (0x1 << 7)
325 #define I2S3_BCLK_SW_CG_MASK 0x1
326 #define I2S3_BCLK_SW_CG_MASK_SFT (0x1 << 6)
328 #define I2S2_BCLK_SW_CG_MASK 0x1
329 #define I2S2_BCLK_SW_CG_MASK_SFT (0x1 << 5)
331 #define I2S1_BCLK_SW_CG_MASK 0x1
332 #define I2S1_BCLK_SW_CG_MASK_SFT (0x1 << 4)
334 #define I2S_SOFT_RST2_MASK 0x1
335 #define I2S_SOFT_RST2_MASK_SFT (0x1 << 2)
337 #define I2S_SOFT_RST_MASK 0x1
338 #define I2S_SOFT_RST_MASK_SFT (0x1 << 1)
342 #define AFE_AWB_RETM_MASK 0x1
343 #define AFE_AWB_RETM_MASK_SFT (0x1 << 31)
345 #define AFE_DL1_DATA2_RETM_MASK 0x1
346 #define AFE_DL1_DATA2_RETM_MASK_SFT (0x1 << 30)
348 #define AFE_DL2_RETM_MASK 0x1
349 #define AFE_DL2_RETM_MASK_SFT (0x1 << 29)
351 #define AFE_DL1_RETM_MASK 0x1
352 #define AFE_DL1_RETM_MASK_SFT (0x1 << 28)
354 #define AFE_ON_RETM_MASK 0x1
355 #define AFE_ON_RETM_MASK_SFT (0x1 << 27)
357 #define MOD_DAI_DUP_WR_MASK 0x1
358 #define MOD_DAI_DUP_WR_MASK_SFT (0x1 << 26)
360 #define DAI_MODE_MASK 0x3
361 #define DAI_MODE_MASK_SFT (0x3 << 24)
363 #define VUL_DATA2_MODE_MASK 0xf
364 #define VUL_DATA2_MODE_MASK_SFT (0xf << 20)
366 #define DL1_DATA2_MODE_MASK 0xf
367 #define DL1_DATA2_MODE_MASK_SFT (0xf << 16)
369 #define DL3_MODE_MASK 0xf
370 #define DL3_MODE_MASK_SFT (0xf << 12)
372 #define VUL_DATA2_R_MONO_MASK 0x1
373 #define VUL_DATA2_R_MONO_MASK_SFT (0x1 << 11)
375 #define VUL_DATA2_DATA_MASK 0x1
376 #define VUL_DATA2_DATA_MASK_SFT (0x1 << 10)
378 #define VUL_DATA2_ON_MASK 0x1
379 #define VUL_DATA2_ON_MASK_SFT (0x1 << 9)
381 #define DL1_DATA2_ON_MASK 0x1
382 #define DL1_DATA2_ON_MASK_SFT (0x1 << 8)
384 #define MOD_DAI_ON_MASK 0x1
385 #define MOD_DAI_ON_MASK_SFT (0x1 << 7)
387 #define AWB_ON_MASK 0x1
388 #define AWB_ON_MASK_SFT (0x1 << 6)
390 #define DL3_ON_MASK 0x1
391 #define DL3_ON_MASK_SFT (0x1 << 5)
393 #define DAI_ON_MASK 0x1
394 #define DAI_ON_MASK_SFT (0x1 << 4)
396 #define VUL_ON_MASK 0x1
397 #define VUL_ON_MASK_SFT (0x1 << 3)
399 #define DL2_ON_MASK 0x1
400 #define DL2_ON_MASK_SFT (0x1 << 2)
402 #define DL1_ON_MASK 0x1
403 #define DL1_ON_MASK_SFT (0x1 << 1)
404 #define AFE_ON_SFT 0
405 #define AFE_ON_MASK 0x1
406 #define AFE_ON_MASK_SFT (0x1 << 0)
410 #define MOD_DAI_MODE_MASK 0x3
411 #define MOD_DAI_MODE_MASK_SFT (0x3 << 30)
413 #define DAI_DUP_WR_MASK 0x1
414 #define DAI_DUP_WR_MASK_SFT (0x1 << 29)
416 #define VUL_R_MONO_MASK 0x1
417 #define VUL_R_MONO_MASK_SFT (0x1 << 28)
419 #define VUL_DATA_MASK 0x1
420 #define VUL_DATA_MASK_SFT (0x1 << 27)
422 #define AXI_2X1_CG_DISABLE_MASK 0x1
423 #define AXI_2X1_CG_DISABLE_MASK_SFT (0x1 << 26)
425 #define AWB_R_MONO_MASK 0x1
426 #define AWB_R_MONO_MASK_SFT (0x1 << 25)
428 #define AWB_DATA_MASK 0x1
429 #define AWB_DATA_MASK_SFT (0x1 << 24)
431 #define DL3_DATA_MASK 0x1
432 #define DL3_DATA_MASK_SFT (0x1 << 23)
434 #define DL2_DATA_MASK 0x1
435 #define DL2_DATA_MASK_SFT (0x1 << 22)
437 #define DL1_DATA_MASK 0x1
438 #define DL1_DATA_MASK_SFT (0x1 << 21)
440 #define DL1_DATA2_DATA_MASK 0x1
441 #define DL1_DATA2_DATA_MASK_SFT (0x1 << 20)
443 #define VUL_MODE_MASK 0xf
444 #define VUL_MODE_MASK_SFT (0xf << 16)
446 #define AWB_MODE_MASK 0xf
447 #define AWB_MODE_MASK_SFT (0xf << 12)
449 #define I2S_MODE_MASK 0xf
450 #define I2S_MODE_MASK_SFT (0xf << 8)
452 #define DL2_MODE_MASK 0xf
453 #define DL2_MODE_MASK_SFT (0xf << 4)
454 #define DL1_MODE_SFT 0
455 #define DL1_MODE_MASK 0xf
456 #define DL1_MODE_MASK_SFT (0xf << 0)
460 #define DL_2_INPUT_MODE_CTL_MASK 0xf
461 #define DL_2_INPUT_MODE_CTL_MASK_SFT (0xf << 28)
463 #define DL_2_CH1_SATURATION_EN_CTL_MASK 0x1
464 #define DL_2_CH1_SATURATION_EN_CTL_MASK_SFT (0x1 << 27)
466 #define DL_2_CH2_SATURATION_EN_CTL_MASK 0x1
467 #define DL_2_CH2_SATURATION_EN_CTL_MASK_SFT (0x1 << 26)
469 #define DL_2_OUTPUT_SEL_CTL_MASK 0x3
470 #define DL_2_OUTPUT_SEL_CTL_MASK_SFT (0x3 << 24)
472 #define DL_2_FADEIN_0START_EN_MASK 0x3
473 #define DL_2_FADEIN_0START_EN_MASK_SFT (0x3 << 16)
475 #define DL_DISABLE_HW_CG_CTL_MASK 0x1
476 #define DL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 15)
478 #define C_DATA_EN_SEL_CTL_PRE_MASK 0x1
479 #define C_DATA_EN_SEL_CTL_PRE_MASK_SFT (0x1 << 14)
481 #define DL_2_SIDE_TONE_ON_CTL_PRE_MASK 0x1
482 #define DL_2_SIDE_TONE_ON_CTL_PRE_MASK_SFT (0x1 << 13)
484 #define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK 0x1
485 #define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK_SFT (0x1 << 12)
487 #define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK 0x1
488 #define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK_SFT (0x1 << 11)
490 #define DL2_ARAMPSP_CTL_PRE_MASK 0x3
491 #define DL2_ARAMPSP_CTL_PRE_MASK_SFT (0x3 << 9)
493 #define DL_2_IIRMODE_CTL_PRE_MASK 0x7
494 #define DL_2_IIRMODE_CTL_PRE_MASK_SFT (0x7 << 6)
496 #define DL_2_VOICE_MODE_CTL_PRE_MASK 0x1
497 #define DL_2_VOICE_MODE_CTL_PRE_MASK_SFT (0x1 << 5)
499 #define D2_2_MUTE_CH1_ON_CTL_PRE_MASK 0x1
500 #define D2_2_MUTE_CH1_ON_CTL_PRE_MASK_SFT (0x1 << 4)
502 #define D2_2_MUTE_CH2_ON_CTL_PRE_MASK 0x1
503 #define D2_2_MUTE_CH2_ON_CTL_PRE_MASK_SFT (0x1 << 3)
505 #define DL_2_IIR_ON_CTL_PRE_MASK 0x1
506 #define DL_2_IIR_ON_CTL_PRE_MASK_SFT (0x1 << 2)
508 #define DL_2_GAIN_ON_CTL_PRE_MASK 0x1
509 #define DL_2_GAIN_ON_CTL_PRE_MASK_SFT (0x1 << 1)
510 #define DL_2_SRC_ON_TMP_CTL_PRE_SFT 0
511 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK 0x1
512 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0)
516 #define DL_2_GAIN_CTL_PRE_MASK 0xffff
517 #define DL_2_GAIN_CTL_PRE_MASK_SFT (0xffff << 16)
518 #define DL_2_GAIN_MODE_CTL_SFT 0
519 #define DL_2_GAIN_MODE_CTL_MASK 0x1
520 #define DL_2_GAIN_MODE_CTL_MASK_SFT (0x1 << 0)
524 #define C_COMB_OUT_SIN_GEN_CTL_MASK 0x1
525 #define C_COMB_OUT_SIN_GEN_CTL_MASK_SFT (0x1 << 31)
527 #define C_BASEBAND_SIN_GEN_CTL_MASK 0x1
528 #define C_BASEBAND_SIN_GEN_CTL_MASK_SFT (0x1 << 30)
530 #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK 0x7
531 #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK_SFT (0x7 << 27)
533 #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK 0x7
534 #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK_SFT (0x7 << 24)
536 #define C_TWO_DIGITAL_MIC_CTL_MASK 0x1
537 #define C_TWO_DIGITAL_MIC_CTL_MASK_SFT (0x1 << 23)
539 #define UL_MODE_3P25M_CH2_CTL_MASK 0x1
540 #define UL_MODE_3P25M_CH2_CTL_MASK_SFT (0x1 << 22)
542 #define UL_MODE_3P25M_CH1_CTL_MASK 0x1
543 #define UL_MODE_3P25M_CH1_CTL_MASK_SFT (0x1 << 21)
545 #define UL_SRC_USE_CIC_OUT_CTL_MASK 0x1
546 #define UL_SRC_USE_CIC_OUT_CTL_MASK_SFT (0x1 << 20)
548 #define UL_VOICE_MODE_CH1_CH2_CTL_MASK 0x7
549 #define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT (0x7 << 17)
551 #define DMIC_LOW_POWER_MODE_CTL_MASK 0x3
552 #define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)
554 #define DMIC_48K_SEL_CTL_MASK 0x1
555 #define DMIC_48K_SEL_CTL_MASK_SFT (0x1 << 13)
557 #define UL_DISABLE_HW_CG_CTL_MASK 0x1
558 #define UL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 12)
560 #define UL_IIR_ON_TMP_CTL_MASK 0x1
561 #define UL_IIR_ON_TMP_CTL_MASK_SFT (0x1 << 10)
563 #define UL_IIRMODE_CTL_MASK 0x7
564 #define UL_IIRMODE_CTL_MASK_SFT (0x7 << 7)
566 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1
567 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)
569 #define AGC_260K_SEL_CH2_CTL_MASK 0x1
570 #define AGC_260K_SEL_CH2_CTL_MASK_SFT (0x1 << 4)
572 #define AGC_260K_SEL_CH1_CTL_MASK 0x1
573 #define AGC_260K_SEL_CH1_CTL_MASK_SFT (0x1 << 3)
575 #define UL_LOOP_BACK_MODE_CTL_MASK 0x1
576 #define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)
578 #define UL_SDM_3_LEVEL_CTL_MASK 0x1
579 #define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)
580 #define UL_SRC_ON_TMP_CTL_SFT 0
581 #define UL_SRC_ON_TMP_CTL_MASK 0x1
582 #define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)
586 #define C_SDM_RESET_CTL_MASK 0x1
587 #define C_SDM_RESET_CTL_MASK_SFT (0x1 << 31)
589 #define ADITHON_CTL_MASK 0x1
590 #define ADITHON_CTL_MASK_SFT (0x1 << 30)
592 #define ADITHVAL_CTL_MASK 0x3
593 #define ADITHVAL_CTL_MASK_SFT (0x3 << 28)
595 #define C_DAC_EN_CTL_MASK 0x1
596 #define C_DAC_EN_CTL_MASK_SFT (0x1 << 27)
598 #define C_MUTE_SW_CTL_MASK 0x1
599 #define C_MUTE_SW_CTL_MASK_SFT (0x1 << 26)
601 #define ASDM_SRC_SEL_CTL_MASK 0x1
602 #define ASDM_SRC_SEL_CTL_MASK_SFT (0x1 << 25)
604 #define C_AMP_DIV_CH2_CTL_MASK 0x7
605 #define C_AMP_DIV_CH2_CTL_MASK_SFT (0x7 << 21)
607 #define C_FREQ_DIV_CH2_CTL_MASK 0x1f
608 #define C_FREQ_DIV_CH2_CTL_MASK_SFT (0x1f << 16)
610 #define C_SINE_MODE_CH2_CTL_MASK 0xf
611 #define C_SINE_MODE_CH2_CTL_MASK_SFT (0xf << 12)
613 #define C_AMP_DIV_CH1_CTL_MASK 0x7
614 #define C_AMP_DIV_CH1_CTL_MASK_SFT (0x7 << 9)
616 #define C_FREQ_DIV_CH1_CTL_MASK 0x1f
617 #define C_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 4)
618 #define C_SINE_MODE_CH1_CTL_SFT 0
619 #define C_SINE_MODE_CH1_CTL_MASK 0xf
620 #define C_SINE_MODE_CH1_CTL_MASK_SFT (0xf << 0)
624 #define C_LOOP_BACK_MODE_CTL_MASK 0xf
625 #define C_LOOP_BACK_MODE_CTL_MASK_SFT (0xf << 12)
626 #define C_EXT_ADC_CTL_SFT 0
627 #define C_EXT_ADC_CTL_MASK 0x1
628 #define C_EXT_ADC_CTL_MASK_SFT (0x1 << 0)
632 #define AFE_UL_DL_CON0_RESERVED_MASK 0x3fff
633 #define AFE_UL_DL_CON0_RESERVED_MASK_SFT (0x3fff << 1)
634 #define ADDA_AFE_ON_SFT 0
635 #define ADDA_AFE_ON_MASK 0x1
636 #define ADDA_AFE_ON_MASK_SFT (0x1 << 0)
640 #define IRQ7_MCU_MODE_MASK 0xf
641 #define IRQ7_MCU_MODE_MASK_SFT (0xf << 24)
643 #define IRQ4_MCU_MODE_MASK 0xf
644 #define IRQ4_MCU_MODE_MASK_SFT (0xf << 20)
646 #define IRQ3_MCU_MODE_MASK 0xf
647 #define IRQ3_MCU_MODE_MASK_SFT (0xf << 16)
649 #define IRQ7_MCU_ON_MASK 0x1
650 #define IRQ7_MCU_ON_MASK_SFT (0x1 << 14)
652 #define IRQ5_MCU_ON_MASK 0x1
653 #define IRQ5_MCU_ON_MASK_SFT (0x1 << 12)
655 #define IRQ2_MCU_MODE_MASK 0xf
656 #define IRQ2_MCU_MODE_MASK_SFT (0xf << 8)
658 #define IRQ1_MCU_MODE_MASK 0xf
659 #define IRQ1_MCU_MODE_MASK_SFT (0xf << 4)
661 #define IRQ4_MCU_ON_MASK 0x1
662 #define IRQ4_MCU_ON_MASK_SFT (0x1 << 3)
664 #define IRQ3_MCU_ON_MASK 0x1
665 #define IRQ3_MCU_ON_MASK_SFT (0x1 << 2)
667 #define IRQ2_MCU_ON_MASK 0x1
668 #define IRQ2_MCU_ON_MASK_SFT (0x1 << 1)
669 #define IRQ1_MCU_ON_SFT 0
670 #define IRQ1_MCU_ON_MASK 0x1
671 #define IRQ1_MCU_ON_MASK_SFT (0x1 << 0)
675 #define AFE_IRQ_CM4_EN_MASK 0x7f
676 #define AFE_IRQ_CM4_EN_MASK_SFT (0x7f << 16)
678 #define AFE_IRQ_MD32_EN_MASK 0x7f
679 #define AFE_IRQ_MD32_EN_MASK_SFT (0x7f << 8)
680 #define AFE_IRQ_MCU_EN_SFT 0
681 #define AFE_IRQ_MCU_EN_MASK 0x7f
682 #define AFE_IRQ_MCU_EN_MASK_SFT (0x7f << 0)
686 #define IRQ7_MCU_CLR_MASK 0x1
687 #define IRQ7_MCU_CLR_MASK_SFT (0x1 << 6)
689 #define IRQ5_MCU_CLR_MASK 0x1
690 #define IRQ5_MCU_CLR_MASK_SFT (0x1 << 4)
692 #define IRQ4_MCU_CLR_MASK 0x1
693 #define IRQ4_MCU_CLR_MASK_SFT (0x1 << 3)
695 #define IRQ3_MCU_CLR_MASK 0x1
696 #define IRQ3_MCU_CLR_MASK_SFT (0x1 << 2)
698 #define IRQ2_MCU_CLR_MASK 0x1
699 #define IRQ2_MCU_CLR_MASK_SFT (0x1 << 1)
700 #define IRQ1_MCU_CLR_SFT 0
701 #define IRQ1_MCU_CLR_MASK 0x1
702 #define IRQ1_MCU_CLR_MASK_SFT (0x1 << 0)
705 #define AFE_IRQ_MCU_CNT1_SFT 0
706 #define AFE_IRQ_MCU_CNT1_MASK 0x3ffff
707 #define AFE_IRQ_MCU_CNT1_MASK_SFT (0x3ffff << 0)
710 #define AFE_IRQ_MCU_CNT2_SFT 0
711 #define AFE_IRQ_MCU_CNT2_MASK 0x3ffff
712 #define AFE_IRQ_MCU_CNT2_MASK_SFT (0x3ffff << 0)
715 #define AFE_IRQ_MCU_CNT3_SFT 0
716 #define AFE_IRQ_MCU_CNT3_MASK 0x3ffff
717 #define AFE_IRQ_MCU_CNT3_MASK_SFT (0x3ffff << 0)
720 #define AFE_IRQ_MCU_CNT4_SFT 0
721 #define AFE_IRQ_MCU_CNT4_MASK 0x3ffff
722 #define AFE_IRQ_MCU_CNT4_MASK_SFT (0x3ffff << 0)
725 #define AFE_IRQ_MCU_CNT5_SFT 0
726 #define AFE_IRQ_MCU_CNT5_MASK 0x3ffff
727 #define AFE_IRQ_MCU_CNT5_MASK_SFT (0x3ffff << 0)
730 #define AFE_IRQ_MCU_CNT7_SFT 0
731 #define AFE_IRQ_MCU_CNT7_MASK 0x3ffff
732 #define AFE_IRQ_MCU_CNT7_MASK_SFT (0x3ffff << 0)
736 #define CPU_COMPACT_MODE_MASK 0x1
737 #define CPU_COMPACT_MODE_MASK_SFT (0x1 << 23)
739 #define CPU_HD_ALIGN_MASK 0x1
740 #define CPU_HD_ALIGN_MASK_SFT (0x1 << 22)
744 #define HDMI_HD_MASK 0x3
745 #define HDMI_HD_MASK_SFT (0x3 << 20)
747 #define MOD_DAI_HD_MASK 0x3
748 #define MOD_DAI_HD_MASK_SFT (0x3 << 18)
750 #define DAI_HD_MASK 0x3
751 #define DAI_HD_MASK_SFT (0x3 << 16)
753 #define VUL_DATA2_HD_MASK 0x3
754 #define VUL_DATA2_HD_MASK_SFT (0x3 << 12)
756 #define VUL_HD_MASK 0x3
757 #define VUL_HD_MASK_SFT (0x3 << 10)
759 #define AWB_HD_MASK 0x3
760 #define AWB_HD_MASK_SFT (0x3 << 8)
762 #define DL3_HD_MASK 0x3
763 #define DL3_HD_MASK_SFT (0x3 << 6)
765 #define DL2_HD_MASK 0x3
766 #define DL2_HD_MASK_SFT (0x3 << 4)
768 #define DL1_DATA2_HD_MASK 0x3
769 #define DL1_DATA2_HD_MASK_SFT (0x3 << 2)
770 #define DL1_HD_SFT 0
771 #define DL1_HD_MASK 0x3
772 #define DL1_HD_MASK_SFT (0x3 << 0)
776 #define HDMI_NORMAL_MODE_MASK 0x1
777 #define HDMI_NORMAL_MODE_MASK_SFT (0x1 << 26)
779 #define MOD_DAI_NORMAL_MODE_MASK 0x1
780 #define MOD_DAI_NORMAL_MODE_MASK_SFT (0x1 << 25)
782 #define DAI_NORMAL_MODE_MASK 0x1
783 #define DAI_NORMAL_MODE_MASK_SFT (0x1 << 24)
785 #define VUL_DATA2_NORMAL_MODE_MASK 0x1
786 #define VUL_DATA2_NORMAL_MODE_MASK_SFT (0x1 << 22)
788 #define VUL_NORMAL_MODE_MASK 0x1
789 #define VUL_NORMAL_MODE_MASK_SFT (0x1 << 21)
791 #define AWB_NORMAL_MODE_MASK 0x1
792 #define AWB_NORMAL_MODE_MASK_SFT (0x1 << 20)
794 #define DL3_NORMAL_MODE_MASK 0x1
795 #define DL3_NORMAL_MODE_MASK_SFT (0x1 << 19)
797 #define DL2_NORMAL_MODE_MASK 0x1
798 #define DL2_NORMAL_MODE_MASK_SFT (0x1 << 18)
800 #define DL1_DATA2_NORMAL_MODE_MASK 0x1
801 #define DL1_DATA2_NORMAL_MODE_MASK_SFT (0x1 << 17)
803 #define DL1_NORMAL_MODE_MASK 0x1
804 #define DL1_NORMAL_MODE_MASK_SFT (0x1 << 16)
806 #define HDMI_HD_ALIGN_MASK 0x1
807 #define HDMI_HD_ALIGN_MASK_SFT (0x1 << 10)
809 #define MOD_DAI_HD_ALIGN_MASK 0x1
810 #define MOD_DAI_HD_ALIGN_MASK_SFT (0x1 << 9)
812 #define DAI_ALIGN_MASK 0x1
813 #define DAI_ALIGN_MASK_SFT (0x1 << 8)
815 #define VUL2_HD_ALIGN_MASK 0x1
816 #define VUL2_HD_ALIGN_MASK_SFT (0x1 << 7)
818 #define VUL_DATA2_HD_ALIGN_MASK 0x1
819 #define VUL_DATA2_HD_ALIGN_MASK_SFT (0x1 << 6)
821 #define VUL_HD_ALIGN_MASK 0x1
822 #define VUL_HD_ALIGN_MASK_SFT (0x1 << 5)
824 #define AWB_HD_ALIGN_MASK 0x1
825 #define AWB_HD_ALIGN_MASK_SFT (0x1 << 4)
827 #define DL3_HD_ALIGN_MASK 0x1
828 #define DL3_HD_ALIGN_MASK_SFT (0x1 << 3)
830 #define DL2_HD_ALIGN_MASK 0x1
831 #define DL2_HD_ALIGN_MASK_SFT (0x1 << 2)
833 #define DL1_DATA2_HD_ALIGN_MASK 0x1
834 #define DL1_DATA2_HD_ALIGN_MASK_SFT (0x1 << 1)
835 #define DL1_HD_ALIGN_SFT 0
836 #define DL1_HD_ALIGN_MASK 0x1
837 #define DL1_HD_ALIGN_MASK_SFT (0x1 << 0)
841 #define PCM_FIX_VALUE_SEL_MASK 0x1
842 #define PCM_FIX_VALUE_SEL_MASK_SFT (0x1 << 31)
844 #define PCM_BUFFER_LOOPBACK_MASK 0x1
845 #define PCM_BUFFER_LOOPBACK_MASK_SFT (0x1 << 30)
847 #define PCM_PARALLEL_LOOPBACK_MASK 0x1
848 #define PCM_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 29)
850 #define PCM_SERIAL_LOOPBACK_MASK 0x1
851 #define PCM_SERIAL_LOOPBACK_MASK_SFT (0x1 << 28)
853 #define PCM_DAI_PCM_LOOPBACK_MASK 0x1
854 #define PCM_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 27)
856 #define PCM_I2S_PCM_LOOPBACK_MASK 0x1
857 #define PCM_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 26)
859 #define PCM_SYNC_DELSEL_MASK 0x1
860 #define PCM_SYNC_DELSEL_MASK_SFT (0x1 << 25)
862 #define PCM_TX_LR_SWAP_MASK 0x1
863 #define PCM_TX_LR_SWAP_MASK_SFT (0x1 << 24)
865 #define PCM_SYNC_OUT_INV_MASK 0x1
866 #define PCM_SYNC_OUT_INV_MASK_SFT (0x1 << 23)
868 #define PCM_BCLK_OUT_INV_MASK 0x1
869 #define PCM_BCLK_OUT_INV_MASK_SFT (0x1 << 22)
871 #define PCM_SYNC_IN_INV_MASK 0x1
872 #define PCM_SYNC_IN_INV_MASK_SFT (0x1 << 21)
874 #define PCM_BCLK_IN_INV_MASK 0x1
875 #define PCM_BCLK_IN_INV_MASK_SFT (0x1 << 20)
877 #define PCM_TX_LCH_RPT_MASK 0x1
878 #define PCM_TX_LCH_RPT_MASK_SFT (0x1 << 19)
880 #define PCM_VBT_16K_MODE_MASK 0x1
881 #define PCM_VBT_16K_MODE_MASK_SFT (0x1 << 18)
883 #define PCM_EXT_MODEM_MASK 0x1
884 #define PCM_EXT_MODEM_MASK_SFT (0x1 << 17)
886 #define PCM_24BIT_MASK 0x1
887 #define PCM_24BIT_MASK_SFT (0x1 << 16)
889 #define PCM_WLEN_MASK 0x3
890 #define PCM_WLEN_MASK_SFT (0x3 << 14)
892 #define PCM_SYNC_LENGTH_MASK 0x1f
893 #define PCM_SYNC_LENGTH_MASK_SFT (0x1f << 9)
895 #define PCM_SYNC_TYPE_MASK 0x1
896 #define PCM_SYNC_TYPE_MASK_SFT (0x1 << 8)
898 #define PCM_BT_MODE_MASK 0x1
899 #define PCM_BT_MODE_MASK_SFT (0x1 << 7)
901 #define PCM_BYP_ASRC_MASK 0x1
902 #define PCM_BYP_ASRC_MASK_SFT (0x1 << 6)
904 #define PCM_SLAVE_MASK 0x1
905 #define PCM_SLAVE_MASK_SFT (0x1 << 5)
907 #define PCM_MODE_MASK 0x3
908 #define PCM_MODE_MASK_SFT (0x3 << 3)
910 #define PCM_FMT_MASK 0x3
911 #define PCM_FMT_MASK_SFT (0x3 << 1)
912 #define PCM_EN_SFT 0
913 #define PCM_EN_MASK 0x1
914 #define PCM_EN_MASK_SFT (0x1 << 0)
918 #define PCM1_TX_FIFO_OV_MASK 0x1
919 #define PCM1_TX_FIFO_OV_MASK_SFT (0x1 << 31)
921 #define PCM1_RX_FIFO_OV_MASK 0x1
922 #define PCM1_RX_FIFO_OV_MASK_SFT (0x1 << 30)
924 #define PCM2_TX_FIFO_OV_MASK 0x1
925 #define PCM2_TX_FIFO_OV_MASK_SFT (0x1 << 29)
927 #define PCM2_RX_FIFO_OV_MASK 0x1
928 #define PCM2_RX_FIFO_OV_MASK_SFT (0x1 << 28)
930 #define PCM1_SYNC_GLITCH_MASK 0x1
931 #define PCM1_SYNC_GLITCH_MASK_SFT (0x1 << 27)
933 #define PCM2_SYNC_GLITCH_MASK 0x1
934 #define PCM2_SYNC_GLITCH_MASK_SFT (0x1 << 26)
936 #define PCM1_PCM2_LOOPBACK_MASK 0x1
937 #define PCM1_PCM2_LOOPBACK_MASK_SFT (0x1 << 15)
939 #define DAI_PCM_LOOPBACK_CH_MASK 0x1
940 #define DAI_PCM_LOOPBACK_CH_MASK_SFT (0x1 << 13)
942 #define I2S_PCM_LOOPBACK_CH_MASK 0x1
943 #define I2S_PCM_LOOPBACK_CH_MASK_SFT (0x1 << 12)
945 #define PCM_USE_MD3_MASK 0x1
946 #define PCM_USE_MD3_MASK_SFT (0x1 << 8)
947 #define TX_FIX_VALUE_SFT 0
948 #define TX_FIX_VALUE_MASK 0xff
949 #define TX_FIX_VALUE_MASK_SFT (0xff << 0)
953 #define PCM2_TX_FIX_VALUE_MASK 0xff
954 #define PCM2_TX_FIX_VALUE_MASK_SFT (0xff << 24)
956 #define PCM2_FIX_VALUE_SEL_MASK 0x1
957 #define PCM2_FIX_VALUE_SEL_MASK_SFT (0x1 << 23)
959 #define PCM2_BUFFER_LOOPBACK_MASK 0x1
960 #define PCM2_BUFFER_LOOPBACK_MASK_SFT (0x1 << 22)
962 #define PCM2_PARALLEL_LOOPBACK_MASK 0x1
963 #define PCM2_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 21)
965 #define PCM2_SERIAL_LOOPBACK_MASK 0x1
966 #define PCM2_SERIAL_LOOPBACK_MASK_SFT (0x1 << 20)
968 #define PCM2_DAI_PCM_LOOPBACK_MASK 0x1
969 #define PCM2_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 19)
971 #define PCM2_I2S_PCM_LOOPBACK_MASK 0x1
972 #define PCM2_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 18)
974 #define PCM2_SYNC_DELSEL_MASK 0x1
975 #define PCM2_SYNC_DELSEL_MASK_SFT (0x1 << 17)
977 #define PCM2_TX_LR_SWAP_MASK 0x1
978 #define PCM2_TX_LR_SWAP_MASK_SFT (0x1 << 16)
980 #define PCM2_SYNC_IN_INV_MASK 0x1
981 #define PCM2_SYNC_IN_INV_MASK_SFT (0x1 << 15)
983 #define PCM2_BCLK_IN_INV_MASK 0x1
984 #define PCM2_BCLK_IN_INV_MASK_SFT (0x1 << 14)
986 #define PCM2_TX_LCH_RPT_MASK 0x1
987 #define PCM2_TX_LCH_RPT_MASK_SFT (0x1 << 13)
989 #define PCM2_VBT_16K_MODE_MASK 0x1
990 #define PCM2_VBT_16K_MODE_MASK_SFT (0x1 << 12)
992 #define PCM2_LOOPBACK_CH_SEL_MASK 0x3
993 #define PCM2_LOOPBACK_CH_SEL_MASK_SFT (0x3 << 10)
995 #define PCM2_TX2_BT_MODE_MASK 0x1
996 #define PCM2_TX2_BT_MODE_MASK_SFT (0x1 << 8)
998 #define PCM2_BT_MODE_MASK 0x1
999 #define PCM2_BT_MODE_MASK_SFT (0x1 << 7)
1001 #define PCM2_AFIFO_MASK 0x1
1002 #define PCM2_AFIFO_MASK_SFT (0x1 << 6)
1004 #define PCM2_WLEN_MASK 0x1
1005 #define PCM2_WLEN_MASK_SFT (0x1 << 5)
1007 #define PCM2_MODE_MASK 0x3
1008 #define PCM2_MODE_MASK_SFT (0x3 << 3)
1010 #define PCM2_FMT_MASK 0x3
1011 #define PCM2_FMT_MASK_SFT (0x3 << 1)
1012 #define PCM2_EN_SFT 0
1013 #define PCM2_EN_MASK 0x1
1014 #define PCM2_EN_MASK_SFT (0x1 << 0)