Lines Matching refs:i2s_path

40 		struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i];  in mt2701_init_clock()  local
45 i2s_path->sel_ck = devm_clk_get(afe->dev, name); in mt2701_init_clock()
46 if (IS_ERR(i2s_path->sel_ck)) { in mt2701_init_clock()
48 return PTR_ERR(i2s_path->sel_ck); in mt2701_init_clock()
52 i2s_path->div_ck = devm_clk_get(afe->dev, name); in mt2701_init_clock()
53 if (IS_ERR(i2s_path->div_ck)) { in mt2701_init_clock()
55 return PTR_ERR(i2s_path->div_ck); in mt2701_init_clock()
59 i2s_path->mclk_ck = devm_clk_get(afe->dev, name); in mt2701_init_clock()
60 if (IS_ERR(i2s_path->mclk_ck)) { in mt2701_init_clock()
62 return PTR_ERR(i2s_path->mclk_ck); in mt2701_init_clock()
71 i2s_path->hop_ck[SNDRV_PCM_STREAM_PLAYBACK] = i2s_ck; in mt2701_init_clock()
79 i2s_path->hop_ck[SNDRV_PCM_STREAM_CAPTURE] = i2s_ck; in mt2701_init_clock()
82 i2s_path->asrco_ck = devm_clk_get(afe->dev, name); in mt2701_init_clock()
83 if (IS_ERR(i2s_path->asrco_ck)) { in mt2701_init_clock()
85 return PTR_ERR(i2s_path->asrco_ck); in mt2701_init_clock()
102 struct mt2701_i2s_path *i2s_path, in mt2701_afe_enable_i2s() argument
107 ret = clk_prepare_enable(i2s_path->asrco_ck); in mt2701_afe_enable_i2s()
113 ret = clk_prepare_enable(i2s_path->hop_ck[dir]); in mt2701_afe_enable_i2s()
122 clk_disable_unprepare(i2s_path->asrco_ck); in mt2701_afe_enable_i2s()
128 struct mt2701_i2s_path *i2s_path, in mt2701_afe_disable_i2s() argument
131 clk_disable_unprepare(i2s_path->hop_ck[dir]); in mt2701_afe_disable_i2s()
132 clk_disable_unprepare(i2s_path->asrco_ck); in mt2701_afe_disable_i2s()
138 struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id]; in mt2701_afe_enable_mclk() local
140 return clk_prepare_enable(i2s_path->mclk_ck); in mt2701_afe_enable_mclk()
146 struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id]; in mt2701_afe_disable_mclk() local
148 clk_disable_unprepare(i2s_path->mclk_ck); in mt2701_afe_disable_mclk()
274 struct mt2701_i2s_path *i2s_path = &priv->i2s_path[id]; in mt2701_mclk_configuration() local
278 if (!(MT2701_PLL_DOMAIN_0_RATE % i2s_path->mclk_rate)) in mt2701_mclk_configuration()
279 ret = clk_set_parent(i2s_path->sel_ck, in mt2701_mclk_configuration()
281 else if (!(MT2701_PLL_DOMAIN_1_RATE % i2s_path->mclk_rate)) in mt2701_mclk_configuration()
282 ret = clk_set_parent(i2s_path->sel_ck, in mt2701_mclk_configuration()
291 ret = clk_set_rate(i2s_path->div_ck, i2s_path->mclk_rate); in mt2701_mclk_configuration()