Lines Matching refs:catpt_updatel_pci

158 	catpt_updatel_pci(cdev, VDRTCTL0, mask, new);  in catpt_dsp_set_srampge()
198 	catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 0);  in catpt_dsp_update_srampge()
203 	catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE,  in catpt_dsp_update_srampge()
236 	catpt_updatel_pci(cdev, VDRTCTL0, LPT_VDRTCTL0_APLLSE, val);  in lpt_dsp_pll_shutdown()
244 	catpt_updatel_pci(cdev, VDRTCTL2, WPT_VDRTCTL2_APLLSE, val);  in wpt_dsp_pll_shutdown()
362 	catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, PCI_D3hot);  in lpt_dsp_power_down()
375 	catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, PCI_D0);  in lpt_dsp_power_up()
398 	catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 0);  in wpt_dsp_power_down()
413 	catpt_updatel_pci(cdev, VDRTCTL2, mask, val);  in wpt_dsp_power_down()
415 	catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DTCGE,  in wpt_dsp_power_down()
424 	catpt_updatel_pci(cdev, VDRTCTL0, mask, WPT_VDRTCTL0_D3PGD);  in wpt_dsp_power_down()
426 	catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, PCI_D3hot);  in wpt_dsp_power_down()
431 	catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE,  in wpt_dsp_power_down()
443 	catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 0);  in wpt_dsp_power_up()
448 	catpt_updatel_pci(cdev, VDRTCTL2, mask, val);  in wpt_dsp_power_up()
450 	catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, PCI_D0);  in wpt_dsp_power_up()
454 	catpt_updatel_pci(cdev, VDRTCTL0, mask, mask);  in wpt_dsp_power_up()
469 	catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE,  in wpt_dsp_power_up()