Lines Matching +full:imx35 +full:- +full:spdif
1 // SPDX-License-Identifier: GPL-2.0
26 #include "imx-pcm.h"
59 * SPDIF control structure
84 * struct fsl_spdif_priv - Freescale SPDIF private data
85 * @soc: SPDIF soc data
86 * @fsl_spdif_control: SPDIF control data
144 static inline bool fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv *spdif, int clk) in fsl_spdif_can_set_clk_rate() argument
146 return (clk == STC_TXCLK_SPDIF_ROOT) && !spdif->soc->shared_root_clock; in fsl_spdif_can_set_clk_rate()
152 struct regmap *regmap = spdif_priv->regmap; in spdif_irq_dpll_lock()
153 struct platform_device *pdev = spdif_priv->pdev; in spdif_irq_dpll_lock()
159 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n", in spdif_irq_dpll_lock()
162 spdif_priv->dpll_locked = locked ? true : false; in spdif_irq_dpll_lock()
168 struct regmap *regmap = spdif_priv->regmap; in spdif_irq_sym_error()
169 struct platform_device *pdev = spdif_priv->pdev; in spdif_irq_sym_error()
171 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n"); in spdif_irq_sym_error()
174 if (!spdif_priv->dpll_locked) in spdif_irq_sym_error()
181 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_irq_uqrx_full()
182 struct regmap *regmap = spdif_priv->regmap; in spdif_irq_uqrx_full()
183 struct platform_device *pdev = spdif_priv->pdev; in spdif_irq_uqrx_full()
188 pos = &ctrl->upos; in spdif_irq_uqrx_full()
193 pos = &ctrl->qpos; in spdif_irq_uqrx_full()
198 dev_err(&pdev->dev, "unsupported channel name\n"); in spdif_irq_uqrx_full()
202 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name); in spdif_irq_uqrx_full()
207 dev_err(&pdev->dev, "User bit receive buffer overflow\n"); in spdif_irq_uqrx_full()
212 ctrl->subcode[*pos++] = val >> 16; in spdif_irq_uqrx_full()
213 ctrl->subcode[*pos++] = val >> 8; in spdif_irq_uqrx_full()
214 ctrl->subcode[*pos++] = val; in spdif_irq_uqrx_full()
220 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_irq_uq_sync()
221 struct platform_device *pdev = spdif_priv->pdev; in spdif_irq_uq_sync()
223 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n"); in spdif_irq_uq_sync()
226 if (ctrl->qpos == 0) in spdif_irq_uq_sync()
230 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1; in spdif_irq_uq_sync()
236 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_irq_uq_err()
237 struct regmap *regmap = spdif_priv->regmap; in spdif_irq_uq_err()
238 struct platform_device *pdev = spdif_priv->pdev; in spdif_irq_uq_err()
241 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n"); in spdif_irq_uq_err()
248 ctrl->ready_buf = 0; in spdif_irq_uq_err()
249 ctrl->upos = 0; in spdif_irq_uq_err()
250 ctrl->qpos = 0; in spdif_irq_uq_err()
253 /* Get spdif interrupt status and clear the interrupt */
256 struct regmap *regmap = spdif_priv->regmap; in spdif_intr_status_clear()
270 struct platform_device *pdev = spdif_priv->pdev; in spdif_isr()
279 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n"); in spdif_isr()
282 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n"); in spdif_isr()
285 dev_dbg(&pdev->dev, "isr: cstatus new\n"); in spdif_isr()
288 dev_dbg(&pdev->dev, "isr: validity flag no good\n"); in spdif_isr()
294 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n"); in spdif_isr()
300 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n"); in spdif_isr()
306 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n"); in spdif_isr()
315 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n"); in spdif_isr()
318 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n"); in spdif_isr()
325 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n"); in spdif_isr()
329 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n"); in spdif_isr()
336 struct regmap *regmap = spdif_priv->regmap; in spdif_softreset()
349 } while ((val & SCR_SOFT_RESET) && cycle--); in spdif_softreset()
358 return -EBUSY; in spdif_softreset()
364 ctrl->ch_status[3] &= ~mask; in spdif_set_cstatus()
365 ctrl->ch_status[3] |= cstatus & mask; in spdif_set_cstatus()
370 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_write_channel_status()
371 struct regmap *regmap = spdif_priv->regmap; in spdif_write_channel_status()
372 struct platform_device *pdev = spdif_priv->pdev; in spdif_write_channel_status()
375 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) | in spdif_write_channel_status()
376 (bitrev8(ctrl->ch_status[1]) << 8) | in spdif_write_channel_status()
377 bitrev8(ctrl->ch_status[2]); in spdif_write_channel_status()
380 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status); in spdif_write_channel_status()
382 ch_status = bitrev8(ctrl->ch_status[3]) << 16; in spdif_write_channel_status()
385 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status); in spdif_write_channel_status()
388 /* Set SPDIF PhaseConfig register for rx clock */
392 struct regmap *regmap = spdif_priv->regmap; in spdif_set_rx_clksrc()
393 u8 clksrc = spdif_priv->rxclk_src; in spdif_set_rx_clksrc()
396 return -EINVAL; in spdif_set_rx_clksrc()
410 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_set_sample_rate()
411 struct regmap *regmap = spdif_priv->regmap; in spdif_set_sample_rate()
412 struct platform_device *pdev = spdif_priv->pdev; in spdif_set_sample_rate()
441 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate); in spdif_set_sample_rate()
442 return -EINVAL; in spdif_set_sample_rate()
445 clk = spdif_priv->txclk_src[rate]; in spdif_set_sample_rate()
447 dev_err(&pdev->dev, "tx clock source is out of range\n"); in spdif_set_sample_rate()
448 return -EINVAL; in spdif_set_sample_rate()
451 txclk_df = spdif_priv->txclk_df[rate]; in spdif_set_sample_rate()
453 dev_err(&pdev->dev, "the txclk_df can't be zero\n"); in spdif_set_sample_rate()
454 return -EINVAL; in spdif_set_sample_rate()
457 sysclk_df = spdif_priv->sysclk_df[rate]; in spdif_set_sample_rate()
463 ret = clk_set_rate(spdif_priv->txclk[rate], in spdif_set_sample_rate()
466 dev_err(&pdev->dev, "failed to set tx clock rate\n"); in spdif_set_sample_rate()
471 dev_dbg(&pdev->dev, "expected clock rate = %d\n", in spdif_set_sample_rate()
473 dev_dbg(&pdev->dev, "actual clock rate = %ld\n", in spdif_set_sample_rate()
474 clk_get_rate(spdif_priv->txclk[rate])); in spdif_set_sample_rate()
486 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n", in spdif_set_sample_rate()
487 spdif_priv->txrate[rate], sample_rate); in spdif_set_sample_rate()
497 struct platform_device *pdev = spdif_priv->pdev; in fsl_spdif_startup()
498 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_startup()
506 dev_err(&pdev->dev, "failed to soft reset\n"); in fsl_spdif_startup()
514 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { in fsl_spdif_startup()
528 /* Power up SPDIF module */ in fsl_spdif_startup()
539 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_shutdown()
542 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { in fsl_spdif_shutdown()
554 /* Power down SPDIF module only if tx&rx are both inactive */ in fsl_spdif_shutdown()
568 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_hw_params()
569 struct platform_device *pdev = spdif_priv->pdev; in fsl_spdif_hw_params()
573 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { in fsl_spdif_hw_params()
576 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n", in fsl_spdif_hw_params()
596 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_trigger()
597 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_spdif_trigger()
615 return -EINVAL; in fsl_spdif_trigger()
630 * FSL SPDIF IEC958 controller(mixer) functions
642 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; in fsl_spdif_info()
643 uinfo->count = 1; in fsl_spdif_info()
653 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_pb_get()
655 uvalue->value.iec958.status[0] = ctrl->ch_status[0]; in fsl_spdif_pb_get()
656 uvalue->value.iec958.status[1] = ctrl->ch_status[1]; in fsl_spdif_pb_get()
657 uvalue->value.iec958.status[2] = ctrl->ch_status[2]; in fsl_spdif_pb_get()
658 uvalue->value.iec958.status[3] = ctrl->ch_status[3]; in fsl_spdif_pb_get()
668 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_pb_put()
670 ctrl->ch_status[0] = uvalue->value.iec958.status[0]; in fsl_spdif_pb_put()
671 ctrl->ch_status[1] = uvalue->value.iec958.status[1]; in fsl_spdif_pb_put()
672 ctrl->ch_status[2] = uvalue->value.iec958.status[2]; in fsl_spdif_pb_put()
673 ctrl->ch_status[3] = uvalue->value.iec958.status[3]; in fsl_spdif_pb_put()
686 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_capture_get()
691 return -EAGAIN; in fsl_spdif_capture_get()
694 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF; in fsl_spdif_capture_get()
695 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF; in fsl_spdif_capture_get()
696 ucontrol->value.iec958.status[2] = cstatus & 0xFF; in fsl_spdif_capture_get()
699 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF; in fsl_spdif_capture_get()
700 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF; in fsl_spdif_capture_get()
701 ucontrol->value.iec958.status[5] = cstatus & 0xFF; in fsl_spdif_capture_get()
718 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_subcode_get()
720 int ret = -EAGAIN; in fsl_spdif_subcode_get()
722 spin_lock_irqsave(&ctrl->ctl_lock, flags); in fsl_spdif_subcode_get()
723 if (ctrl->ready_buf) { in fsl_spdif_subcode_get()
724 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE; in fsl_spdif_subcode_get()
725 memcpy(&ucontrol->value.iec958.subcode[0], in fsl_spdif_subcode_get()
726 &ctrl->subcode[idx], SPDIF_UBITS_SIZE); in fsl_spdif_subcode_get()
729 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); in fsl_spdif_subcode_get()
734 /* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */
738 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; in fsl_spdif_qinfo()
739 uinfo->count = SPDIF_QSUB_SIZE; in fsl_spdif_qinfo()
750 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_qget()
752 int ret = -EAGAIN; in fsl_spdif_qget()
754 spin_lock_irqsave(&ctrl->ctl_lock, flags); in fsl_spdif_qget()
755 if (ctrl->ready_buf) { in fsl_spdif_qget()
756 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE; in fsl_spdif_qget()
757 memcpy(&ucontrol->value.bytes.data[0], in fsl_spdif_qget()
758 &ctrl->qsub[idx], SPDIF_QSUB_SIZE); in fsl_spdif_qget()
761 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); in fsl_spdif_qget()
770 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; in fsl_spdif_vbit_info()
771 uinfo->count = 1; in fsl_spdif_vbit_info()
772 uinfo->value.integer.min = 0; in fsl_spdif_vbit_info()
773 uinfo->value.integer.max = 1; in fsl_spdif_vbit_info()
784 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_rx_vbit_get()
788 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0; in fsl_spdif_rx_vbit_get()
799 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_tx_vbit_get()
804 val = 1 - val; in fsl_spdif_tx_vbit_get()
805 ucontrol->value.integer.value[0] = val; in fsl_spdif_tx_vbit_get()
815 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_tx_vbit_put()
816 u32 val = (1 - ucontrol->value.integer.value[0]) << SCR_VAL_OFFSET; in fsl_spdif_tx_vbit_put()
827 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; in fsl_spdif_rxrate_info()
828 uinfo->count = 1; in fsl_spdif_rxrate_info()
829 uinfo->value.integer.min = 16000; in fsl_spdif_rxrate_info()
830 uinfo->value.integer.max = 96000; in fsl_spdif_rxrate_info()
839 /* Get RX data clock rate given the SPDIF bus_clk */
843 struct regmap *regmap = spdif_priv->regmap; in spdif_get_rxclk_rate()
844 struct platform_device *pdev = spdif_priv->pdev; in spdif_get_rxclk_rate()
856 busclk_freq = clk_get_rate(spdif_priv->sysclk); in spdif_get_rxclk_rate()
863 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas); in spdif_get_rxclk_rate()
864 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq); in spdif_get_rxclk_rate()
865 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64); in spdif_get_rxclk_rate()
882 if (spdif_priv->dpll_locked) in fsl_spdif_rxrate_get()
885 ucontrol->value.integer.value[0] = rate; in fsl_spdif_rxrate_get()
894 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; in fsl_spdif_usync_info()
895 uinfo->count = 1; in fsl_spdif_usync_info()
896 uinfo->value.integer.min = 0; in fsl_spdif_usync_info()
897 uinfo->value.integer.max = 1; in fsl_spdif_usync_info()
905 * 0 Non-CD data
912 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_usync_get()
916 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0; in fsl_spdif_usync_get()
924 * 0 Non-CD data
931 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_usync_put()
932 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET; in fsl_spdif_usync_put()
939 /* FSL SPDIF IEC958 controller defines */
971 .name = "IEC958 Q-subcode Capture Default",
980 .name = "IEC958 RX V-Bit Errors",
988 .name = "IEC958 TX V-Bit",
1022 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx, in fsl_spdif_dai_probe()
1023 &spdif_private->dma_params_rx); in fsl_spdif_dai_probe()
1028 regmap_update_bits(spdif_private->regmap, REG_SPDIF_SCR, in fsl_spdif_dai_probe()
1037 .stream_name = "CPU-Playback",
1044 .stream_name = "CPU-Capture",
1054 .name = "fsl-spdif",
1057 /* FSL SPDIF REGMAP */
1149 bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk); in fsl_spdif_txclk_caldiv()
1173 spdif_priv->txclk_df[index] = txclk_df; in fsl_spdif_txclk_caldiv()
1174 spdif_priv->sysclk_df[index] = sysclk_df; in fsl_spdif_txclk_caldiv()
1175 spdif_priv->txrate[index] = arate; in fsl_spdif_txclk_caldiv()
1179 sub = (u64)(arate - rate[index]) * 100000; in fsl_spdif_txclk_caldiv()
1184 spdif_priv->txclk_df[index] = txclk_df; in fsl_spdif_txclk_caldiv()
1185 spdif_priv->sysclk_df[index] = sysclk_df; in fsl_spdif_txclk_caldiv()
1186 spdif_priv->txrate[index] = arate; in fsl_spdif_txclk_caldiv()
1189 sub = (u64)(rate[index] - arate) * 100000; in fsl_spdif_txclk_caldiv()
1194 spdif_priv->txclk_df[index] = txclk_df; in fsl_spdif_txclk_caldiv()
1195 spdif_priv->sysclk_df[index] = sysclk_df; in fsl_spdif_txclk_caldiv()
1196 spdif_priv->txrate[index] = arate; in fsl_spdif_txclk_caldiv()
1209 struct platform_device *pdev = spdif_priv->pdev; in fsl_spdif_probe_txclk()
1210 struct device *dev = &pdev->dev; in fsl_spdif_probe_txclk()
1218 clk = devm_clk_get(&pdev->dev, tmp); in fsl_spdif_probe_txclk()
1232 spdif_priv->txclk[index] = clk; in fsl_spdif_probe_txclk()
1233 spdif_priv->txclk_src[index] = i; in fsl_spdif_probe_txclk()
1240 dev_dbg(&pdev->dev, "use rxtx%d as tx clock source for %dHz sample rate\n", in fsl_spdif_probe_txclk()
1241 spdif_priv->txclk_src[index], rate[index]); in fsl_spdif_probe_txclk()
1242 dev_dbg(&pdev->dev, "use txclk df %d for %dHz sample rate\n", in fsl_spdif_probe_txclk()
1243 spdif_priv->txclk_df[index], rate[index]); in fsl_spdif_probe_txclk()
1244 if (clk_is_match(spdif_priv->txclk[index], spdif_priv->sysclk)) in fsl_spdif_probe_txclk()
1245 dev_dbg(&pdev->dev, "use sysclk df %d for %dHz sample rate\n", in fsl_spdif_probe_txclk()
1246 spdif_priv->sysclk_df[index], rate[index]); in fsl_spdif_probe_txclk()
1247 dev_dbg(&pdev->dev, "the best rate for %dHz sample rate is %dHz\n", in fsl_spdif_probe_txclk()
1248 rate[index], spdif_priv->txrate[index]); in fsl_spdif_probe_txclk()
1261 spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL); in fsl_spdif_probe()
1263 return -ENOMEM; in fsl_spdif_probe()
1265 spdif_priv->pdev = pdev; in fsl_spdif_probe()
1267 spdif_priv->soc = of_device_get_match_data(&pdev->dev); in fsl_spdif_probe()
1268 if (!spdif_priv->soc) { in fsl_spdif_probe()
1269 dev_err(&pdev->dev, "failed to get soc data\n"); in fsl_spdif_probe()
1270 return -ENODEV; in fsl_spdif_probe()
1274 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai)); in fsl_spdif_probe()
1275 spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev); in fsl_spdif_probe()
1279 regs = devm_ioremap_resource(&pdev->dev, res); in fsl_spdif_probe()
1283 spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, in fsl_spdif_probe()
1285 if (IS_ERR(spdif_priv->regmap)) { in fsl_spdif_probe()
1286 dev_err(&pdev->dev, "regmap init failed\n"); in fsl_spdif_probe()
1287 return PTR_ERR(spdif_priv->regmap); in fsl_spdif_probe()
1294 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0, in fsl_spdif_probe()
1295 dev_name(&pdev->dev), spdif_priv); in fsl_spdif_probe()
1297 dev_err(&pdev->dev, "could not claim irq %u\n", irq); in fsl_spdif_probe()
1302 spdif_priv->sysclk = devm_clk_get(&pdev->dev, "rxtx5"); in fsl_spdif_probe()
1303 if (IS_ERR(spdif_priv->sysclk)) { in fsl_spdif_probe()
1304 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n"); in fsl_spdif_probe()
1305 return PTR_ERR(spdif_priv->sysclk); in fsl_spdif_probe()
1309 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core"); in fsl_spdif_probe()
1310 if (IS_ERR(spdif_priv->coreclk)) { in fsl_spdif_probe()
1311 dev_err(&pdev->dev, "no core clock in devicetree\n"); in fsl_spdif_probe()
1312 return PTR_ERR(spdif_priv->coreclk); in fsl_spdif_probe()
1315 spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba"); in fsl_spdif_probe()
1316 if (IS_ERR(spdif_priv->spbaclk)) in fsl_spdif_probe()
1317 dev_warn(&pdev->dev, "no spba clock in devicetree\n"); in fsl_spdif_probe()
1320 spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1"); in fsl_spdif_probe()
1321 if (IS_ERR(spdif_priv->rxclk)) { in fsl_spdif_probe()
1322 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n"); in fsl_spdif_probe()
1323 return PTR_ERR(spdif_priv->rxclk); in fsl_spdif_probe()
1325 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC; in fsl_spdif_probe()
1334 ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_probe()
1335 spin_lock_init(&ctrl->ctl_lock); in fsl_spdif_probe()
1338 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT | in fsl_spdif_probe()
1340 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID; in fsl_spdif_probe()
1341 ctrl->ch_status[2] = 0x00; in fsl_spdif_probe()
1342 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 | in fsl_spdif_probe()
1345 spdif_priv->dpll_locked = false; in fsl_spdif_probe()
1347 spdif_priv->dma_params_tx.maxburst = FSL_SPDIF_TXFIFO_WML; in fsl_spdif_probe()
1348 spdif_priv->dma_params_rx.maxburst = FSL_SPDIF_RXFIFO_WML; in fsl_spdif_probe()
1349 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL; in fsl_spdif_probe()
1350 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL; in fsl_spdif_probe()
1353 dev_set_drvdata(&pdev->dev, spdif_priv); in fsl_spdif_probe()
1354 pm_runtime_enable(&pdev->dev); in fsl_spdif_probe()
1355 regcache_cache_only(spdif_priv->regmap, true); in fsl_spdif_probe()
1357 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component, in fsl_spdif_probe()
1358 &spdif_priv->cpu_dai_drv, 1); in fsl_spdif_probe()
1360 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); in fsl_spdif_probe()
1365 if (ret && ret != -EPROBE_DEFER) in fsl_spdif_probe()
1366 dev_err(&pdev->dev, "imx_pcm_dma_init failed: %d\n", ret); in fsl_spdif_probe()
1377 regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC, in fsl_spdif_runtime_suspend()
1378 &spdif_priv->regcache_srpc); in fsl_spdif_runtime_suspend()
1379 regcache_cache_only(spdif_priv->regmap, true); in fsl_spdif_runtime_suspend()
1381 clk_disable_unprepare(spdif_priv->rxclk); in fsl_spdif_runtime_suspend()
1384 clk_disable_unprepare(spdif_priv->txclk[i]); in fsl_spdif_runtime_suspend()
1386 if (!IS_ERR(spdif_priv->spbaclk)) in fsl_spdif_runtime_suspend()
1387 clk_disable_unprepare(spdif_priv->spbaclk); in fsl_spdif_runtime_suspend()
1388 clk_disable_unprepare(spdif_priv->coreclk); in fsl_spdif_runtime_suspend()
1399 ret = clk_prepare_enable(spdif_priv->coreclk); in fsl_spdif_runtime_resume()
1405 if (!IS_ERR(spdif_priv->spbaclk)) { in fsl_spdif_runtime_resume()
1406 ret = clk_prepare_enable(spdif_priv->spbaclk); in fsl_spdif_runtime_resume()
1414 ret = clk_prepare_enable(spdif_priv->txclk[i]); in fsl_spdif_runtime_resume()
1419 ret = clk_prepare_enable(spdif_priv->rxclk); in fsl_spdif_runtime_resume()
1423 regcache_cache_only(spdif_priv->regmap, false); in fsl_spdif_runtime_resume()
1424 regcache_mark_dirty(spdif_priv->regmap); in fsl_spdif_runtime_resume()
1426 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC, in fsl_spdif_runtime_resume()
1428 spdif_priv->regcache_srpc); in fsl_spdif_runtime_resume()
1430 ret = regcache_sync(spdif_priv->regmap); in fsl_spdif_runtime_resume()
1437 clk_disable_unprepare(spdif_priv->rxclk); in fsl_spdif_runtime_resume()
1439 for (i--; i >= 0; i--) in fsl_spdif_runtime_resume()
1440 clk_disable_unprepare(spdif_priv->txclk[i]); in fsl_spdif_runtime_resume()
1441 if (!IS_ERR(spdif_priv->spbaclk)) in fsl_spdif_runtime_resume()
1442 clk_disable_unprepare(spdif_priv->spbaclk); in fsl_spdif_runtime_resume()
1444 clk_disable_unprepare(spdif_priv->coreclk); in fsl_spdif_runtime_resume()
1458 { .compatible = "fsl,imx35-spdif", .data = &fsl_spdif_imx35, },
1459 { .compatible = "fsl,vf610-spdif", .data = &fsl_spdif_vf610, },
1460 { .compatible = "fsl,imx6sx-spdif", .data = &fsl_spdif_imx6sx, },
1467 .name = "fsl-spdif-dai",
1479 MODULE_ALIAS("platform:fsl-spdif-dai");