22 /* ASRC Context Control Extended 1 */
68 /* ASRC Channel Status 1 */
98 #define EASRC_CC_FIFO_WTMK_MASK		((BIT(EASRC_CC_FIFO_WTMK_WIDTH) - 1) \
100 #define EASRC_CC_FIFO_WTMK(v)		(((v) << EASRC_CC_FIFO_WTMK_SHIFT) \  argument
104 #define EASRC_CC_SAMPLE_POS_MASK	((BIT(EASRC_CC_SAMPLE_POS_WIDTH) - 1) \
106 #define EASRC_CC_SAMPLE_POS(v)		(((v) << EASRC_CC_SAMPLE_POS_SHIFT) \  argument
113 #define EASRC_CC_BPS_MASK		((BIT(EASRC_CC_BPS_WIDTH) - 1) \
115 #define EASRC_CC_BPS(v)			(((v) << EASRC_CC_BPS_SHIFT) \  argument
125 #define EASRC_CC_CHEN_MASK		((BIT(EASRC_CC_CHEN_WIDTH) - 1) \
127 #define EASRC_CC_CHEN(v)		(((v) << EASRC_CC_CHEN_SHIFT) \  argument
130 /* ASRC Context Control Extended 1 (CCE1) */
139 #define EASRC_CCE1_PF_EXP_MASK		((BIT(EASRC_CCE1_PF_EXP_WIDTH) - 1) \
141 #define EASRC_CCE1_PF_EXP(v)		(((v) << EASRC_CCE1_PF_EXP_SHIFT) \  argument
163 #define EASRC_CCE1_RS_INIT_MASK		((BIT(EASRC_CCE1_RS_INIT_WIDTH) - 1) \
165 #define EASRC_CCE1_RS_INIT(v)		(((v) << EASRC_CCE1_RS_INIT_SHIFT) \  argument
169 #define EASRC_CCE1_PF_INIT_MASK		((BIT(EASRC_CCE1_PF_INIT_WIDTH) - 1) \
171 #define EASRC_CCE1_PF_INIT(v)		(((v) << EASRC_CCE1_PF_INIT_SHIFT) \  argument
177 #define EASRC_CCE2_ST2_TAPS_MASK	((BIT(EASRC_CCE2_ST2_TAPS_WIDTH) - 1) \
179 #define EASRC_CCE2_ST2_TAPS(v)		(((v) << EASRC_CCE2_ST2_TAPS_SHIFT) \  argument
183 #define EASRC_CCE2_ST1_TAPS_MASK	((BIT(EASRC_CCE2_ST1_TAPS_WIDTH) - 1) \
185 #define EASRC_CCE2_ST1_TAPS(v)		(((v) << EASRC_CCE2_ST1_TAPS_SHIFT) \  argument
191 #define EASRC_CIA_ITER_MASK		((BIT(EASRC_CIA_ITER_WIDTH) - 1) \
193 #define EASRC_CIA_ITER(v)		(((v) << EASRC_CIA_ITER_SHIFT) \  argument
197 #define EASRC_CIA_GRLEN_MASK		((BIT(EASRC_CIA_GRLEN_WIDTH) - 1) \
199 #define EASRC_CIA_GRLEN(v)		(((v) << EASRC_CIA_GRLEN_SHIFT) \  argument
203 #define EASRC_CIA_ACCLEN_MASK		((BIT(EASRC_CIA_ACCLEN_WIDTH) - 1) \
205 #define EASRC_CIA_ACCLEN(v)		(((v) << EASRC_CIA_ACCLEN_SHIFT) \  argument
211 #define EASRC_DPCS0R0_MAXCH_MASK	((BIT(EASRC_DPCS0R0_MAXCH_WIDTH) - 1) \
213 #define EASRC_DPCS0R0_MAXCH(v)		(((v) << EASRC_DPCS0R0_MAXCH_SHIFT) \  argument
217 #define EASRC_DPCS0R0_MINCH_MASK	((BIT(EASRC_DPCS0R0_MINCH_WIDTH) - 1) \
219 #define EASRC_DPCS0R0_MINCH(v)		(((v) << EASRC_DPCS0R0_MINCH_SHIFT) \  argument
223 #define EASRC_DPCS0R0_NUMCH_MASK	((BIT(EASRC_DPCS0R0_NUMCH_WIDTH) - 1) \
225 #define EASRC_DPCS0R0_NUMCH(v)		(((v) << EASRC_DPCS0R0_NUMCH_SHIFT) \  argument
227 #define EASRC_DPCS0R0_CTXNUM_SHIFT	1
229 #define EASRC_DPCS0R0_CTXNUM_MASK	((BIT(EASRC_DPCS0R0_CTXNUM_WIDTH) - 1) \
231 #define EASRC_DPCS0R0_CTXNUM(v)		(((v) << EASRC_DPCS0R0_CTXNUM_SHIFT) \  argument
240 #define EASRC_DPCS0R1_ST1_EXP_MASK	((BIT(EASRC_DPCS0R1_ST1_EXP_WIDTH) - 1) \
242 #define EASRC_DPCS0R1_ST1_EXP(v)	(((v) << EASRC_DPCS0R1_ST1_EXP_SHIFT) \  argument
248 #define EASRC_DPCS0R2_ST1_MA_MASK	((BIT(EASRC_DPCS0R2_ST1_MA_WIDTH) - 1) \
250 #define EASRC_DPCS0R2_ST1_MA(v)		(((v) << EASRC_DPCS0R2_ST1_MA_SHIFT) \  argument
254 #define EASRC_DPCS0R2_ST1_SA_MASK	((BIT(EASRC_DPCS0R2_ST1_SA_WIDTH) - 1) \
256 #define EASRC_DPCS0R2_ST1_SA(v)		(((v) << EASRC_DPCS0R2_ST1_SA_SHIFT) \  argument
262 #define EASRC_DPCS0R3_ST2_MA_MASK	((BIT(EASRC_DPCS0R3_ST2_MA_WIDTH) - 1) \
264 #define EASRC_DPCS0R3_ST2_MA(v)		(((v) << EASRC_DPCS0R3_ST2_MA_SHIFT) \  argument
268 #define EASRC_DPCS0R3_ST2_SA_MASK	((BIT(EASRC_DPCS0R3_ST2_SA_WIDTH) - 1) \
270 #define EASRC_DPCS0R3_ST2_SA(v)		(((v) << EASRC_DPCS0R3_ST2_SA_SHIFT) \  argument
279 #define EASRC_COC_FIFO_WTMK_MASK	((BIT(EASRC_COC_FIFO_WTMK_WIDTH) - 1) \
281 #define EASRC_COC_FIFO_WTMK(v)		(((v) << EASRC_COC_FIFO_WTMK_SHIFT) \  argument
285 #define EASRC_COC_SAMPLE_POS_MASK	((BIT(EASRC_COC_SAMPLE_POS_WIDTH) - 1) \
287 #define EASRC_COC_SAMPLE_POS(v)		(((v) << EASRC_COC_SAMPLE_POS_SHIFT) \  argument
294 #define EASRC_COC_BPS_MASK		((BIT(EASRC_COC_BPS_WIDTH) - 1) \
296 #define EASRC_COC_BPS(v)		(((v) << EASRC_COC_BPS_SHIFT) \  argument
307 #define EASRC_COC_IEC_EN_SHIFT		1
317 #define EASRC_COA_ITER_MASK		((BIT(EASRC_COA_ITER_WIDTH) - 1) \
319 #define EASRC_COA_ITER(v)		(((v) << EASRC_COA_ITER_SHIFT) \  argument
323 #define EASRC_COA_GRLEN_MASK		((BIT(EASRC_COA_GRLEN_WIDTH) - 1) \
325 #define EASRC_COA_GRLEN(v)		(((v) << EASRC_COA_GRLEN_SHIFT) \  argument
329 #define EASRC_COA_ACCLEN_MASK		((BIT(EASRC_COA_ACCLEN_WIDTH) - 1) \
331 #define EASRC_COA_ACCLEN(v)		(((v) << EASRC_COA_ACCLEN_SHIFT) \  argument
340 #define EASRC_SFS_NSGI_MASK		((BIT(EASRC_SFS_NSGI_WIDTH) - 1) \
342 #define EASRC_SFS_NSGI(v)		(((v) << EASRC_SFS_NSGI_SHIFT) \  argument
349 #define EASRC_SFS_NSGO_MASK		((BIT(EASRC_SFS_NSGO_WIDTH) - 1) \
351 #define EASRC_SFS_NSGO(v)		(((v) << EASRC_SFS_NSGO_SHIFT) \  argument
357 #define EASRC_RRL_RS_RL(v)		((v) << EASRC_RRL_RS_RL_SHIFT)  argument
365 #define EASRC_RRH_RS_RH_MASK		((BIT(EASRC_RRH_RS_RH_WIDTH) - 1) \
367 #define EASRC_RRH_RS_RH(v)		(((v) << EASRC_RRH_RS_RH_SHIFT) \  argument
373 #define EASRC_RSUC_RS_RM(v)		((v) << EASRC_RSUC_RS_RM_SHIFT)  argument
378 #define EASRC_RRUR_RRR_MASK		((BIT(EASRC_RRUR_RRR_WIDTH) - 1) \
380 #define EASRC_RRUR_RRR(v)		(((v) << EASRC_RRUR_RRR_SHIFT) \  argument
386 #define EASRC_RCTCL_RS_CL(v)		((v) << EASRC_RCTCL_RS_CL_SHIFT)  argument
391 #define EASRC_RCTCH_RS_CH(v)		((v) << EASRC_RCTCH_RS_CH_SHIFT)  argument
396 #define EASRC_PCF_CD(v)			((v) << EASRC_PCF_CD_SHIFT)  argument
401 #define EASRC_CRCM_RS_CWD(v)		((v) << EASRC_CRCM_RS_CWD_SHIFT)  argument
406 #define EASRC_CRCC_RS_CA_MASK		((BIT(EASRC_CRCC_RS_CA_WIDTH) - 1) \
408 #define EASRC_CRCC_RS_CA(v)		(((v) << EASRC_CRCC_RS_CA_SHIFT) \  argument
410 #define EASRC_CRCC_RS_TAPS_SHIFT	1
412 #define EASRC_CRCC_RS_TAPS_MASK		((BIT(EASRC_CRCC_RS_TAPS_WIDTH) - 1) \
414 #define EASRC_CRCC_RS_TAPS(v)		(((v) << EASRC_CRCC_RS_TAPS_SHIFT) \  argument
423 #define EASRC_IRQC_RSDM_MASK		((BIT(EASRC_IRQC_RSDM_WIDTH) - 1) \
425 #define EASRC_IRQC_RSDM(v)		(((v) << EASRC_IRQC_RSDM_SHIFT) \  argument
429 #define EASRC_IRQC_OERM_MASK		((BIT(EASRC_IRQC_OERM_WIDTH) - 1) \
431 #define EASRC_IRQC_OERM(v)		(((v) << EASRC_IRQC_OERM_SHIFT) \  argument
435 #define EASRC_IRQC_IOM_MASK		((BIT(EASRC_IRQC_IOM_WIDTH) - 1) \
437 #define EASRC_IRQC_IOM(v)		(((v) << EASRC_IRQC_IOM_SHIFT) \  argument
443 #define EASRC_IRQF_RSD_MASK		((BIT(EASRC_IRQF_RSD_WIDTH) - 1) \
445 #define EASRC_IRQF_RSD(v)		(((v) << EASRC_IRQF_RSD_SHIFT) \  argument
449 #define EASRC_IRQF_OER_MASK		((BIT(EASRC_IRQF_OER_WIDTH) - 1) \
451 #define EASRC_IRQF_OER(v)		(((v) << EASRC_IRQF_OER_SHIFT) \  argument
455 #define EASRC_IRQF_IFO_MASK		((BIT(EASRC_IRQF_IFO_WIDTH) - 1) \
457 #define EASRC_IRQF_IFO(v)		(((v) << EASRC_IRQF_IFO_SHIFT) \  argument
463 #define EASRC_CSx_CSx(v)		((v) << EASRC_CSx_CSx_SHIFT)  argument
468 #define EASRC_DBGC_DMS_MASK		((BIT(EASRC_DBGC_DMS_WIDTH) - 1) \
470 #define EASRC_DBGC_DMS(v)		(((v) << EASRC_DBGC_DMS_SHIFT) \  argument
476 #define EASRC_DBGS_DS(v)		((v) << EASRC_DBGS_DS_SHIFT)  argument
481 #define EASRC_PF_COEFF_MEM		1
485 #define EASRC_PF_TWO_STAGE_MODE		1
487 #define EASRC_PF_ST2_COEFF_WR		1
492 #define EASRC_RS_64_TAPS		1
497 #define EASRC_INIT_MODE_REPLICATE	1
513 #define FIRMWARE_VERSION		1
519 	EASRC_WIDTH_20_BIT = 1,
557 	unsigned int endianness : 1;
558 	unsigned int unsign : 1;
559 	unsigned int floating_point : 1;
560 	unsigned int iec958: 1;
591  * @st1_num_taps: tap number of stage 1
593  * @st1_num_exp: exponent number of stage 1
598  * @st1_coeff: pointer of stage 1 coeff