Lines Matching +full:8 +full:- +full:channel
1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * - implement DAPM and input muxing
9 * - implement modulation limit
10 * - implement non-default PWM start
13 * because the registers are of unequal size, and multi-byte registers
18 * it doesn't matter because the entire map can be accessed as 8-bit
21 * routines have to be open-coded.
71 #define TAS5086_CHANNEL_VOL(X) (0x08 + (X)) /* Channel 1-6 volume */
89 * Default TAS5086 power-up configuration
173 size = tas5086_register_size(&client->dev, reg); in tas5086_reg_write()
175 return -EINVAL; in tas5086_reg_write()
179 for (i = size; i >= 1; --i) { in tas5086_reg_write()
181 value >>= 8; in tas5086_reg_write()
190 return -EIO; in tas5086_reg_write()
203 size = tas5086_register_size(&client->dev, reg); in tas5086_reg_read()
205 return -EINVAL; in tas5086_reg_read()
209 msgs[0].addr = client->addr; in tas5086_reg_read()
214 msgs[1].addr = client->addr; in tas5086_reg_read()
219 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); in tas5086_reg_read()
223 return -EIO; in tas5086_reg_read()
228 *value <<= 8; in tas5086_reg_read()
246 /* Current sample rate for de-emphasis control */
260 if (priv->deemph) { in tas5086_set_deemph()
262 if (tas5086_deemph[i] == priv->rate) { in tas5086_set_deemph()
269 return regmap_update_bits(priv->regmap, TAS5086_SYS_CONTROL_1, in tas5086_set_deemph()
279 ucontrol->value.integer.value[0] = priv->deemph; in tas5086_get_deemph()
290 priv->deemph = ucontrol->value.integer.value[0]; in tas5086_put_deemph()
299 struct snd_soc_component *component = codec_dai->component; in tas5086_set_dai_sysclk()
304 priv->mclk = freq; in tas5086_set_dai_sysclk()
307 priv->sclk = freq; in tas5086_set_dai_sysclk()
317 struct snd_soc_component *component = codec_dai->component; in tas5086_set_dai_fmt()
322 dev_err(component->dev, "Invalid clocking mode\n"); in tas5086_set_dai_fmt()
323 return -EINVAL; in tas5086_set_dai_fmt()
327 priv->format = format; in tas5086_set_dai_fmt()
348 return -ENOENT; in index_in_array()
355 struct snd_soc_component *component = dai->component; in tas5086_hw_params()
360 priv->rate = params_rate(params); in tas5086_hw_params()
364 ARRAY_SIZE(tas5086_sample_rates), priv->rate); in tas5086_hw_params()
367 dev_err(component->dev, "Invalid sample rate\n"); in tas5086_hw_params()
368 return -EINVAL; in tas5086_hw_params()
371 ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL, in tas5086_hw_params()
379 priv->mclk / priv->rate); in tas5086_hw_params()
381 dev_err(component->dev, "Invalid MCLK / Fs ratio\n"); in tas5086_hw_params()
382 return -EINVAL; in tas5086_hw_params()
385 ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL, in tas5086_hw_params()
392 ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL, in tas5086_hw_params()
394 (priv->sclk == 48 * priv->rate) ? in tas5086_hw_params()
402 * a logical bit-boundary. Hence, we have to refer to the format passed in tas5086_hw_params()
407 switch (priv->format & SND_SOC_DAIFMT_FORMAT_MASK) { in tas5086_hw_params()
418 dev_err(component->dev, "Invalid DAI format\n"); in tas5086_hw_params()
419 return -EINVAL; in tas5086_hw_params()
434 dev_err(component->dev, "Invalid bit width\n"); in tas5086_hw_params()
435 return -EINVAL; in tas5086_hw_params()
438 ret = regmap_write(priv->regmap, TAS5086_SERIAL_DATA_IF, val); in tas5086_hw_params()
443 ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL, in tas5086_hw_params()
453 struct snd_soc_component *component = dai->component; in tas5086_mute_stream()
460 return regmap_write(priv->regmap, TAS5086_SOFT_MUTE, val); in tas5086_mute_stream()
465 if (gpio_is_valid(priv->gpio_nreset)) { in tas5086_reset()
466 /* Reset codec - minimum assertion time is 400ns */ in tas5086_reset()
467 gpio_direction_output(priv->gpio_nreset, 0); in tas5086_reset()
469 gpio_set_value(priv->gpio_nreset, 1); in tas5086_reset()
488 * If any of the channels is configured to start in Mid-Z mode, in tas5086_init()
489 * configure 'part 1' of the PWM starts to use Mid-Z, and tell in tas5086_init()
490 * all configured mid-z channels to start under 'part 1'. in tas5086_init()
492 if (priv->pwm_start_mid_z) in tas5086_init()
493 regmap_write(priv->regmap, TAS5086_PWM_START, in tas5086_init()
495 priv->pwm_start_mid_z); in tas5086_init()
497 /* lookup and set split-capacitor charge period */ in tas5086_init()
498 if (priv->charge_period == 0) { in tas5086_init()
499 regmap_write(priv->regmap, TAS5086_SPLIT_CAP_CHARGE, 0); in tas5086_init()
503 priv->charge_period); in tas5086_init()
505 regmap_write(priv->regmap, TAS5086_SPLIT_CAP_CHARGE, in tas5086_init()
509 "Invalid split-cap charge period of %d ns.\n", in tas5086_init()
510 priv->charge_period); in tas5086_init()
514 ret = regmap_write(priv->regmap, TAS5086_OSC_TRIM, 0x00); in tas5086_init()
519 ret = regmap_write(priv->regmap, TAS5086_SYS_CONTROL_2, 0x20); in tas5086_init()
524 ret = regmap_write(priv->regmap, TAS5086_SOFT_MUTE, in tas5086_init()
533 static const DECLARE_TLV_DB_SCALE(tas5086_dac_tlv, -10350, 50, 1);
538 SOC_DOUBLE_R_TLV("Channel 1/2 Playback Volume",
541 SOC_DOUBLE_R_TLV("Channel 3/4 Playback Volume",
544 SOC_DOUBLE_R_TLV("Channel 5/6 Playback Volume",
547 SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0,
554 "SDIN1-L", "SDIN1-R", "SDIN2-L", "SDIN2-R",
555 "SDIN3-L", "SDIN3-R", "Ground (0)", "nc"
559 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 20, 8, tas5086_dapm_sdin_texts),
560 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 16, 8, tas5086_dapm_sdin_texts),
561 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 12, 8, tas5086_dapm_sdin_texts),
562 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 8, 8, tas5086_dapm_sdin_texts),
563 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 4, 8, tas5086_dapm_sdin_texts),
564 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 0, 8, tas5086_dapm_sdin_texts),
568 SOC_DAPM_ENUM("Channel 1 input", tas5086_dapm_input_mux_enum[0]),
569 SOC_DAPM_ENUM("Channel 2 input", tas5086_dapm_input_mux_enum[1]),
570 SOC_DAPM_ENUM("Channel 3 input", tas5086_dapm_input_mux_enum[2]),
571 SOC_DAPM_ENUM("Channel 4 input", tas5086_dapm_input_mux_enum[3]),
572 SOC_DAPM_ENUM("Channel 5 input", tas5086_dapm_input_mux_enum[4]),
573 SOC_DAPM_ENUM("Channel 6 input", tas5086_dapm_input_mux_enum[5]),
578 { "Channel 1 Mux", "Channel 2 Mux", "Channel 3 Mux",
579 "Channel 4 Mux", "Channel 5 Mux", "Channel 6 Mux" };
585 SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 8, 6, tas5086_dapm_channel_texts),
600 SND_SOC_DAPM_INPUT("SDIN1-L"),
601 SND_SOC_DAPM_INPUT("SDIN1-R"),
602 SND_SOC_DAPM_INPUT("SDIN2-L"),
603 SND_SOC_DAPM_INPUT("SDIN2-R"),
604 SND_SOC_DAPM_INPUT("SDIN3-L"),
605 SND_SOC_DAPM_INPUT("SDIN3-R"),
606 SND_SOC_DAPM_INPUT("SDIN4-L"),
607 SND_SOC_DAPM_INPUT("SDIN4-R"),
616 SND_SOC_DAPM_MUX("Channel 1 Mux", SND_SOC_NOPM, 0, 0,
618 SND_SOC_DAPM_MUX("Channel 2 Mux", SND_SOC_NOPM, 0, 0,
620 SND_SOC_DAPM_MUX("Channel 3 Mux", SND_SOC_NOPM, 0, 0,
622 SND_SOC_DAPM_MUX("Channel 4 Mux", SND_SOC_NOPM, 0, 0,
624 SND_SOC_DAPM_MUX("Channel 5 Mux", SND_SOC_NOPM, 0, 0,
626 SND_SOC_DAPM_MUX("Channel 6 Mux", SND_SOC_NOPM, 0, 0,
644 /* SDIN inputs -> channel muxes */
645 { "Channel 1 Mux", "SDIN1-L", "SDIN1-L" },
646 { "Channel 1 Mux", "SDIN1-R", "SDIN1-R" },
647 { "Channel 1 Mux", "SDIN2-L", "SDIN2-L" },
648 { "Channel 1 Mux", "SDIN2-R", "SDIN2-R" },
649 { "Channel 1 Mux", "SDIN3-L", "SDIN3-L" },
650 { "Channel 1 Mux", "SDIN3-R", "SDIN3-R" },
652 { "Channel 2 Mux", "SDIN1-L", "SDIN1-L" },
653 { "Channel 2 Mux", "SDIN1-R", "SDIN1-R" },
654 { "Channel 2 Mux", "SDIN2-L", "SDIN2-L" },
655 { "Channel 2 Mux", "SDIN2-R", "SDIN2-R" },
656 { "Channel 2 Mux", "SDIN3-L", "SDIN3-L" },
657 { "Channel 2 Mux", "SDIN3-R", "SDIN3-R" },
659 { "Channel 2 Mux", "SDIN1-L", "SDIN1-L" },
660 { "Channel 2 Mux", "SDIN1-R", "SDIN1-R" },
661 { "Channel 2 Mux", "SDIN2-L", "SDIN2-L" },
662 { "Channel 2 Mux", "SDIN2-R", "SDIN2-R" },
663 { "Channel 2 Mux", "SDIN3-L", "SDIN3-L" },
664 { "Channel 2 Mux", "SDIN3-R", "SDIN3-R" },
666 { "Channel 3 Mux", "SDIN1-L", "SDIN1-L" },
667 { "Channel 3 Mux", "SDIN1-R", "SDIN1-R" },
668 { "Channel 3 Mux", "SDIN2-L", "SDIN2-L" },
669 { "Channel 3 Mux", "SDIN2-R", "SDIN2-R" },
670 { "Channel 3 Mux", "SDIN3-L", "SDIN3-L" },
671 { "Channel 3 Mux", "SDIN3-R", "SDIN3-R" },
673 { "Channel 4 Mux", "SDIN1-L", "SDIN1-L" },
674 { "Channel 4 Mux", "SDIN1-R", "SDIN1-R" },
675 { "Channel 4 Mux", "SDIN2-L", "SDIN2-L" },
676 { "Channel 4 Mux", "SDIN2-R", "SDIN2-R" },
677 { "Channel 4 Mux", "SDIN3-L", "SDIN3-L" },
678 { "Channel 4 Mux", "SDIN3-R", "SDIN3-R" },
680 { "Channel 5 Mux", "SDIN1-L", "SDIN1-L" },
681 { "Channel 5 Mux", "SDIN1-R", "SDIN1-R" },
682 { "Channel 5 Mux", "SDIN2-L", "SDIN2-L" },
683 { "Channel 5 Mux", "SDIN2-R", "SDIN2-R" },
684 { "Channel 5 Mux", "SDIN3-L", "SDIN3-L" },
685 { "Channel 5 Mux", "SDIN3-R", "SDIN3-R" },
687 { "Channel 6 Mux", "SDIN1-L", "SDIN1-L" },
688 { "Channel 6 Mux", "SDIN1-R", "SDIN1-R" },
689 { "Channel 6 Mux", "SDIN2-L", "SDIN2-L" },
690 { "Channel 6 Mux", "SDIN2-R", "SDIN2-R" },
691 { "Channel 6 Mux", "SDIN3-L", "SDIN3-L" },
692 { "Channel 6 Mux", "SDIN3-R", "SDIN3-R" },
694 /* Channel muxes -> PWM muxes */
695 { "PWM1 Mux", "Channel 1 Mux", "Channel 1 Mux" },
696 { "PWM2 Mux", "Channel 1 Mux", "Channel 1 Mux" },
697 { "PWM3 Mux", "Channel 1 Mux", "Channel 1 Mux" },
698 { "PWM4 Mux", "Channel 1 Mux", "Channel 1 Mux" },
699 { "PWM5 Mux", "Channel 1 Mux", "Channel 1 Mux" },
700 { "PWM6 Mux", "Channel 1 Mux", "Channel 1 Mux" },
702 { "PWM1 Mux", "Channel 2 Mux", "Channel 2 Mux" },
703 { "PWM2 Mux", "Channel 2 Mux", "Channel 2 Mux" },
704 { "PWM3 Mux", "Channel 2 Mux", "Channel 2 Mux" },
705 { "PWM4 Mux", "Channel 2 Mux", "Channel 2 Mux" },
706 { "PWM5 Mux", "Channel 2 Mux", "Channel 2 Mux" },
707 { "PWM6 Mux", "Channel 2 Mux", "Channel 2 Mux" },
709 { "PWM1 Mux", "Channel 3 Mux", "Channel 3 Mux" },
710 { "PWM2 Mux", "Channel 3 Mux", "Channel 3 Mux" },
711 { "PWM3 Mux", "Channel 3 Mux", "Channel 3 Mux" },
712 { "PWM4 Mux", "Channel 3 Mux", "Channel 3 Mux" },
713 { "PWM5 Mux", "Channel 3 Mux", "Channel 3 Mux" },
714 { "PWM6 Mux", "Channel 3 Mux", "Channel 3 Mux" },
716 { "PWM1 Mux", "Channel 4 Mux", "Channel 4 Mux" },
717 { "PWM2 Mux", "Channel 4 Mux", "Channel 4 Mux" },
718 { "PWM3 Mux", "Channel 4 Mux", "Channel 4 Mux" },
719 { "PWM4 Mux", "Channel 4 Mux", "Channel 4 Mux" },
720 { "PWM5 Mux", "Channel 4 Mux", "Channel 4 Mux" },
721 { "PWM6 Mux", "Channel 4 Mux", "Channel 4 Mux" },
723 { "PWM1 Mux", "Channel 5 Mux", "Channel 5 Mux" },
724 { "PWM2 Mux", "Channel 5 Mux", "Channel 5 Mux" },
725 { "PWM3 Mux", "Channel 5 Mux", "Channel 5 Mux" },
726 { "PWM4 Mux", "Channel 5 Mux", "Channel 5 Mux" },
727 { "PWM5 Mux", "Channel 5 Mux", "Channel 5 Mux" },
728 { "PWM6 Mux", "Channel 5 Mux", "Channel 5 Mux" },
730 { "PWM1 Mux", "Channel 6 Mux", "Channel 6 Mux" },
731 { "PWM2 Mux", "Channel 6 Mux", "Channel 6 Mux" },
732 { "PWM3 Mux", "Channel 6 Mux", "Channel 6 Mux" },
733 { "PWM4 Mux", "Channel 6 Mux", "Channel 6 Mux" },
734 { "PWM5 Mux", "Channel 6 Mux", "Channel 6 Mux" },
735 { "PWM6 Mux", "Channel 6 Mux", "Channel 6 Mux" },
755 .name = "tas5086-hifi",
773 ret = regmap_write(priv->regmap, TAS5086_SYS_CONTROL_2, 0x60); in tas5086_soc_suspend()
777 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies); in tas5086_soc_suspend()
787 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); in tas5086_soc_resume()
792 regcache_mark_dirty(priv->regmap); in tas5086_soc_resume()
794 ret = tas5086_init(component->dev, priv); in tas5086_soc_resume()
798 ret = regcache_sync(priv->regmap); in tas5086_soc_resume()
822 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); in tas5086_probe()
824 dev_err(component->dev, "Failed to enable regulators: %d\n", ret); in tas5086_probe()
828 priv->pwm_start_mid_z = 0; in tas5086_probe()
829 priv->charge_period = 1300000; /* hardware default is 1300 ms */ in tas5086_probe()
831 if (of_match_device(of_match_ptr(tas5086_dt_ids), component->dev)) { in tas5086_probe()
832 struct device_node *of_node = component->dev->of_node; in tas5086_probe()
834 of_property_read_u32(of_node, "ti,charge-period", in tas5086_probe()
835 &priv->charge_period); in tas5086_probe()
841 "ti,mid-z-channel-%d", i + 1); in tas5086_probe()
844 priv->pwm_start_mid_z |= 1 << i; in tas5086_probe()
849 ret = tas5086_init(component->dev, priv); in tas5086_probe()
854 ret = regmap_write(priv->regmap, TAS5086_MASTER_VOL, 0x30); in tas5086_probe()
861 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies); in tas5086_probe()
870 if (gpio_is_valid(priv->gpio_nreset)) in tas5086_remove()
872 gpio_set_value(priv->gpio_nreset, 0); in tas5086_remove()
874 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies); in tas5086_remove()
901 .reg_bits = 8,
918 struct device *dev = &i2c->dev; in tas5086_i2c_probe()
919 int gpio_nreset = -EINVAL; in tas5086_i2c_probe()
924 return -ENOMEM; in tas5086_i2c_probe()
927 priv->supplies[i].supply = supply_names[i]; in tas5086_i2c_probe()
929 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies), in tas5086_i2c_probe()
930 priv->supplies); in tas5086_i2c_probe()
936 priv->regmap = devm_regmap_init(dev, NULL, i2c, &tas5086_regmap); in tas5086_i2c_probe()
937 if (IS_ERR(priv->regmap)) { in tas5086_i2c_probe()
938 ret = PTR_ERR(priv->regmap); in tas5086_i2c_probe()
939 dev_err(&i2c->dev, "Failed to create regmap: %d\n", ret); in tas5086_i2c_probe()
946 struct device_node *of_node = dev->of_node; in tas5086_i2c_probe()
947 gpio_nreset = of_get_named_gpio(of_node, "reset-gpio", 0); in tas5086_i2c_probe()
952 gpio_nreset = -EINVAL; in tas5086_i2c_probe()
954 priv->gpio_nreset = gpio_nreset; in tas5086_i2c_probe()
956 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); in tas5086_i2c_probe()
965 ret = regmap_read(priv->regmap, TAS5086_DEV_ID, &i); in tas5086_i2c_probe()
969 ret = -ENODEV; in tas5086_i2c_probe()
976 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies); in tas5086_i2c_probe()
979 ret = devm_snd_soc_register_component(&i2c->dev, in tas5086_i2c_probe()