Lines Matching +full:adc +full:- +full:channel +full:- +full:clk +full:- +full:src
1 // SPDX-License-Identifier: GPL-2.0-only
3 // rt5682.c -- RT5682 ALSA SoC audio component driver
26 #include <sound/soc-dapm.h>
53 ret = regmap_multi_reg_write(rt5682->regmap, patch_list, in rt5682_apply_patch_list()
742 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
743 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
778 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
781 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
784 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
787 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
790 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
810 regmap_write(rt5682->regmap, RT5682_RESET, 0); in rt5682_reset()
811 if (!rt5682->is_sdw) in rt5682_reset()
812 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1); in rt5682_reset()
817 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
840 return -EINVAL; in rt5682_sel_asrc_clk_src()
866 dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type); in rt5682_button_detect()
887 if (rt5682->is_sdw) in rt5682_enable_push_button_irq()
911 * rt5682_headset_detect - Detect headset.
922 struct snd_soc_dapm_context *dapm = &component->dapm; in rt5682_headset_detect()
955 rt5682->jack_type = SND_JACK_HEADSET; in rt5682_headset_detect()
959 rt5682->jack_type = SND_JACK_HEADPHONE; in rt5682_headset_detect()
986 rt5682->jack_type = 0; in rt5682_headset_detect()
989 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type); in rt5682_headset_detect()
990 return rt5682->jack_type; in rt5682_headset_detect()
999 rt5682->hs_jack = hs_jack; in rt5682_set_jack_detect()
1002 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, in rt5682_set_jack_detect()
1004 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, in rt5682_set_jack_detect()
1006 cancel_delayed_work_sync(&rt5682->jack_detect_work); in rt5682_set_jack_detect()
1011 if (!rt5682->is_sdw) { in rt5682_set_jack_detect()
1012 switch (rt5682->pdata.jd_src) { in rt5682_set_jack_detect()
1025 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, in rt5682_set_jack_detect()
1027 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, in rt5682_set_jack_detect()
1031 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2, in rt5682_set_jack_detect()
1033 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, in rt5682_set_jack_detect()
1036 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4, in rt5682_set_jack_detect()
1037 0x7f7f, (rt5682->pdata.btndet_delay << 8 | in rt5682_set_jack_detect()
1038 rt5682->pdata.btndet_delay)); in rt5682_set_jack_detect()
1039 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5, in rt5682_set_jack_detect()
1040 0x7f7f, (rt5682->pdata.btndet_delay << 8 | in rt5682_set_jack_detect()
1041 rt5682->pdata.btndet_delay)); in rt5682_set_jack_detect()
1042 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6, in rt5682_set_jack_detect()
1043 0x7f7f, (rt5682->pdata.btndet_delay << 8 | in rt5682_set_jack_detect()
1044 rt5682->pdata.btndet_delay)); in rt5682_set_jack_detect()
1045 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7, in rt5682_set_jack_detect()
1046 0x7f7f, (rt5682->pdata.btndet_delay << 8 | in rt5682_set_jack_detect()
1047 rt5682->pdata.btndet_delay)); in rt5682_set_jack_detect()
1049 &rt5682->jack_detect_work, in rt5682_set_jack_detect()
1054 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, in rt5682_set_jack_detect()
1056 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, in rt5682_set_jack_detect()
1061 dev_warn(component->dev, "Wrong JD source\n"); in rt5682_set_jack_detect()
1075 while (!rt5682->component) in rt5682_jack_detect_handler()
1078 while (!rt5682->component->card->instantiated) in rt5682_jack_detect_handler()
1081 mutex_lock(&rt5682->calibrate_mutex); in rt5682_jack_detect_handler()
1083 val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL) in rt5682_jack_detect_handler()
1087 if (rt5682->jack_type == 0) { in rt5682_jack_detect_handler()
1089 rt5682->jack_type = in rt5682_jack_detect_handler()
1090 rt5682_headset_detect(rt5682->component, 1); in rt5682_jack_detect_handler()
1091 } else if ((rt5682->jack_type & SND_JACK_HEADSET) == in rt5682_jack_detect_handler()
1094 rt5682->jack_type = SND_JACK_HEADSET; in rt5682_jack_detect_handler()
1095 btn_type = rt5682_button_detect(rt5682->component); in rt5682_jack_detect_handler()
1107 rt5682->jack_type |= SND_JACK_BTN_0; in rt5682_jack_detect_handler()
1112 rt5682->jack_type |= SND_JACK_BTN_1; in rt5682_jack_detect_handler()
1117 rt5682->jack_type |= SND_JACK_BTN_2; in rt5682_jack_detect_handler()
1122 rt5682->jack_type |= SND_JACK_BTN_3; in rt5682_jack_detect_handler()
1127 dev_err(rt5682->component->dev, in rt5682_jack_detect_handler()
1135 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0); in rt5682_jack_detect_handler()
1138 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type, in rt5682_jack_detect_handler()
1143 if (!rt5682->is_sdw) { in rt5682_jack_detect_handler()
1144 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | in rt5682_jack_detect_handler()
1146 schedule_delayed_work(&rt5682->jd_check_work, 0); in rt5682_jack_detect_handler()
1148 cancel_delayed_work_sync(&rt5682->jd_check_work); in rt5682_jack_detect_handler()
1151 mutex_unlock(&rt5682->calibrate_mutex); in rt5682_jack_detect_handler()
1164 /* ADC Digital Volume Control */
1165 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
1167 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
1170 /* ADC Boost Volume Control */
1171 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
1181 if (rt5682->sysclk < target) { in rt5682_div_sel()
1182 dev_err(rt5682->component->dev, in rt5682_div_sel()
1183 "sysclk rate %d is too low\n", rt5682->sysclk); in rt5682_div_sel()
1187 for (i = 0; i < size - 1; i++) { in rt5682_div_sel()
1188 dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]); in rt5682_div_sel()
1189 if (target * div[i] == rt5682->sysclk) in rt5682_div_sel()
1191 if (target * div[i + 1] > rt5682->sysclk) { in rt5682_div_sel()
1192 dev_dbg(rt5682->component->dev, in rt5682_div_sel()
1194 rt5682->sysclk); in rt5682_div_sel()
1199 if (target * div[i] < rt5682->sysclk) in rt5682_div_sel()
1200 dev_err(rt5682->component->dev, in rt5682_div_sel()
1201 "sysclk rate %d is too high\n", rt5682->sysclk); in rt5682_div_sel()
1203 return size - 1; in rt5682_div_sel()
1207 * set_dmic_clk - Set parameter of dmic.
1220 snd_soc_dapm_to_component(w->dapm); in set_dmic_clk()
1222 int idx = -EINVAL, dmic_clk_rate = 3072000; in set_dmic_clk()
1225 if (rt5682->pdata.dmic_clk_rate) in set_dmic_clk()
1226 dmic_clk_rate = rt5682->pdata.dmic_clk_rate; in set_dmic_clk()
1240 snd_soc_dapm_to_component(w->dapm); in set_filter_clk()
1242 int ref, val, reg, idx = -EINVAL; in set_filter_clk()
1246 if (rt5682->is_sdw) in set_filter_clk()
1251 if (w->shift == RT5682_PWR_ADC_S1F_BIT && in set_filter_clk()
1253 ref = 256 * rt5682->lrck[RT5682_AIF2]; in set_filter_clk()
1255 ref = 256 * rt5682->lrck[RT5682_AIF1]; in set_filter_clk()
1259 if (w->shift == RT5682_PWR_ADC_S1F_BIT) in set_filter_clk()
1269 if (rt5682->sysclk <= 12288000 * div_o[idx]) in set_filter_clk()
1285 snd_soc_dapm_to_component(w->dapm); in is_sys_clk_from_pll1()
1300 snd_soc_dapm_to_component(w->dapm); in is_sys_clk_from_pll2()
1315 snd_soc_dapm_to_component(w->dapm); in is_using_asrc()
1317 switch (w->shift) { in is_using_asrc()
1356 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1363 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1390 /* MX-26 [13] [5] */
1392 "DAC MIX", "ADC"
1409 /* STO1 ADC Source */
1410 /* MX-26 [11:10] [3:2] */
1430 /* MX-26 [12] [4] */
1449 /* MX-79 [6:4] I2S1 ADC data location */
1466 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
1469 /* MX-2B [4], MX-2B [0]*/
1500 snd_soc_dapm_to_component(w->dapm); in rt5682_hp_event()
1531 snd_soc_dapm_to_component(w->dapm); in set_dmic_power()
1535 if (rt5682->pdata.dmic_delay) in set_dmic_power()
1536 delay = rt5682->pdata.dmic_delay; in set_dmic_power()
1553 if (!rt5682->jack_type) { in set_dmic_power()
1554 if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS")) in set_dmic_power()
1557 if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2")) in set_dmic_power()
1571 snd_soc_dapm_to_component(w->dapm); in rt5682_set_verf()
1575 switch (w->shift) { in rt5682_set_verf()
1590 switch (w->shift) { in rt5682_set_verf()
1643 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1664 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1691 /* ADC Mux */
1692 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1694 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1696 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1698 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1700 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1702 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1707 /* ADC Mixer */
1708 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
1711 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
1714 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1720 /* ADC PGA */
1721 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1735 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1737 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1739 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1741 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1743 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1770 /* DAC channel Mux */
1811 /* CLK DET */
1828 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1829 {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1830 {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1836 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1838 {"ADC STO1 ASRC", NULL, "AD ASRC"},
1839 {"ADC STO1 ASRC", NULL, "DA ASRC"},
1840 {"ADC STO1 ASRC", NULL, "CLKDET"},
1862 {"DMIC L1", NULL, "DMIC CLK"},
1864 {"DMIC R1", NULL, "DMIC CLK"},
1866 {"DMIC CLK", NULL, "DMIC ASRC"},
1868 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1869 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1870 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1871 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1873 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1874 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1875 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1876 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1878 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1879 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1880 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1881 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1883 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1884 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1885 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1887 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1888 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1889 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1891 {"ADC Stereo1 Filter", NULL, "BTN Detection Mode"},
1893 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1894 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1896 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1897 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1898 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1899 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1900 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1901 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1902 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1903 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1904 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1905 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1906 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1907 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1908 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1909 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1910 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1911 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1913 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1914 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1915 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1916 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1920 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1921 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1922 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1923 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1924 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1952 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1954 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1991 struct snd_soc_component *component = dai->component; in rt5682_set_tdm_slot()
2017 return -EINVAL; in rt5682_set_tdm_slot()
2026 return -EINVAL; in rt5682_set_tdm_slot()
2046 return -EINVAL; in rt5682_set_tdm_slot()
2060 struct snd_soc_component *component = dai->component; in rt5682_hw_params()
2065 rt5682->lrck[dai->id] = params_rate(params); in rt5682_hw_params()
2066 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]); in rt5682_hw_params()
2070 dev_err(component->dev, "Unsupported frame size: %d\n", in rt5682_hw_params()
2072 return -EINVAL; in rt5682_hw_params()
2075 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", in rt5682_hw_params()
2076 rt5682->lrck[dai->id], pre_div, dai->id); in rt5682_hw_params()
2098 return -EINVAL; in rt5682_hw_params()
2101 switch (dai->id) { in rt5682_hw_params()
2105 if (rt5682->master[RT5682_AIF1]) { in rt5682_hw_params()
2110 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); in rt5682_hw_params()
2124 if (rt5682->master[RT5682_AIF2]) { in rt5682_hw_params()
2139 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); in rt5682_hw_params()
2140 return -EINVAL; in rt5682_hw_params()
2148 struct snd_soc_component *component = dai->component; in rt5682_set_dai_fmt()
2154 rt5682->master[dai->id] = 1; in rt5682_set_dai_fmt()
2157 rt5682->master[dai->id] = 0; in rt5682_set_dai_fmt()
2160 return -EINVAL; in rt5682_set_dai_fmt()
2171 if (dai->id == RT5682_AIF1) in rt5682_set_dai_fmt()
2174 return -EINVAL; in rt5682_set_dai_fmt()
2177 if (dai->id == RT5682_AIF1) in rt5682_set_dai_fmt()
2181 return -EINVAL; in rt5682_set_dai_fmt()
2184 return -EINVAL; in rt5682_set_dai_fmt()
2203 return -EINVAL; in rt5682_set_dai_fmt()
2206 switch (dai->id) { in rt5682_set_dai_fmt()
2214 tdm_ctrl | rt5682->master[dai->id]); in rt5682_set_dai_fmt()
2217 if (rt5682->master[dai->id] == 0) in rt5682_set_dai_fmt()
2224 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); in rt5682_set_dai_fmt()
2225 return -EINVAL; in rt5682_set_dai_fmt()
2234 unsigned int reg_val = 0, src = 0; in rt5682_set_component_sysclk() local
2236 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src) in rt5682_set_component_sysclk()
2242 src = RT5682_CLK_SRC_MCLK; in rt5682_set_component_sysclk()
2246 src = RT5682_CLK_SRC_PLL1; in rt5682_set_component_sysclk()
2250 src = RT5682_CLK_SRC_PLL2; in rt5682_set_component_sysclk()
2254 src = RT5682_CLK_SRC_RCCLK; in rt5682_set_component_sysclk()
2257 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); in rt5682_set_component_sysclk()
2258 return -EINVAL; in rt5682_set_component_sysclk()
2263 if (rt5682->master[RT5682_AIF2]) { in rt5682_set_component_sysclk()
2266 src << RT5682_I2S2_SRC_SFT); in rt5682_set_component_sysclk()
2269 rt5682->sysclk = freq; in rt5682_set_component_sysclk()
2270 rt5682->sysclk_src = clk_id; in rt5682_set_component_sysclk()
2272 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", in rt5682_set_component_sysclk()
2287 if (source == rt5682->pll_src[pll_id] && in rt5682_set_component_pll()
2288 freq_in == rt5682->pll_in[pll_id] && in rt5682_set_component_pll()
2289 freq_out == rt5682->pll_out[pll_id]) in rt5682_set_component_pll()
2293 dev_dbg(component->dev, "PLL disabled\n"); in rt5682_set_component_pll()
2295 rt5682->pll_in[pll_id] = 0; in rt5682_set_component_pll()
2296 rt5682->pll_out[pll_id] = 0; in rt5682_set_component_pll()
2310 dev_err(component->dev, "Unknown PLL2 Source %d\n", in rt5682_set_component_pll()
2312 return -EINVAL; in rt5682_set_component_pll()
2322 dev_err(component->dev, "Unsupport input clock %d\n", in rt5682_set_component_pll()
2326 dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", in rt5682_set_component_pll()
2334 dev_err(component->dev, "Unsupport input clock %d\n", in rt5682_set_component_pll()
2338 dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", in rt5682_set_component_pll()
2378 dev_err(component->dev, "Unknown PLL1 Source %d\n", in rt5682_set_component_pll()
2380 return -EINVAL; in rt5682_set_component_pll()
2385 dev_err(component->dev, "Unsupport input clock %d\n", in rt5682_set_component_pll()
2390 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", in rt5682_set_component_pll()
2401 rt5682->pll_in[pll_id] = freq_in; in rt5682_set_component_pll()
2402 rt5682->pll_out[pll_id] = freq_out; in rt5682_set_component_pll()
2403 rt5682->pll_src[pll_id] = source; in rt5682_set_component_pll()
2410 struct snd_soc_component *component = dai->component; in rt5682_set_bclk1_ratio()
2413 rt5682->bclk[dai->id] = ratio; in rt5682_set_bclk1_ratio()
2433 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio); in rt5682_set_bclk1_ratio()
2434 return -EINVAL; in rt5682_set_bclk1_ratio()
2442 struct snd_soc_component *component = dai->component; in rt5682_set_bclk2_ratio()
2445 rt5682->bclk[dai->id] = ratio; in rt5682_set_bclk2_ratio()
2459 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio); in rt5682_set_bclk2_ratio()
2460 return -EINVAL; in rt5682_set_bclk2_ratio()
2473 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, in rt5682_set_bias_level()
2475 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, in rt5682_set_bias_level()
2481 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, in rt5682_set_bias_level()
2485 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, in rt5682_set_bias_level()
2487 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, in rt5682_set_bias_level()
2504 if (!rt5682->master[RT5682_AIF1]) { in rt5682_clk_check()
2505 dev_dbg(rt5682->component->dev, "sysclk/dai not set correctly\n"); in rt5682_clk_check()
2516 struct snd_soc_component *component = rt5682->component; in rt5682_wclk_prepare()
2521 return -EINVAL; in rt5682_wclk_prepare()
2552 struct snd_soc_component *component = rt5682->component; in rt5682_wclk_unprepare()
2563 if (!rt5682->jack_type) in rt5682_wclk_unprepare()
2582 struct snd_soc_component *component = rt5682->component; in rt5682_wclk_recalc_rate()
2590 if (rt5682->lrck[RT5682_AIF1] != CLK_48 && in rt5682_wclk_recalc_rate()
2591 rt5682->lrck[RT5682_AIF1] != CLK_44) { in rt5682_wclk_recalc_rate()
2592 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n", in rt5682_wclk_recalc_rate()
2597 return rt5682->lrck[RT5682_AIF1]; in rt5682_wclk_recalc_rate()
2606 struct snd_soc_component *component = rt5682->component; in rt5682_wclk_round_rate()
2610 return -EINVAL; in rt5682_wclk_round_rate()
2616 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n", in rt5682_wclk_round_rate()
2630 struct snd_soc_component *component = rt5682->component; in rt5682_wclk_set_rate()
2631 struct clk *parent_clk; in rt5682_wclk_set_rate()
2637 return -EINVAL; in rt5682_wclk_set_rate()
2640 * Whether the wclk's parent clk (mclk) exists or not, please ensure in rt5682_wclk_set_rate()
2642 * temporary limitation. Only accept 48MHz clk as the clk provider. in rt5682_wclk_set_rate()
2646 parent_clk = clk_get_parent(hw->clk); in rt5682_wclk_set_rate()
2648 dev_warn(component->dev, in rt5682_wclk_set_rate()
2653 dev_warn(component->dev, "clk %s only support %d Hz input\n", in rt5682_wclk_set_rate()
2667 rt5682->lrck[RT5682_AIF1] = rate; in rt5682_wclk_set_rate()
2669 pre_div = rl6231_get_clk_info(rt5682->sysclk, rate); in rt5682_wclk_set_rate()
2674 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); in rt5682_wclk_set_rate()
2685 struct snd_soc_component *component = rt5682->component; in rt5682_bclk_recalc_rate()
2729 return -EINVAL; in rt5682_bclk_round_rate()
2749 struct snd_soc_component *component = rt5682->component; in rt5682_bclk_set_rate()
2754 return -EINVAL; in rt5682_bclk_set_rate()
2759 if (dai->id == RT5682_AIF1) in rt5682_bclk_set_rate()
2762 dev_err(component->dev, "dai %d not found in component\n", in rt5682_bclk_set_rate()
2764 return -ENODEV; in rt5682_bclk_set_rate()
2787 struct device *dev = component->dev; in rt5682_register_dai_clks()
2789 struct rt5682_platform_data *pdata = &rt5682->pdata; in rt5682_register_dai_clks()
2796 dai_clk_hw = &rt5682->dai_clks_hw[i]; in rt5682_register_dai_clks()
2801 if (rt5682->mclk) { in rt5682_register_dai_clks()
2811 &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX] in rt5682_register_dai_clks()
2817 return -EINVAL; in rt5682_register_dai_clks()
2820 init.name = pdata->dai_clk_names[i]; in rt5682_register_dai_clks()
2823 dai_clk_hw->init = &init; in rt5682_register_dai_clks()
2832 if (dev->of_node) { in rt5682_register_dai_clks()
2853 struct snd_soc_dapm_context *dapm = &component->dapm; in rt5682_probe()
2858 rt5682->component = component; in rt5682_probe()
2860 if (rt5682->is_sdw) { in rt5682_probe()
2861 slave = rt5682->slave; in rt5682_probe()
2863 &slave->initialization_complete, in rt5682_probe()
2866 dev_err(&slave->dev, "Initialization not complete, timed out\n"); in rt5682_probe()
2867 return -ETIMEDOUT; in rt5682_probe()
2872 rt5682->mclk = devm_clk_get(component->dev, "mclk"); in rt5682_probe()
2873 if (IS_ERR(rt5682->mclk)) { in rt5682_probe()
2874 if (PTR_ERR(rt5682->mclk) != -ENOENT) { in rt5682_probe()
2875 ret = PTR_ERR(rt5682->mclk); in rt5682_probe()
2878 rt5682->mclk = NULL; in rt5682_probe()
2887 rt5682->lrck[RT5682_AIF1] = CLK_48; in rt5682_probe()
2909 regcache_cache_only(rt5682->regmap, true); in rt5682_suspend()
2910 regcache_mark_dirty(rt5682->regmap); in rt5682_suspend()
2918 regcache_cache_only(rt5682->regmap, false); in rt5682_resume()
2919 regcache_sync(rt5682->regmap); in rt5682_resume()
2922 &rt5682->jack_detect_work, msecs_to_jiffies(250)); in rt5682_resume()
2970 device_property_read_u32(dev, "realtek,dmic1-data-pin", in rt5682_parse_dt()
2971 &rt5682->pdata.dmic1_data_pin); in rt5682_parse_dt()
2972 device_property_read_u32(dev, "realtek,dmic1-clk-pin", in rt5682_parse_dt()
2973 &rt5682->pdata.dmic1_clk_pin); in rt5682_parse_dt()
2974 device_property_read_u32(dev, "realtek,jd-src", in rt5682_parse_dt()
2975 &rt5682->pdata.jd_src); in rt5682_parse_dt()
2976 device_property_read_u32(dev, "realtek,btndet-delay", in rt5682_parse_dt()
2977 &rt5682->pdata.btndet_delay); in rt5682_parse_dt()
2978 device_property_read_u32(dev, "realtek,dmic-clk-rate-hz", in rt5682_parse_dt()
2979 &rt5682->pdata.dmic_clk_rate); in rt5682_parse_dt()
2980 device_property_read_u32(dev, "realtek,dmic-delay-ms", in rt5682_parse_dt()
2981 &rt5682->pdata.dmic_delay); in rt5682_parse_dt()
2983 rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node, in rt5682_parse_dt()
2984 "realtek,ldo1-en-gpios", 0); in rt5682_parse_dt()
2986 if (device_property_read_string_array(dev, "clock-output-names", in rt5682_parse_dt()
2987 rt5682->pdata.dai_clk_names, in rt5682_parse_dt()
2989 dev_warn(dev, "Using default DAI clk names: %s, %s\n", in rt5682_parse_dt()
2990 rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX], in rt5682_parse_dt()
2991 rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]); in rt5682_parse_dt()
3001 mutex_lock(&rt5682->calibrate_mutex); in rt5682_calibrate()
3004 regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f); in rt5682_calibrate()
3005 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af); in rt5682_calibrate()
3007 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af); in rt5682_calibrate()
3008 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300); in rt5682_calibrate()
3009 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000); in rt5682_calibrate()
3010 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100); in rt5682_calibrate()
3011 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800); in rt5682_calibrate()
3012 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000); in rt5682_calibrate()
3013 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005); in rt5682_calibrate()
3014 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c); in rt5682_calibrate()
3015 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d); in rt5682_calibrate()
3016 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321); in rt5682_calibrate()
3017 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004); in rt5682_calibrate()
3018 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); in rt5682_calibrate()
3019 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1); in rt5682_calibrate()
3020 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311); in rt5682_calibrate()
3021 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); in rt5682_calibrate()
3023 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00); in rt5682_calibrate()
3026 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value); in rt5682_calibrate()
3034 dev_err(rt5682->component->dev, "HP Calibration Failure\n"); in rt5682_calibrate()
3037 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f); in rt5682_calibrate()
3038 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080); in rt5682_calibrate()
3039 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000); in rt5682_calibrate()
3040 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000); in rt5682_calibrate()
3041 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000); in rt5682_calibrate()
3042 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005); in rt5682_calibrate()
3043 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4); in rt5682_calibrate()
3044 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c); in rt5682_calibrate()
3046 mutex_unlock(&rt5682->calibrate_mutex); in rt5682_calibrate()