Lines Matching +full:0 +full:x1
13 #define RT5670_RESET 0x00
14 #define RT5670_VENDOR_ID 0xfd
15 #define RT5670_VENDOR_ID1 0xfe
16 #define RT5670_VENDOR_ID2 0xff
18 #define RT5670_HP_VOL 0x02
19 #define RT5670_LOUT1 0x03
21 #define RT5670_CJ_CTRL1 0x0a
22 #define RT5670_CJ_CTRL2 0x0b
23 #define RT5670_CJ_CTRL3 0x0c
24 #define RT5670_IN2 0x0e
25 #define RT5670_INL1_INR1_VOL 0x0f
27 #define RT5670_DAC1_DIG_VOL 0x19
28 #define RT5670_DAC2_DIG_VOL 0x1a
29 #define RT5670_DAC_CTRL 0x1b
30 #define RT5670_STO1_ADC_DIG_VOL 0x1c
31 #define RT5670_MONO_ADC_DIG_VOL 0x1d
32 #define RT5670_ADC_BST_VOL1 0x1e
33 #define RT5670_STO2_ADC_DIG_VOL 0x1f
35 #define RT5670_ADC_BST_VOL2 0x20
36 #define RT5670_STO2_ADC_MIXER 0x26
37 #define RT5670_STO1_ADC_MIXER 0x27
38 #define RT5670_MONO_ADC_MIXER 0x28
39 #define RT5670_AD_DA_MIXER 0x29
40 #define RT5670_STO_DAC_MIXER 0x2a
41 #define RT5670_DD_MIXER 0x2b
42 #define RT5670_DIG_MIXER 0x2c
43 #define RT5670_DSP_PATH1 0x2d
44 #define RT5670_DSP_PATH2 0x2e
45 #define RT5670_DIG_INF1_DATA 0x2f
46 #define RT5670_DIG_INF2_DATA 0x30
48 #define RT5670_PDM_OUT_CTRL 0x31
49 #define RT5670_PDM_DATA_CTRL1 0x32
50 #define RT5670_PDM1_DATA_CTRL2 0x33
51 #define RT5670_PDM1_DATA_CTRL3 0x34
52 #define RT5670_PDM1_DATA_CTRL4 0x35
53 #define RT5670_PDM2_DATA_CTRL2 0x36
54 #define RT5670_PDM2_DATA_CTRL3 0x37
55 #define RT5670_PDM2_DATA_CTRL4 0x38
57 #define RT5670_REC_L1_MIXER 0x3b
58 #define RT5670_REC_L2_MIXER 0x3c
59 #define RT5670_REC_R1_MIXER 0x3d
60 #define RT5670_REC_R2_MIXER 0x3e
62 #define RT5670_HPO_MIXER 0x45
63 #define RT5670_MONO_MIXER 0x4c
64 #define RT5670_OUT_L1_MIXER 0x4f
65 #define RT5670_OUT_R1_MIXER 0x52
66 #define RT5670_LOUT_MIXER 0x53
68 #define RT5670_PWR_DIG1 0x61
69 #define RT5670_PWR_DIG2 0x62
70 #define RT5670_PWR_ANLG1 0x63
71 #define RT5670_PWR_ANLG2 0x64
72 #define RT5670_PWR_MIXER 0x65
73 #define RT5670_PWR_VOL 0x66
75 #define RT5670_PRIV_INDEX 0x6a
76 #define RT5670_PRIV_DATA 0x6c
78 #define RT5670_I2S4_SDP 0x6f
79 #define RT5670_I2S1_SDP 0x70
80 #define RT5670_I2S2_SDP 0x71
81 #define RT5670_I2S3_SDP 0x72
82 #define RT5670_ADDA_CLK1 0x73
83 #define RT5670_ADDA_CLK2 0x74
84 #define RT5670_DMIC_CTRL1 0x75
85 #define RT5670_DMIC_CTRL2 0x76
87 #define RT5670_TDM_CTRL_1 0x77
88 #define RT5670_TDM_CTRL_2 0x78
89 #define RT5670_TDM_CTRL_3 0x79
92 #define RT5670_DSP_CLK 0x7f
93 #define RT5670_GLB_CLK 0x80
94 #define RT5670_PLL_CTRL1 0x81
95 #define RT5670_PLL_CTRL2 0x82
96 #define RT5670_ASRC_1 0x83
97 #define RT5670_ASRC_2 0x84
98 #define RT5670_ASRC_3 0x85
99 #define RT5670_ASRC_4 0x86
100 #define RT5670_ASRC_5 0x87
101 #define RT5670_ASRC_7 0x89
102 #define RT5670_ASRC_8 0x8a
103 #define RT5670_ASRC_9 0x8b
104 #define RT5670_ASRC_10 0x8c
105 #define RT5670_ASRC_11 0x8d
106 #define RT5670_DEPOP_M1 0x8e
107 #define RT5670_DEPOP_M2 0x8f
108 #define RT5670_DEPOP_M3 0x90
109 #define RT5670_CHARGE_PUMP 0x91
110 #define RT5670_MICBIAS 0x93
111 #define RT5670_A_JD_CTRL1 0x94
112 #define RT5670_A_JD_CTRL2 0x95
113 #define RT5670_ASRC_12 0x97
114 #define RT5670_ASRC_13 0x98
115 #define RT5670_ASRC_14 0x99
116 #define RT5670_VAD_CTRL1 0x9a
117 #define RT5670_VAD_CTRL2 0x9b
118 #define RT5670_VAD_CTRL3 0x9c
119 #define RT5670_VAD_CTRL4 0x9d
120 #define RT5670_VAD_CTRL5 0x9e
122 #define RT5670_ADC_EQ_CTRL1 0xae
123 #define RT5670_ADC_EQ_CTRL2 0xaf
124 #define RT5670_EQ_CTRL1 0xb0
125 #define RT5670_EQ_CTRL2 0xb1
126 #define RT5670_ALC_DRC_CTRL1 0xb2
127 #define RT5670_ALC_DRC_CTRL2 0xb3
128 #define RT5670_ALC_CTRL_1 0xb4
129 #define RT5670_ALC_CTRL_2 0xb5
130 #define RT5670_ALC_CTRL_3 0xb6
131 #define RT5670_ALC_CTRL_4 0xb7
132 #define RT5670_JD_CTRL 0xbb
133 #define RT5670_IRQ_CTRL1 0xbd
134 #define RT5670_IRQ_CTRL2 0xbe
135 #define RT5670_INT_IRQ_ST 0xbf
136 #define RT5670_GPIO_CTRL1 0xc0
137 #define RT5670_GPIO_CTRL2 0xc1
138 #define RT5670_GPIO_CTRL3 0xc2
139 #define RT5670_SCRABBLE_FUN 0xcd
140 #define RT5670_SCRABBLE_CTRL 0xce
141 #define RT5670_BASE_BACK 0xcf
142 #define RT5670_MP3_PLUS1 0xd0
143 #define RT5670_MP3_PLUS2 0xd1
144 #define RT5670_ADJ_HPF1 0xd3
145 #define RT5670_ADJ_HPF2 0xd4
146 #define RT5670_HP_CALIB_AMP_DET 0xd6
147 #define RT5670_SV_ZCD1 0xd9
148 #define RT5670_SV_ZCD2 0xda
149 #define RT5670_IL_CMD 0xdb
150 #define RT5670_IL_CMD2 0xdc
151 #define RT5670_IL_CMD3 0xdd
152 #define RT5670_DRC_HL_CTRL1 0xe6
153 #define RT5670_DRC_HL_CTRL2 0xe7
154 #define RT5670_ADC_MONO_HP_CTRL1 0xec
155 #define RT5670_ADC_MONO_HP_CTRL2 0xed
156 #define RT5670_ADC_STO2_HP_CTRL1 0xee
157 #define RT5670_ADC_STO2_HP_CTRL2 0xef
158 #define RT5670_JD_CTRL3 0xf8
159 #define RT5670_JD_CTRL4 0xf9
161 #define RT5670_DIG_MISC 0xfa
162 #define RT5670_GEN_CTRL2 0xfb
163 #define RT5670_GEN_CTRL3 0xfc
167 #define RT5670_DIG_VOL 0x00
168 #define RT5670_PR_ALC_CTRL_1 0x01
169 #define RT5670_PR_ALC_CTRL_2 0x02
170 #define RT5670_PR_ALC_CTRL_3 0x03
171 #define RT5670_PR_ALC_CTRL_4 0x04
172 #define RT5670_PR_ALC_CTRL_5 0x05
173 #define RT5670_PR_ALC_CTRL_6 0x06
174 #define RT5670_BIAS_CUR1 0x12
175 #define RT5670_BIAS_CUR3 0x14
176 #define RT5670_CLSD_INT_REG1 0x1c
177 #define RT5670_MAMP_INT_REG2 0x37
178 #define RT5670_CHOP_DAC_ADC 0x3d
179 #define RT5670_MIXER_INT_REG 0x3f
180 #define RT5670_3D_SPK 0x63
181 #define RT5670_WND_1 0x6c
182 #define RT5670_WND_2 0x6d
183 #define RT5670_WND_3 0x6e
184 #define RT5670_WND_4 0x6f
185 #define RT5670_WND_5 0x70
186 #define RT5670_WND_8 0x73
187 #define RT5670_DIP_SPK_INF 0x75
188 #define RT5670_HP_DCC_INT1 0x77
189 #define RT5670_EQ_BW_LOP 0xa0
190 #define RT5670_EQ_GN_LOP 0xa1
191 #define RT5670_EQ_FC_BP1 0xa2
192 #define RT5670_EQ_BW_BP1 0xa3
193 #define RT5670_EQ_GN_BP1 0xa4
194 #define RT5670_EQ_FC_BP2 0xa5
195 #define RT5670_EQ_BW_BP2 0xa6
196 #define RT5670_EQ_GN_BP2 0xa7
197 #define RT5670_EQ_FC_BP3 0xa8
198 #define RT5670_EQ_BW_BP3 0xa9
199 #define RT5670_EQ_GN_BP3 0xaa
200 #define RT5670_EQ_FC_BP4 0xab
201 #define RT5670_EQ_BW_BP4 0xac
202 #define RT5670_EQ_GN_BP4 0xad
203 #define RT5670_EQ_FC_HIP1 0xae
204 #define RT5670_EQ_GN_HIP1 0xaf
205 #define RT5670_EQ_FC_HIP2 0xb0
206 #define RT5670_EQ_BW_HIP2 0xb1
207 #define RT5670_EQ_GN_HIP2 0xb2
208 #define RT5670_EQ_PRE_VOL 0xb3
209 #define RT5670_EQ_PST_VOL 0xb4
213 #define RT5670_L_MUTE (0x1 << 15)
215 #define RT5670_VOL_L_MUTE (0x1 << 14)
217 #define RT5670_R_MUTE (0x1 << 7)
219 #define RT5670_VOL_R_MUTE (0x1 << 6)
221 #define RT5670_L_VOL_MASK (0x3f << 8)
223 #define RT5670_R_VOL_MASK (0x3f)
224 #define RT5670_R_VOL_SFT 0
226 /* SW Reset & Device ID (0x00) */
227 #define RT5670_ID_MASK (0x3 << 1)
228 #define RT5670_ID_5670 (0x0 << 1)
229 #define RT5670_ID_5672 (0x1 << 1)
230 #define RT5670_ID_5671 (0x2 << 1)
232 /* Combo Jack Control 1 (0x0a) */
233 #define RT5670_CBJ_BST1_MASK (0xf << 12)
235 #define RT5670_CBJ_JD_HP_EN (0x1 << 9)
236 #define RT5670_CBJ_JD_MIC_EN (0x1 << 8)
237 #define RT5670_CBJ_BST1_EN (0x1 << 2)
239 /* Combo Jack Control 1 (0x0b) */
240 #define RT5670_CBJ_MN_JD (0x1 << 12)
241 #define RT5670_CAPLESS_EN (0x1 << 11)
242 #define RT5670_CBJ_DET_MODE (0x1 << 7)
244 /* IN2 Control (0x0e) */
245 #define RT5670_BST_MASK1 (0xf<<12)
247 #define RT5670_BST_MASK2 (0xf<<8)
249 #define RT5670_IN_DF1 (0x1 << 7)
251 #define RT5670_IN_DF2 (0x1 << 6)
254 /* INL and INR Volume Control (0x0f) */
255 #define RT5670_INL_SEL_MASK (0x1 << 15)
257 #define RT5670_INL_SEL_IN4P (0x0 << 15)
258 #define RT5670_INL_SEL_MONOP (0x1 << 15)
259 #define RT5670_INL_VOL_MASK (0x1f << 8)
261 #define RT5670_INR_SEL_MASK (0x1 << 7)
263 #define RT5670_INR_SEL_IN4N (0x0 << 7)
264 #define RT5670_INR_SEL_MONON (0x1 << 7)
265 #define RT5670_INR_VOL_MASK (0x1f)
266 #define RT5670_INR_VOL_SFT 0
268 /* Sidetone Control (0x18) */
269 #define RT5670_ST_SEL_MASK (0x7 << 9)
271 #define RT5670_M_ST_DACR2 (0x1 << 8)
273 #define RT5670_M_ST_DACL2 (0x1 << 7)
275 #define RT5670_ST_EN (0x1 << 6)
278 /* DAC1 Digital Volume (0x19) */
279 #define RT5670_DAC_L1_VOL_MASK (0xff << 8)
281 #define RT5670_DAC_R1_VOL_MASK (0xff)
282 #define RT5670_DAC_R1_VOL_SFT 0
284 /* DAC2 Digital Volume (0x1a) */
285 #define RT5670_DAC_L2_VOL_MASK (0xff << 8)
287 #define RT5670_DAC_R2_VOL_MASK (0xff)
288 #define RT5670_DAC_R2_VOL_SFT 0
290 /* DAC2 Control (0x1b) */
291 #define RT5670_M_DAC_L2_VOL (0x1 << 13)
293 #define RT5670_M_DAC_R2_VOL (0x1 << 12)
295 #define RT5670_DAC2_L_SEL_MASK (0x7 << 4)
297 #define RT5670_DAC2_R_SEL_MASK (0x7 << 0)
298 #define RT5670_DAC2_R_SEL_SFT 0
300 /* ADC Digital Volume Control (0x1c) */
301 #define RT5670_ADC_L_VOL_MASK (0x7f << 8)
303 #define RT5670_ADC_R_VOL_MASK (0x7f)
304 #define RT5670_ADC_R_VOL_SFT 0
306 /* Mono ADC Digital Volume Control (0x1d) */
307 #define RT5670_MONO_ADC_L_VOL_MASK (0x7f << 8)
309 #define RT5670_MONO_ADC_R_VOL_MASK (0x7f)
310 #define RT5670_MONO_ADC_R_VOL_SFT 0
312 /* ADC Boost Volume Control (0x1e) */
313 #define RT5670_STO1_ADC_L_BST_MASK (0x3 << 14)
315 #define RT5670_STO1_ADC_R_BST_MASK (0x3 << 12)
317 #define RT5670_STO1_ADC_COMP_MASK (0x3 << 10)
319 #define RT5670_STO2_ADC_L_BST_MASK (0x3 << 8)
321 #define RT5670_STO2_ADC_R_BST_MASK (0x3 << 6)
323 #define RT5670_STO2_ADC_COMP_MASK (0x3 << 4)
326 /* Stereo2 ADC Mixer Control (0x26) */
327 #define RT5670_STO2_ADC_SRC_MASK (0x1 << 15)
330 /* Stereo ADC Mixer Control (0x26 0x27) */
331 #define RT5670_M_ADC_L1 (0x1 << 14)
333 #define RT5670_M_ADC_L2 (0x1 << 13)
335 #define RT5670_ADC_1_SRC_MASK (0x1 << 12)
337 #define RT5670_ADC_1_SRC_ADC (0x1 << 12)
338 #define RT5670_ADC_1_SRC_DACMIX (0x0 << 12)
339 #define RT5670_ADC_2_SRC_MASK (0x1 << 11)
341 #define RT5670_ADC_SRC_MASK (0x1 << 10)
343 #define RT5670_DMIC_SRC_MASK (0x3 << 8)
345 #define RT5670_M_ADC_R1 (0x1 << 6)
347 #define RT5670_M_ADC_R2 (0x1 << 5)
349 #define RT5670_DMIC3_SRC_MASK (0x1 << 1)
350 #define RT5670_DMIC3_SRC_SFT 0
352 /* Mono ADC Mixer Control (0x28) */
353 #define RT5670_M_MONO_ADC_L1 (0x1 << 14)
355 #define RT5670_M_MONO_ADC_L2 (0x1 << 13)
357 #define RT5670_MONO_ADC_L1_SRC_MASK (0x1 << 12)
359 #define RT5670_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
360 #define RT5670_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
361 #define RT5670_MONO_ADC_L2_SRC_MASK (0x1 << 11)
363 #define RT5670_MONO_ADC_L_SRC_MASK (0x1 << 10)
365 #define RT5670_MONO_DMIC_L_SRC_MASK (0x3 << 8)
367 #define RT5670_M_MONO_ADC_R1 (0x1 << 6)
369 #define RT5670_M_MONO_ADC_R2 (0x1 << 5)
371 #define RT5670_MONO_ADC_R1_SRC_MASK (0x1 << 4)
373 #define RT5670_MONO_ADC_R1_SRC_ADCR (0x1 << 4)
374 #define RT5670_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4)
375 #define RT5670_MONO_ADC_R2_SRC_MASK (0x1 << 3)
377 #define RT5670_MONO_DMIC_R_SRC_MASK (0x3)
378 #define RT5670_MONO_DMIC_R_SRC_SFT 0
380 /* ADC Mixer to DAC Mixer Control (0x29) */
381 #define RT5670_M_ADCMIX_L (0x1 << 15)
383 #define RT5670_M_DAC1_L (0x1 << 14)
385 #define RT5670_DAC1_R_SEL_MASK (0x3 << 10)
387 #define RT5670_DAC1_R_SEL_IF1 (0x0 << 10)
388 #define RT5670_DAC1_R_SEL_IF2 (0x1 << 10)
389 #define RT5670_DAC1_R_SEL_IF3 (0x2 << 10)
390 #define RT5670_DAC1_R_SEL_IF4 (0x3 << 10)
391 #define RT5670_DAC1_L_SEL_MASK (0x3 << 8)
393 #define RT5670_DAC1_L_SEL_IF1 (0x0 << 8)
394 #define RT5670_DAC1_L_SEL_IF2 (0x1 << 8)
395 #define RT5670_DAC1_L_SEL_IF3 (0x2 << 8)
396 #define RT5670_DAC1_L_SEL_IF4 (0x3 << 8)
397 #define RT5670_M_ADCMIX_R (0x1 << 7)
399 #define RT5670_M_DAC1_R (0x1 << 6)
402 /* Stereo DAC Mixer Control (0x2a) */
403 #define RT5670_M_DAC_L1 (0x1 << 14)
405 #define RT5670_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
407 #define RT5670_M_DAC_L2 (0x1 << 12)
409 #define RT5670_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
411 #define RT5670_M_DAC_R1_STO_L (0x1 << 9)
413 #define RT5670_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
415 #define RT5670_M_DAC_R1 (0x1 << 6)
417 #define RT5670_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
419 #define RT5670_M_DAC_R2 (0x1 << 4)
421 #define RT5670_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
423 #define RT5670_M_DAC_L1_STO_R (0x1 << 1)
425 #define RT5670_DAC_L1_STO_R_VOL_MASK (0x1)
426 #define RT5670_DAC_L1_STO_R_VOL_SFT 0
428 /* Mono DAC Mixer Control (0x2b) */
429 #define RT5670_M_DAC_L1_MONO_L (0x1 << 14)
431 #define RT5670_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
433 #define RT5670_M_DAC_L2_MONO_L (0x1 << 12)
435 #define RT5670_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
437 #define RT5670_M_DAC_R2_MONO_L (0x1 << 10)
439 #define RT5670_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)
441 #define RT5670_M_DAC_R1_MONO_R (0x1 << 6)
443 #define RT5670_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)
445 #define RT5670_M_DAC_R2_MONO_R (0x1 << 4)
447 #define RT5670_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)
449 #define RT5670_M_DAC_L2_MONO_R (0x1 << 2)
451 #define RT5670_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)
454 /* Digital Mixer Control (0x2c) */
455 #define RT5670_M_STO_L_DAC_L (0x1 << 15)
457 #define RT5670_STO_L_DAC_L_VOL_MASK (0x1 << 14)
459 #define RT5670_M_DAC_L2_DAC_L (0x1 << 13)
461 #define RT5670_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
463 #define RT5670_M_STO_R_DAC_R (0x1 << 11)
465 #define RT5670_STO_R_DAC_R_VOL_MASK (0x1 << 10)
467 #define RT5670_M_DAC_R2_DAC_R (0x1 << 9)
469 #define RT5670_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
471 #define RT5670_M_DAC_R2_DAC_L (0x1 << 7)
473 #define RT5670_DAC_R2_DAC_L_VOL_MASK (0x1 << 6)
475 #define RT5670_M_DAC_L2_DAC_R (0x1 << 5)
477 #define RT5670_DAC_L2_DAC_R_VOL_MASK (0x1 << 4)
480 /* DSP Path Control 1 (0x2d) */
481 #define RT5670_RXDP_SEL_MASK (0x7 << 13)
483 #define RT5670_RXDP_SRC_MASK (0x3 << 11)
485 #define RT5670_RXDP_SRC_NOR (0x0 << 11)
486 #define RT5670_RXDP_SRC_DIV2 (0x1 << 11)
487 #define RT5670_RXDP_SRC_DIV3 (0x2 << 11)
488 #define RT5670_TXDP_SRC_MASK (0x3 << 4)
490 #define RT5670_TXDP_SRC_NOR (0x0 << 4)
491 #define RT5670_TXDP_SRC_DIV2 (0x1 << 4)
492 #define RT5670_TXDP_SRC_DIV3 (0x2 << 4)
493 #define RT5670_TXDP_SLOT_SEL_MASK (0x3 << 2)
495 #define RT5670_DSP_UL_SEL (0x1 << 1)
497 #define RT5670_DSP_DL_SEL 0x1
498 #define RT5670_DSP_DL_SFT 0
500 /* DSP Path Control 2 (0x2e) */
501 #define RT5670_TXDP_L_VOL_MASK (0x7f << 8)
503 #define RT5670_TXDP_R_VOL_MASK (0x7f)
504 #define RT5670_TXDP_R_VOL_SFT 0
506 /* Digital Interface Data Control (0x2f) */
507 #define RT5670_IF1_ADC2_IN_SEL (0x1 << 15)
509 #define RT5670_IF2_ADC_IN_MASK (0x7 << 12)
511 #define RT5670_IF2_DAC_SEL_MASK (0x3 << 10)
513 #define RT5670_IF2_ADC_SEL_MASK (0x3 << 8)
516 /* Digital Interface Data Control (0x30) */
517 #define RT5670_IF4_ADC_IN_MASK (0x3 << 4)
520 /* PDM Output Control (0x31) */
521 #define RT5670_PDM1_L_MASK (0x1 << 15)
523 #define RT5670_M_PDM1_L (0x1 << 14)
525 #define RT5670_PDM1_R_MASK (0x1 << 13)
527 #define RT5670_M_PDM1_R (0x1 << 12)
529 #define RT5670_PDM2_L_MASK (0x1 << 11)
531 #define RT5670_M_PDM2_L (0x1 << 10)
533 #define RT5670_PDM2_R_MASK (0x1 << 9)
535 #define RT5670_M_PDM2_R (0x1 << 8)
537 #define RT5670_PDM2_BUSY (0x1 << 7)
538 #define RT5670_PDM1_BUSY (0x1 << 6)
539 #define RT5670_PDM_PATTERN (0x1 << 5)
540 #define RT5670_PDM_GAIN (0x1 << 4)
541 #define RT5670_PDM_DIV_MASK (0x3)
543 /* REC Left Mixer Control 1 (0x3b) */
544 #define RT5670_G_HP_L_RM_L_MASK (0x7 << 13)
546 #define RT5670_G_IN_L_RM_L_MASK (0x7 << 10)
548 #define RT5670_G_BST4_RM_L_MASK (0x7 << 7)
550 #define RT5670_G_BST3_RM_L_MASK (0x7 << 4)
552 #define RT5670_G_BST2_RM_L_MASK (0x7 << 1)
555 /* REC Left Mixer Control 2 (0x3c) */
556 #define RT5670_G_BST1_RM_L_MASK (0x7 << 13)
558 #define RT5670_M_IN_L_RM_L (0x1 << 5)
560 #define RT5670_M_BST2_RM_L (0x1 << 3)
562 #define RT5670_M_BST1_RM_L (0x1 << 1)
565 /* REC Right Mixer Control 1 (0x3d) */
566 #define RT5670_G_HP_R_RM_R_MASK (0x7 << 13)
568 #define RT5670_G_IN_R_RM_R_MASK (0x7 << 10)
570 #define RT5670_G_BST4_RM_R_MASK (0x7 << 7)
572 #define RT5670_G_BST3_RM_R_MASK (0x7 << 4)
574 #define RT5670_G_BST2_RM_R_MASK (0x7 << 1)
577 /* REC Right Mixer Control 2 (0x3e) */
578 #define RT5670_G_BST1_RM_R_MASK (0x7 << 13)
580 #define RT5670_M_IN_R_RM_R (0x1 << 5)
582 #define RT5670_M_BST2_RM_R (0x1 << 3)
584 #define RT5670_M_BST1_RM_R (0x1 << 1)
587 /* HPMIX Control (0x45) */
588 #define RT5670_M_DAC2_HM (0x1 << 15)
590 #define RT5670_M_HPVOL_HM (0x1 << 14)
592 #define RT5670_M_DAC1_HM (0x1 << 13)
594 #define RT5670_G_HPOMIX_MASK (0x1 << 12)
596 #define RT5670_M_INR1_HMR (0x1 << 3)
598 #define RT5670_M_DACR1_HMR (0x1 << 2)
600 #define RT5670_M_INL1_HML (0x1 << 1)
602 #define RT5670_M_DACL1_HML (0x1)
603 #define RT5670_M_DACL1_HML_SFT 0
605 /* Mono Output Mixer Control (0x4c) */
606 #define RT5670_M_DAC_R2_MA (0x1 << 15)
608 #define RT5670_M_DAC_L2_MA (0x1 << 14)
610 #define RT5670_M_OV_R_MM (0x1 << 13)
612 #define RT5670_M_OV_L_MM (0x1 << 12)
614 #define RT5670_G_MONOMIX_MASK (0x1 << 10)
616 #define RT5670_M_DAC_R2_MM (0x1 << 9)
618 #define RT5670_M_DAC_L2_MM (0x1 << 8)
620 #define RT5670_M_BST4_MM (0x1 << 7)
623 /* Output Left Mixer Control 1 (0x4d) */
624 #define RT5670_G_BST3_OM_L_MASK (0x7 << 13)
626 #define RT5670_G_BST2_OM_L_MASK (0x7 << 10)
628 #define RT5670_G_BST1_OM_L_MASK (0x7 << 7)
630 #define RT5670_G_IN_L_OM_L_MASK (0x7 << 4)
632 #define RT5670_G_RM_L_OM_L_MASK (0x7 << 1)
635 /* Output Left Mixer Control 2 (0x4e) */
636 #define RT5670_G_DAC_R2_OM_L_MASK (0x7 << 13)
638 #define RT5670_G_DAC_L2_OM_L_MASK (0x7 << 10)
640 #define RT5670_G_DAC_L1_OM_L_MASK (0x7 << 7)
643 /* Output Left Mixer Control 3 (0x4f) */
644 #define RT5670_M_BST1_OM_L (0x1 << 5)
646 #define RT5670_M_IN_L_OM_L (0x1 << 4)
648 #define RT5670_M_DAC_L2_OM_L (0x1 << 1)
650 #define RT5670_M_DAC_L1_OM_L (0x1)
651 #define RT5670_M_DAC_L1_OM_L_SFT 0
653 /* Output Right Mixer Control 1 (0x50) */
654 #define RT5670_G_BST4_OM_R_MASK (0x7 << 13)
656 #define RT5670_G_BST2_OM_R_MASK (0x7 << 10)
658 #define RT5670_G_BST1_OM_R_MASK (0x7 << 7)
660 #define RT5670_G_IN_R_OM_R_MASK (0x7 << 4)
662 #define RT5670_G_RM_R_OM_R_MASK (0x7 << 1)
665 /* Output Right Mixer Control 2 (0x51) */
666 #define RT5670_G_DAC_L2_OM_R_MASK (0x7 << 13)
668 #define RT5670_G_DAC_R2_OM_R_MASK (0x7 << 10)
670 #define RT5670_G_DAC_R1_OM_R_MASK (0x7 << 7)
673 /* Output Right Mixer Control 3 (0x52) */
674 #define RT5670_M_BST2_OM_R (0x1 << 6)
676 #define RT5670_M_IN_R_OM_R (0x1 << 4)
678 #define RT5670_M_DAC_R2_OM_R (0x1 << 1)
680 #define RT5670_M_DAC_R1_OM_R (0x1)
681 #define RT5670_M_DAC_R1_OM_R_SFT 0
683 /* LOUT Mixer Control (0x53) */
684 #define RT5670_M_DAC_L1_LM (0x1 << 15)
686 #define RT5670_M_DAC_R1_LM (0x1 << 14)
688 #define RT5670_M_OV_L_LM (0x1 << 13)
690 #define RT5670_M_OV_R_LM (0x1 << 12)
692 #define RT5670_G_LOUTMIX_MASK (0x1 << 11)
695 /* Power Management for Digital 1 (0x61) */
696 #define RT5670_PWR_I2S1 (0x1 << 15)
698 #define RT5670_PWR_I2S2 (0x1 << 14)
700 #define RT5670_PWR_DAC_L1 (0x1 << 12)
702 #define RT5670_PWR_DAC_R1 (0x1 << 11)
704 #define RT5670_PWR_DAC_L2 (0x1 << 7)
706 #define RT5670_PWR_DAC_R2 (0x1 << 6)
708 #define RT5670_PWR_ADC_L (0x1 << 2)
710 #define RT5670_PWR_ADC_R (0x1 << 1)
712 #define RT5670_PWR_CLS_D (0x1)
713 #define RT5670_PWR_CLS_D_BIT 0
715 /* Power Management for Digital 2 (0x62) */
716 #define RT5670_PWR_ADC_S1F (0x1 << 15)
718 #define RT5670_PWR_ADC_MF_L (0x1 << 14)
720 #define RT5670_PWR_ADC_MF_R (0x1 << 13)
722 #define RT5670_PWR_I2S_DSP (0x1 << 12)
724 #define RT5670_PWR_DAC_S1F (0x1 << 11)
726 #define RT5670_PWR_DAC_MF_L (0x1 << 10)
728 #define RT5670_PWR_DAC_MF_R (0x1 << 9)
730 #define RT5670_PWR_ADC_S2F (0x1 << 8)
732 #define RT5670_PWR_PDM1 (0x1 << 7)
734 #define RT5670_PWR_PDM2 (0x1 << 6)
737 /* Power Management for Analog 1 (0x63) */
738 #define RT5670_PWR_VREF1 (0x1 << 15)
740 #define RT5670_PWR_FV1 (0x1 << 14)
742 #define RT5670_PWR_MB (0x1 << 13)
744 #define RT5670_PWR_LM (0x1 << 12)
746 #define RT5670_PWR_BG (0x1 << 11)
748 #define RT5670_PWR_HP_L (0x1 << 7)
750 #define RT5670_PWR_HP_R (0x1 << 6)
752 #define RT5670_PWR_HA (0x1 << 5)
754 #define RT5670_PWR_VREF2 (0x1 << 4)
756 #define RT5670_PWR_FV2 (0x1 << 3)
758 #define RT5670_LDO_SEL_MASK (0x7)
759 #define RT5670_LDO_SEL_SFT 0
761 /* Power Management for Analog 2 (0x64) */
762 #define RT5670_PWR_BST1 (0x1 << 15)
764 #define RT5670_PWR_BST2 (0x1 << 13)
766 #define RT5670_PWR_MB1 (0x1 << 11)
768 #define RT5670_PWR_MB2 (0x1 << 10)
770 #define RT5670_PWR_PLL (0x1 << 9)
772 #define RT5670_PWR_BST1_P (0x1 << 6)
774 #define RT5670_PWR_BST2_P (0x1 << 4)
776 #define RT5670_PWR_JD1 (0x1 << 2)
778 #define RT5670_PWR_JD (0x1 << 1)
781 /* Power Management for Mixer (0x65) */
782 #define RT5670_PWR_OM_L (0x1 << 15)
784 #define RT5670_PWR_OM_R (0x1 << 14)
786 #define RT5670_PWR_RM_L (0x1 << 11)
788 #define RT5670_PWR_RM_R (0x1 << 10)
791 /* Power Management for Volume (0x66) */
792 #define RT5670_PWR_HV_L (0x1 << 11)
794 #define RT5670_PWR_HV_R (0x1 << 10)
796 #define RT5670_PWR_IN_L (0x1 << 9)
798 #define RT5670_PWR_IN_R (0x1 << 8)
800 #define RT5670_PWR_MIC_DET (0x1 << 5)
803 /* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71 0x72) */
804 #define RT5670_I2S_MS_MASK (0x1 << 15)
806 #define RT5670_I2S_MS_M (0x0 << 15)
807 #define RT5670_I2S_MS_S (0x1 << 15)
808 #define RT5670_I2S_IF_MASK (0x7 << 12)
810 #define RT5670_I2S_O_CP_MASK (0x3 << 10)
812 #define RT5670_I2S_O_CP_OFF (0x0 << 10)
813 #define RT5670_I2S_O_CP_U_LAW (0x1 << 10)
814 #define RT5670_I2S_O_CP_A_LAW (0x2 << 10)
815 #define RT5670_I2S_I_CP_MASK (0x3 << 8)
817 #define RT5670_I2S_I_CP_OFF (0x0 << 8)
818 #define RT5670_I2S_I_CP_U_LAW (0x1 << 8)
819 #define RT5670_I2S_I_CP_A_LAW (0x2 << 8)
820 #define RT5670_I2S_BP_MASK (0x1 << 7)
822 #define RT5670_I2S_BP_NOR (0x0 << 7)
823 #define RT5670_I2S_BP_INV (0x1 << 7)
824 #define RT5670_I2S_DL_MASK (0x3 << 2)
826 #define RT5670_I2S_DL_16 (0x0 << 2)
827 #define RT5670_I2S_DL_20 (0x1 << 2)
828 #define RT5670_I2S_DL_24 (0x2 << 2)
829 #define RT5670_I2S_DL_8 (0x3 << 2)
830 #define RT5670_I2S_DF_MASK (0x3)
831 #define RT5670_I2S_DF_SFT 0
832 #define RT5670_I2S_DF_I2S (0x0)
833 #define RT5670_I2S_DF_LEFT (0x1)
834 #define RT5670_I2S_DF_PCM_A (0x2)
835 #define RT5670_I2S_DF_PCM_B (0x3)
837 /* I2S2 Audio Serial Data Port Control (0x71) */
838 #define RT5670_I2S2_SDI_MASK (0x1 << 6)
840 #define RT5670_I2S2_SDI_I2S1 (0x0 << 6)
841 #define RT5670_I2S2_SDI_I2S2 (0x1 << 6)
843 /* ADC/DAC Clock Control 1 (0x73) */
844 #define RT5670_I2S_BCLK_MS1_MASK (0x1 << 15)
846 #define RT5670_I2S_BCLK_MS1_32 (0x0 << 15)
847 #define RT5670_I2S_BCLK_MS1_64 (0x1 << 15)
848 #define RT5670_I2S_PD1_MASK (0x7 << 12)
850 #define RT5670_I2S_PD1_1 (0x0 << 12)
851 #define RT5670_I2S_PD1_2 (0x1 << 12)
852 #define RT5670_I2S_PD1_3 (0x2 << 12)
853 #define RT5670_I2S_PD1_4 (0x3 << 12)
854 #define RT5670_I2S_PD1_6 (0x4 << 12)
855 #define RT5670_I2S_PD1_8 (0x5 << 12)
856 #define RT5670_I2S_PD1_12 (0x6 << 12)
857 #define RT5670_I2S_PD1_16 (0x7 << 12)
858 #define RT5670_I2S_BCLK_MS2_MASK (0x1 << 11)
860 #define RT5670_I2S_BCLK_MS2_32 (0x0 << 11)
861 #define RT5670_I2S_BCLK_MS2_64 (0x1 << 11)
862 #define RT5670_I2S_PD2_MASK (0x7 << 8)
864 #define RT5670_I2S_PD2_1 (0x0 << 8)
865 #define RT5670_I2S_PD2_2 (0x1 << 8)
866 #define RT5670_I2S_PD2_3 (0x2 << 8)
867 #define RT5670_I2S_PD2_4 (0x3 << 8)
868 #define RT5670_I2S_PD2_6 (0x4 << 8)
869 #define RT5670_I2S_PD2_8 (0x5 << 8)
870 #define RT5670_I2S_PD2_12 (0x6 << 8)
871 #define RT5670_I2S_PD2_16 (0x7 << 8)
872 #define RT5670_I2S_BCLK_MS3_MASK (0x1 << 7)
874 #define RT5670_I2S_BCLK_MS3_32 (0x0 << 7)
875 #define RT5670_I2S_BCLK_MS3_64 (0x1 << 7)
876 #define RT5670_I2S_PD3_MASK (0x7 << 4)
878 #define RT5670_I2S_PD3_1 (0x0 << 4)
879 #define RT5670_I2S_PD3_2 (0x1 << 4)
880 #define RT5670_I2S_PD3_3 (0x2 << 4)
881 #define RT5670_I2S_PD3_4 (0x3 << 4)
882 #define RT5670_I2S_PD3_6 (0x4 << 4)
883 #define RT5670_I2S_PD3_8 (0x5 << 4)
884 #define RT5670_I2S_PD3_12 (0x6 << 4)
885 #define RT5670_I2S_PD3_16 (0x7 << 4)
886 #define RT5670_DAC_OSR_MASK (0x3 << 2)
888 #define RT5670_DAC_OSR_128 (0x0 << 2)
889 #define RT5670_DAC_OSR_64 (0x1 << 2)
890 #define RT5670_DAC_OSR_32 (0x2 << 2)
891 #define RT5670_DAC_OSR_16 (0x3 << 2)
892 #define RT5670_ADC_OSR_MASK (0x3)
893 #define RT5670_ADC_OSR_SFT 0
894 #define RT5670_ADC_OSR_128 (0x0)
895 #define RT5670_ADC_OSR_64 (0x1)
896 #define RT5670_ADC_OSR_32 (0x2)
897 #define RT5670_ADC_OSR_16 (0x3)
899 /* ADC/DAC Clock Control 2 (0x74) */
900 #define RT5670_DAC_L_OSR_MASK (0x3 << 14)
902 #define RT5670_DAC_L_OSR_128 (0x0 << 14)
903 #define RT5670_DAC_L_OSR_64 (0x1 << 14)
904 #define RT5670_DAC_L_OSR_32 (0x2 << 14)
905 #define RT5670_DAC_L_OSR_16 (0x3 << 14)
906 #define RT5670_ADC_R_OSR_MASK (0x3 << 12)
908 #define RT5670_ADC_R_OSR_128 (0x0 << 12)
909 #define RT5670_ADC_R_OSR_64 (0x1 << 12)
910 #define RT5670_ADC_R_OSR_32 (0x2 << 12)
911 #define RT5670_ADC_R_OSR_16 (0x3 << 12)
912 #define RT5670_DAHPF_EN (0x1 << 11)
914 #define RT5670_ADHPF_EN (0x1 << 10)
917 /* Digital Microphone Control (0x75) */
918 #define RT5670_DMIC_1_EN_MASK (0x1 << 15)
920 #define RT5670_DMIC_1_DIS (0x0 << 15)
921 #define RT5670_DMIC_1_EN (0x1 << 15)
922 #define RT5670_DMIC_2_EN_MASK (0x1 << 14)
924 #define RT5670_DMIC_2_DIS (0x0 << 14)
925 #define RT5670_DMIC_2_EN (0x1 << 14)
926 #define RT5670_DMIC_1L_LH_MASK (0x1 << 13)
928 #define RT5670_DMIC_1L_LH_FALLING (0x0 << 13)
929 #define RT5670_DMIC_1L_LH_RISING (0x1 << 13)
930 #define RT5670_DMIC_1R_LH_MASK (0x1 << 12)
932 #define RT5670_DMIC_1R_LH_FALLING (0x0 << 12)
933 #define RT5670_DMIC_1R_LH_RISING (0x1 << 12)
934 #define RT5670_DMIC_2_DP_MASK (0x1 << 10)
936 #define RT5670_DMIC_2_DP_GPIO8 (0x0 << 10)
937 #define RT5670_DMIC_2_DP_IN3N (0x1 << 10)
938 #define RT5670_DMIC_2L_LH_MASK (0x1 << 9)
940 #define RT5670_DMIC_2L_LH_FALLING (0x0 << 9)
941 #define RT5670_DMIC_2L_LH_RISING (0x1 << 9)
942 #define RT5670_DMIC_2R_LH_MASK (0x1 << 8)
944 #define RT5670_DMIC_2R_LH_FALLING (0x0 << 8)
945 #define RT5670_DMIC_2R_LH_RISING (0x1 << 8)
946 #define RT5670_DMIC_CLK_MASK (0x7 << 5)
948 #define RT5670_DMIC_3_EN_MASK (0x1 << 4)
950 #define RT5670_DMIC_3_DIS (0x0 << 4)
951 #define RT5670_DMIC_3_EN (0x1 << 4)
952 #define RT5670_DMIC_1_DP_MASK (0x3 << 0)
953 #define RT5670_DMIC_1_DP_SFT 0
954 #define RT5670_DMIC_1_DP_GPIO6 (0x0 << 0)
955 #define RT5670_DMIC_1_DP_IN2P (0x1 << 0)
956 #define RT5670_DMIC_1_DP_GPIO7 (0x2 << 0)
958 /* Digital Microphone Control2 (0x76) */
959 #define RT5670_DMIC_3_DP_MASK (0x3 << 6)
961 #define RT5670_DMIC_3_DP_GPIO9 (0x0 << 6)
962 #define RT5670_DMIC_3_DP_GPIO10 (0x1 << 6)
963 #define RT5670_DMIC_3_DP_GPIO5 (0x2 << 6)
965 /* Global Clock Control (0x80) */
966 #define RT5670_SCLK_SRC_MASK (0x3 << 14)
968 #define RT5670_SCLK_SRC_MCLK (0x0 << 14)
969 #define RT5670_SCLK_SRC_PLL1 (0x1 << 14)
970 #define RT5670_SCLK_SRC_RCCLK (0x2 << 14) /* 15MHz */
971 #define RT5670_PLL1_SRC_MASK (0x7 << 11)
973 #define RT5670_PLL1_SRC_MCLK (0x0 << 11)
974 #define RT5670_PLL1_SRC_BCLK1 (0x1 << 11)
975 #define RT5670_PLL1_SRC_BCLK2 (0x2 << 11)
976 #define RT5670_PLL1_SRC_BCLK3 (0x3 << 11)
977 #define RT5670_PLL1_PD_MASK (0x1 << 3)
979 #define RT5670_PLL1_PD_1 (0x0 << 3)
980 #define RT5670_PLL1_PD_2 (0x1 << 3)
984 /* PLL M/N/K Code Control 1 (0x81) */
985 #define RT5670_PLL_N_MAX 0x1ff
988 #define RT5670_PLL_K_MAX 0x1f
990 #define RT5670_PLL_K_SFT 0
992 /* PLL M/N/K Code Control 2 (0x82) */
993 #define RT5670_PLL_M_MAX 0xf
996 #define RT5670_PLL_M_BP (0x1 << 11)
999 /* ASRC Control 1 (0x83) */
1000 #define RT5670_STO_T_MASK (0x1 << 15)
1002 #define RT5670_STO_T_SCLK (0x0 << 15)
1003 #define RT5670_STO_T_LRCK1 (0x1 << 15)
1004 #define RT5670_M1_T_MASK (0x1 << 14)
1006 #define RT5670_M1_T_I2S2 (0x0 << 14)
1007 #define RT5670_M1_T_I2S2_D3 (0x1 << 14)
1008 #define RT5670_I2S2_F_MASK (0x1 << 12)
1010 #define RT5670_I2S2_F_I2S2_D2 (0x0 << 12)
1011 #define RT5670_I2S2_F_I2S1_TCLK (0x1 << 12)
1012 #define RT5670_DMIC_1_M_MASK (0x1 << 9)
1014 #define RT5670_DMIC_1_M_NOR (0x0 << 9)
1015 #define RT5670_DMIC_1_M_ASYN (0x1 << 9)
1016 #define RT5670_DMIC_2_M_MASK (0x1 << 8)
1018 #define RT5670_DMIC_2_M_NOR (0x0 << 8)
1019 #define RT5670_DMIC_2_M_ASYN (0x1 << 8)
1021 /* ASRC clock source selection (0x84, 0x85) */
1022 #define RT5670_CLK_SEL_SYS (0x0)
1023 #define RT5670_CLK_SEL_I2S1_ASRC (0x1)
1024 #define RT5670_CLK_SEL_I2S2_ASRC (0x2)
1025 #define RT5670_CLK_SEL_I2S3_ASRC (0x3)
1026 #define RT5670_CLK_SEL_SYS2 (0x5)
1027 #define RT5670_CLK_SEL_SYS3 (0x6)
1029 /* ASRC Control 2 (0x84) */
1030 #define RT5670_DA_STO_CLK_SEL_MASK (0xf << 12)
1032 #define RT5670_DA_MONOL_CLK_SEL_MASK (0xf << 8)
1034 #define RT5670_DA_MONOR_CLK_SEL_MASK (0xf << 4)
1036 #define RT5670_AD_STO1_CLK_SEL_MASK (0xf << 0)
1037 #define RT5670_AD_STO1_CLK_SEL_SFT 0
1039 /* ASRC Control 3 (0x85) */
1040 #define RT5670_UP_CLK_SEL_MASK (0xf << 12)
1042 #define RT5670_DOWN_CLK_SEL_MASK (0xf << 8)
1044 #define RT5670_AD_MONOL_CLK_SEL_MASK (0xf << 4)
1046 #define RT5670_AD_MONOR_CLK_SEL_MASK (0xf << 0)
1047 #define RT5670_AD_MONOR_CLK_SEL_SFT 0
1049 /* ASRC Control 4 (0x89) */
1050 #define RT5670_I2S1_PD_MASK (0x7 << 12)
1052 #define RT5670_I2S2_PD_MASK (0x7 << 8)
1055 /* HPOUT Over Current Detection (0x8b) */
1056 #define RT5670_HP_OVCD_MASK (0x1 << 10)
1058 #define RT5670_HP_OVCD_DIS (0x0 << 10)
1059 #define RT5670_HP_OVCD_EN (0x1 << 10)
1060 #define RT5670_HP_OC_TH_MASK (0x3 << 8)
1062 #define RT5670_HP_OC_TH_90 (0x0 << 8)
1063 #define RT5670_HP_OC_TH_105 (0x1 << 8)
1064 #define RT5670_HP_OC_TH_120 (0x2 << 8)
1065 #define RT5670_HP_OC_TH_135 (0x3 << 8)
1067 /* Class D Over Current Control (0x8c) */
1068 #define RT5670_CLSD_OC_MASK (0x1 << 9)
1070 #define RT5670_CLSD_OC_PU (0x0 << 9)
1071 #define RT5670_CLSD_OC_PD (0x1 << 9)
1072 #define RT5670_AUTO_PD_MASK (0x1 << 8)
1074 #define RT5670_AUTO_PD_DIS (0x0 << 8)
1075 #define RT5670_AUTO_PD_EN (0x1 << 8)
1076 #define RT5670_CLSD_OC_TH_MASK (0x3f)
1077 #define RT5670_CLSD_OC_TH_SFT 0
1079 /* Class D Output Control (0x8d) */
1080 #define RT5670_CLSD_RATIO_MASK (0xf << 12)
1082 #define RT5670_CLSD_OM_MASK (0x1 << 11)
1084 #define RT5670_CLSD_OM_MONO (0x0 << 11)
1085 #define RT5670_CLSD_OM_STO (0x1 << 11)
1086 #define RT5670_CLSD_SCH_MASK (0x1 << 10)
1088 #define RT5670_CLSD_SCH_L (0x0 << 10)
1089 #define RT5670_CLSD_SCH_S (0x1 << 10)
1091 /* Depop Mode Control 1 (0x8e) */
1092 #define RT5670_SMT_TRIG_MASK (0x1 << 15)
1094 #define RT5670_SMT_TRIG_DIS (0x0 << 15)
1095 #define RT5670_SMT_TRIG_EN (0x1 << 15)
1096 #define RT5670_HP_L_SMT_MASK (0x1 << 9)
1098 #define RT5670_HP_L_SMT_DIS (0x0 << 9)
1099 #define RT5670_HP_L_SMT_EN (0x1 << 9)
1100 #define RT5670_HP_R_SMT_MASK (0x1 << 8)
1102 #define RT5670_HP_R_SMT_DIS (0x0 << 8)
1103 #define RT5670_HP_R_SMT_EN (0x1 << 8)
1104 #define RT5670_HP_CD_PD_MASK (0x1 << 7)
1106 #define RT5670_HP_CD_PD_DIS (0x0 << 7)
1107 #define RT5670_HP_CD_PD_EN (0x1 << 7)
1108 #define RT5670_RSTN_MASK (0x1 << 6)
1110 #define RT5670_RSTN_DIS (0x0 << 6)
1111 #define RT5670_RSTN_EN (0x1 << 6)
1112 #define RT5670_RSTP_MASK (0x1 << 5)
1114 #define RT5670_RSTP_DIS (0x0 << 5)
1115 #define RT5670_RSTP_EN (0x1 << 5)
1116 #define RT5670_HP_CO_MASK (0x1 << 4)
1118 #define RT5670_HP_CO_DIS (0x0 << 4)
1119 #define RT5670_HP_CO_EN (0x1 << 4)
1120 #define RT5670_HP_CP_MASK (0x1 << 3)
1122 #define RT5670_HP_CP_PD (0x0 << 3)
1123 #define RT5670_HP_CP_PU (0x1 << 3)
1124 #define RT5670_HP_SG_MASK (0x1 << 2)
1126 #define RT5670_HP_SG_DIS (0x0 << 2)
1127 #define RT5670_HP_SG_EN (0x1 << 2)
1128 #define RT5670_HP_DP_MASK (0x1 << 1)
1130 #define RT5670_HP_DP_PD (0x0 << 1)
1131 #define RT5670_HP_DP_PU (0x1 << 1)
1132 #define RT5670_HP_CB_MASK (0x1)
1133 #define RT5670_HP_CB_SFT 0
1134 #define RT5670_HP_CB_PD (0x0)
1135 #define RT5670_HP_CB_PU (0x1)
1137 /* Depop Mode Control 2 (0x8f) */
1138 #define RT5670_DEPOP_MASK (0x1 << 13)
1140 #define RT5670_DEPOP_AUTO (0x0 << 13)
1141 #define RT5670_DEPOP_MAN (0x1 << 13)
1142 #define RT5670_RAMP_MASK (0x1 << 12)
1144 #define RT5670_RAMP_DIS (0x0 << 12)
1145 #define RT5670_RAMP_EN (0x1 << 12)
1146 #define RT5670_BPS_MASK (0x1 << 11)
1148 #define RT5670_BPS_DIS (0x0 << 11)
1149 #define RT5670_BPS_EN (0x1 << 11)
1150 #define RT5670_FAST_UPDN_MASK (0x1 << 10)
1152 #define RT5670_FAST_UPDN_DIS (0x0 << 10)
1153 #define RT5670_FAST_UPDN_EN (0x1 << 10)
1154 #define RT5670_MRES_MASK (0x3 << 8)
1156 #define RT5670_MRES_15MO (0x0 << 8)
1157 #define RT5670_MRES_25MO (0x1 << 8)
1158 #define RT5670_MRES_35MO (0x2 << 8)
1159 #define RT5670_MRES_45MO (0x3 << 8)
1160 #define RT5670_VLO_MASK (0x1 << 7)
1162 #define RT5670_VLO_3V (0x0 << 7)
1163 #define RT5670_VLO_32V (0x1 << 7)
1164 #define RT5670_DIG_DP_MASK (0x1 << 6)
1166 #define RT5670_DIG_DP_DIS (0x0 << 6)
1167 #define RT5670_DIG_DP_EN (0x1 << 6)
1168 #define RT5670_DP_TH_MASK (0x3 << 4)
1171 /* Depop Mode Control 3 (0x90) */
1172 #define RT5670_CP_SYS_MASK (0x7 << 12)
1174 #define RT5670_CP_FQ1_MASK (0x7 << 8)
1176 #define RT5670_CP_FQ2_MASK (0x7 << 4)
1178 #define RT5670_CP_FQ3_MASK (0x7)
1179 #define RT5670_CP_FQ3_SFT 0
1180 #define RT5670_CP_FQ_1_5_KHZ 0
1189 /* HPOUT charge pump (0x91) */
1190 #define RT5670_OSW_L_MASK (0x1 << 11)
1192 #define RT5670_OSW_L_DIS (0x0 << 11)
1193 #define RT5670_OSW_L_EN (0x1 << 11)
1194 #define RT5670_OSW_R_MASK (0x1 << 10)
1196 #define RT5670_OSW_R_DIS (0x0 << 10)
1197 #define RT5670_OSW_R_EN (0x1 << 10)
1198 #define RT5670_PM_HP_MASK (0x3 << 8)
1200 #define RT5670_PM_HP_LV (0x0 << 8)
1201 #define RT5670_PM_HP_MV (0x1 << 8)
1202 #define RT5670_PM_HP_HV (0x2 << 8)
1203 #define RT5670_IB_HP_MASK (0x3 << 6)
1205 #define RT5670_IB_HP_125IL (0x0 << 6)
1206 #define RT5670_IB_HP_25IL (0x1 << 6)
1207 #define RT5670_IB_HP_5IL (0x2 << 6)
1208 #define RT5670_IB_HP_1IL (0x3 << 6)
1210 /* PV detection and SPK gain control (0x92) */
1211 #define RT5670_PVDD_DET_MASK (0x1 << 15)
1213 #define RT5670_PVDD_DET_DIS (0x0 << 15)
1214 #define RT5670_PVDD_DET_EN (0x1 << 15)
1215 #define RT5670_SPK_AG_MASK (0x1 << 14)
1217 #define RT5670_SPK_AG_DIS (0x0 << 14)
1218 #define RT5670_SPK_AG_EN (0x1 << 14)
1220 /* Micbias Control (0x93) */
1221 #define RT5670_MIC1_BS_MASK (0x1 << 15)
1223 #define RT5670_MIC1_BS_9AV (0x0 << 15)
1224 #define RT5670_MIC1_BS_75AV (0x1 << 15)
1225 #define RT5670_MIC2_BS_MASK (0x1 << 14)
1227 #define RT5670_MIC2_BS_9AV (0x0 << 14)
1228 #define RT5670_MIC2_BS_75AV (0x1 << 14)
1229 #define RT5670_MIC1_CLK_MASK (0x1 << 13)
1231 #define RT5670_MIC1_CLK_DIS (0x0 << 13)
1232 #define RT5670_MIC1_CLK_EN (0x1 << 13)
1233 #define RT5670_MIC2_CLK_MASK (0x1 << 12)
1235 #define RT5670_MIC2_CLK_DIS (0x0 << 12)
1236 #define RT5670_MIC2_CLK_EN (0x1 << 12)
1237 #define RT5670_MIC1_OVCD_MASK (0x1 << 11)
1239 #define RT5670_MIC1_OVCD_DIS (0x0 << 11)
1240 #define RT5670_MIC1_OVCD_EN (0x1 << 11)
1241 #define RT5670_MIC1_OVTH_MASK (0x3 << 9)
1243 #define RT5670_MIC1_OVTH_600UA (0x0 << 9)
1244 #define RT5670_MIC1_OVTH_1500UA (0x1 << 9)
1245 #define RT5670_MIC1_OVTH_2000UA (0x2 << 9)
1246 #define RT5670_MIC2_OVCD_MASK (0x1 << 8)
1248 #define RT5670_MIC2_OVCD_DIS (0x0 << 8)
1249 #define RT5670_MIC2_OVCD_EN (0x1 << 8)
1250 #define RT5670_MIC2_OVTH_MASK (0x3 << 6)
1252 #define RT5670_MIC2_OVTH_600UA (0x0 << 6)
1253 #define RT5670_MIC2_OVTH_1500UA (0x1 << 6)
1254 #define RT5670_MIC2_OVTH_2000UA (0x2 << 6)
1255 #define RT5670_PWR_MB_MASK (0x1 << 5)
1257 #define RT5670_PWR_MB_PD (0x0 << 5)
1258 #define RT5670_PWR_MB_PU (0x1 << 5)
1259 #define RT5670_PWR_CLK25M_MASK (0x1 << 4)
1261 #define RT5670_PWR_CLK25M_PD (0x0 << 4)
1262 #define RT5670_PWR_CLK25M_PU (0x1 << 4)
1264 /* Analog JD Control 1 (0x94) */
1265 #define RT5670_JD1_MODE_MASK (0x3 << 0)
1266 #define RT5670_JD1_MODE_0 (0x0 << 0)
1267 #define RT5670_JD1_MODE_1 (0x1 << 0)
1268 #define RT5670_JD1_MODE_2 (0x2 << 0)
1270 /* VAD Control 4 (0x9d) */
1271 #define RT5670_VAD_SEL_MASK (0x3 << 8)
1274 /* EQ Control 1 (0xb0) */
1275 #define RT5670_EQ_SRC_MASK (0x1 << 15)
1277 #define RT5670_EQ_SRC_DAC (0x0 << 15)
1278 #define RT5670_EQ_SRC_ADC (0x1 << 15)
1279 #define RT5670_EQ_UPD (0x1 << 14)
1281 #define RT5670_EQ_CD_MASK (0x1 << 13)
1283 #define RT5670_EQ_CD_DIS (0x0 << 13)
1284 #define RT5670_EQ_CD_EN (0x1 << 13)
1285 #define RT5670_EQ_DITH_MASK (0x3 << 8)
1287 #define RT5670_EQ_DITH_NOR (0x0 << 8)
1288 #define RT5670_EQ_DITH_LSB (0x1 << 8)
1289 #define RT5670_EQ_DITH_LSB_1 (0x2 << 8)
1290 #define RT5670_EQ_DITH_LSB_2 (0x3 << 8)
1292 /* EQ Control 2 (0xb1) */
1293 #define RT5670_EQ_HPF1_M_MASK (0x1 << 8)
1295 #define RT5670_EQ_HPF1_M_HI (0x0 << 8)
1296 #define RT5670_EQ_HPF1_M_1ST (0x1 << 8)
1297 #define RT5670_EQ_LPF1_M_MASK (0x1 << 7)
1299 #define RT5670_EQ_LPF1_M_LO (0x0 << 7)
1300 #define RT5670_EQ_LPF1_M_1ST (0x1 << 7)
1301 #define RT5670_EQ_HPF2_MASK (0x1 << 6)
1303 #define RT5670_EQ_HPF2_DIS (0x0 << 6)
1304 #define RT5670_EQ_HPF2_EN (0x1 << 6)
1305 #define RT5670_EQ_HPF1_MASK (0x1 << 5)
1307 #define RT5670_EQ_HPF1_DIS (0x0 << 5)
1308 #define RT5670_EQ_HPF1_EN (0x1 << 5)
1309 #define RT5670_EQ_BPF4_MASK (0x1 << 4)
1311 #define RT5670_EQ_BPF4_DIS (0x0 << 4)
1312 #define RT5670_EQ_BPF4_EN (0x1 << 4)
1313 #define RT5670_EQ_BPF3_MASK (0x1 << 3)
1315 #define RT5670_EQ_BPF3_DIS (0x0 << 3)
1316 #define RT5670_EQ_BPF3_EN (0x1 << 3)
1317 #define RT5670_EQ_BPF2_MASK (0x1 << 2)
1319 #define RT5670_EQ_BPF2_DIS (0x0 << 2)
1320 #define RT5670_EQ_BPF2_EN (0x1 << 2)
1321 #define RT5670_EQ_BPF1_MASK (0x1 << 1)
1323 #define RT5670_EQ_BPF1_DIS (0x0 << 1)
1324 #define RT5670_EQ_BPF1_EN (0x1 << 1)
1325 #define RT5670_EQ_LPF_MASK (0x1)
1326 #define RT5670_EQ_LPF_SFT 0
1327 #define RT5670_EQ_LPF_DIS (0x0)
1328 #define RT5670_EQ_LPF_EN (0x1)
1329 #define RT5670_EQ_CTRL_MASK (0x7f)
1331 /* Memory Test (0xb2) */
1332 #define RT5670_MT_MASK (0x1 << 15)
1334 #define RT5670_MT_DIS (0x0 << 15)
1335 #define RT5670_MT_EN (0x1 << 15)
1337 /* DRC/AGC Control 1 (0xb4) */
1338 #define RT5670_DRC_AGC_P_MASK (0x1 << 15)
1340 #define RT5670_DRC_AGC_P_DAC (0x0 << 15)
1341 #define RT5670_DRC_AGC_P_ADC (0x1 << 15)
1342 #define RT5670_DRC_AGC_MASK (0x1 << 14)
1344 #define RT5670_DRC_AGC_DIS (0x0 << 14)
1345 #define RT5670_DRC_AGC_EN (0x1 << 14)
1346 #define RT5670_DRC_AGC_UPD (0x1 << 13)
1348 #define RT5670_DRC_AGC_AR_MASK (0x1f << 8)
1350 #define RT5670_DRC_AGC_R_MASK (0x7 << 5)
1352 #define RT5670_DRC_AGC_R_48K (0x1 << 5)
1353 #define RT5670_DRC_AGC_R_96K (0x2 << 5)
1354 #define RT5670_DRC_AGC_R_192K (0x3 << 5)
1355 #define RT5670_DRC_AGC_R_441K (0x5 << 5)
1356 #define RT5670_DRC_AGC_R_882K (0x6 << 5)
1357 #define RT5670_DRC_AGC_R_1764K (0x7 << 5)
1358 #define RT5670_DRC_AGC_RC_MASK (0x1f)
1359 #define RT5670_DRC_AGC_RC_SFT 0
1361 /* DRC/AGC Control 2 (0xb5) */
1362 #define RT5670_DRC_AGC_POB_MASK (0x3f << 8)
1364 #define RT5670_DRC_AGC_CP_MASK (0x1 << 7)
1366 #define RT5670_DRC_AGC_CP_DIS (0x0 << 7)
1367 #define RT5670_DRC_AGC_CP_EN (0x1 << 7)
1368 #define RT5670_DRC_AGC_CPR_MASK (0x3 << 5)
1370 #define RT5670_DRC_AGC_CPR_1_1 (0x0 << 5)
1371 #define RT5670_DRC_AGC_CPR_1_2 (0x1 << 5)
1372 #define RT5670_DRC_AGC_CPR_1_3 (0x2 << 5)
1373 #define RT5670_DRC_AGC_CPR_1_4 (0x3 << 5)
1374 #define RT5670_DRC_AGC_PRB_MASK (0x1f)
1375 #define RT5670_DRC_AGC_PRB_SFT 0
1377 /* DRC/AGC Control 3 (0xb6) */
1378 #define RT5670_DRC_AGC_NGB_MASK (0xf << 12)
1380 #define RT5670_DRC_AGC_TAR_MASK (0x1f << 7)
1382 #define RT5670_DRC_AGC_NG_MASK (0x1 << 6)
1384 #define RT5670_DRC_AGC_NG_DIS (0x0 << 6)
1385 #define RT5670_DRC_AGC_NG_EN (0x1 << 6)
1386 #define RT5670_DRC_AGC_NGH_MASK (0x1 << 5)
1388 #define RT5670_DRC_AGC_NGH_DIS (0x0 << 5)
1389 #define RT5670_DRC_AGC_NGH_EN (0x1 << 5)
1390 #define RT5670_DRC_AGC_NGT_MASK (0x1f)
1391 #define RT5670_DRC_AGC_NGT_SFT 0
1393 /* Jack Detect Control (0xbb) */
1394 #define RT5670_JD_MASK (0x7 << 13)
1396 #define RT5670_JD_DIS (0x0 << 13)
1397 #define RT5670_JD_GPIO1 (0x1 << 13)
1398 #define RT5670_JD_JD1_IN4P (0x2 << 13)
1399 #define RT5670_JD_JD2_IN4N (0x3 << 13)
1400 #define RT5670_JD_GPIO2 (0x4 << 13)
1401 #define RT5670_JD_GPIO3 (0x5 << 13)
1402 #define RT5670_JD_GPIO4 (0x6 << 13)
1403 #define RT5670_JD_HP_MASK (0x1 << 11)
1405 #define RT5670_JD_HP_DIS (0x0 << 11)
1406 #define RT5670_JD_HP_EN (0x1 << 11)
1407 #define RT5670_JD_HP_TRG_MASK (0x1 << 10)
1409 #define RT5670_JD_HP_TRG_LO (0x0 << 10)
1410 #define RT5670_JD_HP_TRG_HI (0x1 << 10)
1411 #define RT5670_JD_SPL_MASK (0x1 << 9)
1413 #define RT5670_JD_SPL_DIS (0x0 << 9)
1414 #define RT5670_JD_SPL_EN (0x1 << 9)
1415 #define RT5670_JD_SPL_TRG_MASK (0x1 << 8)
1417 #define RT5670_JD_SPL_TRG_LO (0x0 << 8)
1418 #define RT5670_JD_SPL_TRG_HI (0x1 << 8)
1419 #define RT5670_JD_SPR_MASK (0x1 << 7)
1421 #define RT5670_JD_SPR_DIS (0x0 << 7)
1422 #define RT5670_JD_SPR_EN (0x1 << 7)
1423 #define RT5670_JD_SPR_TRG_MASK (0x1 << 6)
1425 #define RT5670_JD_SPR_TRG_LO (0x0 << 6)
1426 #define RT5670_JD_SPR_TRG_HI (0x1 << 6)
1427 #define RT5670_JD_MO_MASK (0x1 << 5)
1429 #define RT5670_JD_MO_DIS (0x0 << 5)
1430 #define RT5670_JD_MO_EN (0x1 << 5)
1431 #define RT5670_JD_MO_TRG_MASK (0x1 << 4)
1433 #define RT5670_JD_MO_TRG_LO (0x0 << 4)
1434 #define RT5670_JD_MO_TRG_HI (0x1 << 4)
1435 #define RT5670_JD_LO_MASK (0x1 << 3)
1437 #define RT5670_JD_LO_DIS (0x0 << 3)
1438 #define RT5670_JD_LO_EN (0x1 << 3)
1439 #define RT5670_JD_LO_TRG_MASK (0x1 << 2)
1441 #define RT5670_JD_LO_TRG_LO (0x0 << 2)
1442 #define RT5670_JD_LO_TRG_HI (0x1 << 2)
1443 #define RT5670_JD1_IN4P_MASK (0x1 << 1)
1445 #define RT5670_JD1_IN4P_DIS (0x0 << 1)
1446 #define RT5670_JD1_IN4P_EN (0x1 << 1)
1447 #define RT5670_JD2_IN4N_MASK (0x1)
1448 #define RT5670_JD2_IN4N_SFT 0
1449 #define RT5670_JD2_IN4N_DIS (0x0)
1450 #define RT5670_JD2_IN4N_EN (0x1)
1452 /* IRQ Control 1 (0xbd) */
1453 #define RT5670_IRQ_JD_MASK (0x1 << 15)
1455 #define RT5670_IRQ_JD_BP (0x0 << 15)
1456 #define RT5670_IRQ_JD_NOR (0x1 << 15)
1457 #define RT5670_IRQ_OT_MASK (0x1 << 14)
1459 #define RT5670_IRQ_OT_BP (0x0 << 14)
1460 #define RT5670_IRQ_OT_NOR (0x1 << 14)
1461 #define RT5670_JD_STKY_MASK (0x1 << 13)
1463 #define RT5670_JD_STKY_DIS (0x0 << 13)
1464 #define RT5670_JD_STKY_EN (0x1 << 13)
1465 #define RT5670_OT_STKY_MASK (0x1 << 12)
1467 #define RT5670_OT_STKY_DIS (0x0 << 12)
1468 #define RT5670_OT_STKY_EN (0x1 << 12)
1469 #define RT5670_JD_P_MASK (0x1 << 11)
1471 #define RT5670_JD_P_NOR (0x0 << 11)
1472 #define RT5670_JD_P_INV (0x1 << 11)
1473 #define RT5670_OT_P_MASK (0x1 << 10)
1475 #define RT5670_OT_P_NOR (0x0 << 10)
1476 #define RT5670_OT_P_INV (0x1 << 10)
1477 #define RT5670_JD1_1_EN_MASK (0x1 << 9)
1479 #define RT5670_JD1_1_DIS (0x0 << 9)
1480 #define RT5670_JD1_1_EN (0x1 << 9)
1482 /* IRQ Control 2 (0xbe) */
1483 #define RT5670_IRQ_MB1_OC_MASK (0x1 << 15)
1485 #define RT5670_IRQ_MB1_OC_BP (0x0 << 15)
1486 #define RT5670_IRQ_MB1_OC_NOR (0x1 << 15)
1487 #define RT5670_IRQ_MB2_OC_MASK (0x1 << 14)
1489 #define RT5670_IRQ_MB2_OC_BP (0x0 << 14)
1490 #define RT5670_IRQ_MB2_OC_NOR (0x1 << 14)
1491 #define RT5670_MB1_OC_STKY_MASK (0x1 << 11)
1493 #define RT5670_MB1_OC_STKY_DIS (0x0 << 11)
1494 #define RT5670_MB1_OC_STKY_EN (0x1 << 11)
1495 #define RT5670_MB2_OC_STKY_MASK (0x1 << 10)
1497 #define RT5670_MB2_OC_STKY_DIS (0x0 << 10)
1498 #define RT5670_MB2_OC_STKY_EN (0x1 << 10)
1499 #define RT5670_MB1_OC_P_MASK (0x1 << 7)
1501 #define RT5670_MB1_OC_P_NOR (0x0 << 7)
1502 #define RT5670_MB1_OC_P_INV (0x1 << 7)
1503 #define RT5670_MB2_OC_P_MASK (0x1 << 6)
1505 #define RT5670_MB2_OC_P_NOR (0x0 << 6)
1506 #define RT5670_MB2_OC_P_INV (0x1 << 6)
1507 #define RT5670_MB1_OC_CLR (0x1 << 3)
1509 #define RT5670_MB2_OC_CLR (0x1 << 2)
1512 /* GPIO Control 1 (0xc0) */
1513 #define RT5670_GP1_PIN_MASK (0x1 << 15)
1515 #define RT5670_GP1_PIN_GPIO1 (0x0 << 15)
1516 #define RT5670_GP1_PIN_IRQ (0x1 << 15)
1517 #define RT5670_GP2_PIN_MASK (0x1 << 14)
1519 #define RT5670_GP2_PIN_GPIO2 (0x0 << 14)
1520 #define RT5670_GP2_PIN_DMIC1_SCL (0x1 << 14)
1521 #define RT5670_GP3_PIN_MASK (0x3 << 12)
1523 #define RT5670_GP3_PIN_GPIO3 (0x0 << 12)
1524 #define RT5670_GP3_PIN_DMIC1_SDA (0x1 << 12)
1525 #define RT5670_GP3_PIN_IRQ (0x2 << 12)
1526 #define RT5670_GP4_PIN_MASK (0x1 << 11)
1528 #define RT5670_GP4_PIN_GPIO4 (0x0 << 11)
1529 #define RT5670_GP4_PIN_DMIC2_SDA (0x1 << 11)
1530 #define RT5670_DP_SIG_MASK (0x1 << 10)
1532 #define RT5670_DP_SIG_TEST (0x0 << 10)
1533 #define RT5670_DP_SIG_AP (0x1 << 10)
1534 #define RT5670_GPIO_M_MASK (0x1 << 9)
1536 #define RT5670_GPIO_M_FLT (0x0 << 9)
1537 #define RT5670_GPIO_M_PH (0x1 << 9)
1538 #define RT5670_I2S2_PIN_MASK (0x1 << 8)
1540 #define RT5670_I2S2_PIN_I2S (0x0 << 8)
1541 #define RT5670_I2S2_PIN_GPIO (0x1 << 8)
1542 #define RT5670_GP5_PIN_MASK (0x1 << 7)
1544 #define RT5670_GP5_PIN_GPIO5 (0x0 << 7)
1545 #define RT5670_GP5_PIN_DMIC3_SDA (0x1 << 7)
1546 #define RT5670_GP6_PIN_MASK (0x1 << 6)
1548 #define RT5670_GP6_PIN_GPIO6 (0x0 << 6)
1549 #define RT5670_GP6_PIN_DMIC1_SDA (0x1 << 6)
1550 #define RT5670_GP7_PIN_MASK (0x3 << 4)
1552 #define RT5670_GP7_PIN_GPIO7 (0x0 << 4)
1553 #define RT5670_GP7_PIN_DMIC1_SDA (0x1 << 4)
1554 #define RT5670_GP7_PIN_PDM_SCL2 (0x2 << 4)
1555 #define RT5670_GP8_PIN_MASK (0x1 << 3)
1557 #define RT5670_GP8_PIN_GPIO8 (0x0 << 3)
1558 #define RT5670_GP8_PIN_DMIC2_SDA (0x1 << 3)
1559 #define RT5670_GP9_PIN_MASK (0x1 << 2)
1561 #define RT5670_GP9_PIN_GPIO9 (0x0 << 2)
1562 #define RT5670_GP9_PIN_DMIC3_SDA (0x1 << 2)
1563 #define RT5670_GP10_PIN_MASK (0x3)
1564 #define RT5670_GP10_PIN_SFT 0
1565 #define RT5670_GP10_PIN_GPIO9 (0x0)
1566 #define RT5670_GP10_PIN_DMIC3_SDA (0x1)
1567 #define RT5670_GP10_PIN_PDM_ADT2 (0x2)
1569 /* GPIO Control 2 (0xc1) */
1570 #define RT5670_GP4_PF_MASK (0x1 << 11)
1572 #define RT5670_GP4_PF_IN (0x0 << 11)
1573 #define RT5670_GP4_PF_OUT (0x1 << 11)
1574 #define RT5670_GP4_OUT_MASK (0x1 << 10)
1576 #define RT5670_GP4_OUT_LO (0x0 << 10)
1577 #define RT5670_GP4_OUT_HI (0x1 << 10)
1578 #define RT5670_GP4_P_MASK (0x1 << 9)
1580 #define RT5670_GP4_P_NOR (0x0 << 9)
1581 #define RT5670_GP4_P_INV (0x1 << 9)
1582 #define RT5670_GP3_PF_MASK (0x1 << 8)
1584 #define RT5670_GP3_PF_IN (0x0 << 8)
1585 #define RT5670_GP3_PF_OUT (0x1 << 8)
1586 #define RT5670_GP3_OUT_MASK (0x1 << 7)
1588 #define RT5670_GP3_OUT_LO (0x0 << 7)
1589 #define RT5670_GP3_OUT_HI (0x1 << 7)
1590 #define RT5670_GP3_P_MASK (0x1 << 6)
1592 #define RT5670_GP3_P_NOR (0x0 << 6)
1593 #define RT5670_GP3_P_INV (0x1 << 6)
1594 #define RT5670_GP2_PF_MASK (0x1 << 5)
1596 #define RT5670_GP2_PF_IN (0x0 << 5)
1597 #define RT5670_GP2_PF_OUT (0x1 << 5)
1598 #define RT5670_GP2_OUT_MASK (0x1 << 4)
1600 #define RT5670_GP2_OUT_LO (0x0 << 4)
1601 #define RT5670_GP2_OUT_HI (0x1 << 4)
1602 #define RT5670_GP2_P_MASK (0x1 << 3)
1604 #define RT5670_GP2_P_NOR (0x0 << 3)
1605 #define RT5670_GP2_P_INV (0x1 << 3)
1606 #define RT5670_GP1_PF_MASK (0x1 << 2)
1608 #define RT5670_GP1_PF_IN (0x0 << 2)
1609 #define RT5670_GP1_PF_OUT (0x1 << 2)
1610 #define RT5670_GP1_OUT_MASK (0x1 << 1)
1612 #define RT5670_GP1_OUT_LO (0x0 << 1)
1613 #define RT5670_GP1_OUT_HI (0x1 << 1)
1614 #define RT5670_GP1_P_MASK (0x1)
1615 #define RT5670_GP1_P_SFT 0
1616 #define RT5670_GP1_P_NOR (0x0)
1617 #define RT5670_GP1_P_INV (0x1)
1619 /* Scramble Function (0xcd) */
1620 #define RT5670_SCB_KEY_MASK (0xff)
1621 #define RT5670_SCB_KEY_SFT 0
1623 /* Scramble Control (0xce) */
1624 #define RT5670_SCB_SWAP_MASK (0x1 << 15)
1626 #define RT5670_SCB_SWAP_DIS (0x0 << 15)
1627 #define RT5670_SCB_SWAP_EN (0x1 << 15)
1628 #define RT5670_SCB_MASK (0x1 << 14)
1630 #define RT5670_SCB_DIS (0x0 << 14)
1631 #define RT5670_SCB_EN (0x1 << 14)
1633 /* Baseback Control (0xcf) */
1634 #define RT5670_BB_MASK (0x1 << 15)
1636 #define RT5670_BB_DIS (0x0 << 15)
1637 #define RT5670_BB_EN (0x1 << 15)
1638 #define RT5670_BB_CT_MASK (0x7 << 12)
1640 #define RT5670_BB_CT_A (0x0 << 12)
1641 #define RT5670_BB_CT_B (0x1 << 12)
1642 #define RT5670_BB_CT_C (0x2 << 12)
1643 #define RT5670_BB_CT_D (0x3 << 12)
1644 #define RT5670_M_BB_L_MASK (0x1 << 9)
1646 #define RT5670_M_BB_R_MASK (0x1 << 8)
1648 #define RT5670_M_BB_HPF_L_MASK (0x1 << 7)
1650 #define RT5670_M_BB_HPF_R_MASK (0x1 << 6)
1652 #define RT5670_G_BB_BST_MASK (0x3f)
1653 #define RT5670_G_BB_BST_SFT 0
1655 /* MP3 Plus Control 1 (0xd0) */
1656 #define RT5670_M_MP3_L_MASK (0x1 << 15)
1658 #define RT5670_M_MP3_R_MASK (0x1 << 14)
1660 #define RT5670_M_MP3_MASK (0x1 << 13)
1662 #define RT5670_M_MP3_DIS (0x0 << 13)
1663 #define RT5670_M_MP3_EN (0x1 << 13)
1664 #define RT5670_EG_MP3_MASK (0x1f << 8)
1666 #define RT5670_MP3_HLP_MASK (0x1 << 7)
1668 #define RT5670_MP3_HLP_DIS (0x0 << 7)
1669 #define RT5670_MP3_HLP_EN (0x1 << 7)
1670 #define RT5670_M_MP3_ORG_L_MASK (0x1 << 6)
1672 #define RT5670_M_MP3_ORG_R_MASK (0x1 << 5)
1675 /* MP3 Plus Control 2 (0xd1) */
1676 #define RT5670_MP3_WT_MASK (0x1 << 13)
1678 #define RT5670_MP3_WT_1_4 (0x0 << 13)
1679 #define RT5670_MP3_WT_1_2 (0x1 << 13)
1680 #define RT5670_OG_MP3_MASK (0x1f << 8)
1682 #define RT5670_HG_MP3_MASK (0x3f)
1683 #define RT5670_HG_MP3_SFT 0
1685 /* 3D HP Control 1 (0xd2) */
1686 #define RT5670_3D_CF_MASK (0x1 << 15)
1688 #define RT5670_3D_CF_DIS (0x0 << 15)
1689 #define RT5670_3D_CF_EN (0x1 << 15)
1690 #define RT5670_3D_HP_MASK (0x1 << 14)
1692 #define RT5670_3D_HP_DIS (0x0 << 14)
1693 #define RT5670_3D_HP_EN (0x1 << 14)
1694 #define RT5670_3D_BT_MASK (0x1 << 13)
1696 #define RT5670_3D_BT_DIS (0x0 << 13)
1697 #define RT5670_3D_BT_EN (0x1 << 13)
1698 #define RT5670_3D_1F_MIX_MASK (0x3 << 11)
1700 #define RT5670_3D_HP_M_MASK (0x1 << 10)
1702 #define RT5670_3D_HP_M_SUR (0x0 << 10)
1703 #define RT5670_3D_HP_M_FRO (0x1 << 10)
1704 #define RT5670_M_3D_HRTF_MASK (0x1 << 9)
1706 #define RT5670_M_3D_D2H_MASK (0x1 << 8)
1708 #define RT5670_M_3D_D2R_MASK (0x1 << 7)
1710 #define RT5670_M_3D_REVB_MASK (0x1 << 6)
1713 /* Adjustable high pass filter control 1 (0xd3) */
1714 #define RT5670_2ND_HPF_MASK (0x1 << 15)
1716 #define RT5670_2ND_HPF_DIS (0x0 << 15)
1717 #define RT5670_2ND_HPF_EN (0x1 << 15)
1718 #define RT5670_HPF_CF_L_MASK (0x7 << 12)
1720 #define RT5670_1ST_HPF_MASK (0x1 << 11)
1722 #define RT5670_1ST_HPF_DIS (0x0 << 11)
1723 #define RT5670_1ST_HPF_EN (0x1 << 11)
1724 #define RT5670_HPF_CF_R_MASK (0x7 << 8)
1726 #define RT5670_ZD_T_MASK (0x3 << 6)
1728 #define RT5670_ZD_F_MASK (0x3 << 4)
1730 #define RT5670_ZD_F_IM (0x0 << 4)
1731 #define RT5670_ZD_F_ZC_IM (0x1 << 4)
1732 #define RT5670_ZD_F_ZC_IOD (0x2 << 4)
1733 #define RT5670_ZD_F_UN (0x3 << 4)
1735 /* HP calibration control and Amp detection (0xd6) */
1736 #define RT5670_SI_DAC_MASK (0x1 << 11)
1738 #define RT5670_SI_DAC_AUTO (0x0 << 11)
1739 #define RT5670_SI_DAC_TEST (0x1 << 11)
1740 #define RT5670_DC_CAL_M_MASK (0x1 << 10)
1742 #define RT5670_DC_CAL_M_CAL (0x0 << 10)
1743 #define RT5670_DC_CAL_M_NOR (0x1 << 10)
1744 #define RT5670_DC_CAL_MASK (0x1 << 9)
1746 #define RT5670_DC_CAL_DIS (0x0 << 9)
1747 #define RT5670_DC_CAL_EN (0x1 << 9)
1748 #define RT5670_HPD_RCV_MASK (0x7 << 6)
1750 #define RT5670_HPD_PS_MASK (0x1 << 5)
1752 #define RT5670_HPD_PS_DIS (0x0 << 5)
1753 #define RT5670_HPD_PS_EN (0x1 << 5)
1754 #define RT5670_CAL_M_MASK (0x1 << 4)
1756 #define RT5670_CAL_M_DEP (0x0 << 4)
1757 #define RT5670_CAL_M_CAL (0x1 << 4)
1758 #define RT5670_CAL_MASK (0x1 << 3)
1760 #define RT5670_CAL_DIS (0x0 << 3)
1761 #define RT5670_CAL_EN (0x1 << 3)
1762 #define RT5670_CAL_TEST_MASK (0x1 << 2)
1764 #define RT5670_CAL_TEST_DIS (0x0 << 2)
1765 #define RT5670_CAL_TEST_EN (0x1 << 2)
1766 #define RT5670_CAL_P_MASK (0x3)
1767 #define RT5670_CAL_P_SFT 0
1768 #define RT5670_CAL_P_NONE (0x0)
1769 #define RT5670_CAL_P_CAL (0x1)
1770 #define RT5670_CAL_P_DAC_CAL (0x2)
1772 /* Soft volume and zero cross control 1 (0xd9) */
1773 #define RT5670_SV_MASK (0x1 << 15)
1775 #define RT5670_SV_DIS (0x0 << 15)
1776 #define RT5670_SV_EN (0x1 << 15)
1777 #define RT5670_SPO_SV_MASK (0x1 << 14)
1779 #define RT5670_SPO_SV_DIS (0x0 << 14)
1780 #define RT5670_SPO_SV_EN (0x1 << 14)
1781 #define RT5670_OUT_SV_MASK (0x1 << 13)
1783 #define RT5670_OUT_SV_DIS (0x0 << 13)
1784 #define RT5670_OUT_SV_EN (0x1 << 13)
1785 #define RT5670_HP_SV_MASK (0x1 << 12)
1787 #define RT5670_HP_SV_DIS (0x0 << 12)
1788 #define RT5670_HP_SV_EN (0x1 << 12)
1789 #define RT5670_ZCD_DIG_MASK (0x1 << 11)
1791 #define RT5670_ZCD_DIG_DIS (0x0 << 11)
1792 #define RT5670_ZCD_DIG_EN (0x1 << 11)
1793 #define RT5670_ZCD_MASK (0x1 << 10)
1795 #define RT5670_ZCD_PD (0x0 << 10)
1796 #define RT5670_ZCD_PU (0x1 << 10)
1797 #define RT5670_M_ZCD_MASK (0x3f << 4)
1799 #define RT5670_M_ZCD_RM_L (0x1 << 9)
1800 #define RT5670_M_ZCD_RM_R (0x1 << 8)
1801 #define RT5670_M_ZCD_SM_L (0x1 << 7)
1802 #define RT5670_M_ZCD_SM_R (0x1 << 6)
1803 #define RT5670_M_ZCD_OM_L (0x1 << 5)
1804 #define RT5670_M_ZCD_OM_R (0x1 << 4)
1805 #define RT5670_SV_DLY_MASK (0xf)
1806 #define RT5670_SV_DLY_SFT 0
1808 /* Soft volume and zero cross control 2 (0xda) */
1809 #define RT5670_ZCD_HP_MASK (0x1 << 15)
1811 #define RT5670_ZCD_HP_DIS (0x0 << 15)
1812 #define RT5670_ZCD_HP_EN (0x1 << 15)
1814 /* General Control 3 (0xfc) */
1815 #define RT5670_TDM_DATA_MODE_SEL (0x1 << 11)
1816 #define RT5670_TDM_DATA_MODE_NOR (0x0 << 11)
1817 #define RT5670_TDM_DATA_MODE_50FS (0x1 << 11)
1820 /* 3D Speaker Control (0x63) */
1821 #define RT5670_3D_SPK_MASK (0x1 << 15)
1823 #define RT5670_3D_SPK_DIS (0x0 << 15)
1824 #define RT5670_3D_SPK_EN (0x1 << 15)
1825 #define RT5670_3D_SPK_M_MASK (0x3 << 13)
1827 #define RT5670_3D_SPK_CG_MASK (0x1f << 8)
1829 #define RT5670_3D_SPK_SG_MASK (0x1f)
1830 #define RT5670_3D_SPK_SG_SFT 0
1832 /* Wind Noise Detection Control 1 (0x6c) */
1833 #define RT5670_WND_MASK (0x1 << 15)
1835 #define RT5670_WND_DIS (0x0 << 15)
1836 #define RT5670_WND_EN (0x1 << 15)
1838 /* Wind Noise Detection Control 2 (0x6d) */
1839 #define RT5670_WND_FC_NW_MASK (0x3f << 10)
1841 #define RT5670_WND_FC_WK_MASK (0x3f << 4)
1844 /* Wind Noise Detection Control 3 (0x6e) */
1845 #define RT5670_HPF_FC_MASK (0x3f << 6)
1847 #define RT5670_WND_FC_ST_MASK (0x3f)
1848 #define RT5670_WND_FC_ST_SFT 0
1850 /* Wind Noise Detection Control 4 (0x6f) */
1851 #define RT5670_WND_TH_LO_MASK (0x3ff)
1852 #define RT5670_WND_TH_LO_SFT 0
1854 /* Wind Noise Detection Control 5 (0x70) */
1855 #define RT5670_WND_TH_HI_MASK (0x3ff)
1856 #define RT5670_WND_TH_HI_SFT 0
1858 /* Wind Noise Detection Control 8 (0x73) */
1859 #define RT5670_WND_WIND_MASK (0x1 << 13) /* Read-Only */
1861 #define RT5670_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
1869 /* Dipole Speaker Interface (0x75) */
1870 #define RT5670_DP_ATT_MASK (0x3 << 14)
1872 #define RT5670_DP_SPK_MASK (0x1 << 10)
1874 #define RT5670_DP_SPK_DIS (0x0 << 10)
1875 #define RT5670_DP_SPK_EN (0x1 << 10)
1877 /* EQ Pre Volume Control (0xb3) */
1878 #define RT5670_EQ_PRE_VOL_MASK (0xffff)
1879 #define RT5670_EQ_PRE_VOL_SFT 0
1881 /* EQ Post Volume Control (0xb4) */
1882 #define RT5670_EQ_PST_VOL_MASK (0xffff)
1883 #define RT5670_EQ_PST_VOL_SFT 0
1885 /* Jack Detect Control 3 (0xf8) */
1886 #define RT5670_CMP_MIC_IN_DET_MASK (0x7 << 12)
1887 #define RT5670_JD_CBJ_EN (0x1 << 7)
1888 #define RT5670_JD_CBJ_POL (0x1 << 6)
1889 #define RT5670_JD_TRI_CBJ_SEL_MASK (0x7 << 3)
1891 #define RT5670_JD_CBJ_GPIO_JD1 (0x0 << 3)
1892 #define RT5670_JD_CBJ_JD1_1 (0x1 << 3)
1893 #define RT5670_JD_CBJ_JD1_2 (0x2 << 3)
1894 #define RT5670_JD_CBJ_JD2 (0x3 << 3)
1895 #define RT5670_JD_CBJ_JD3 (0x4 << 3)
1896 #define RT5670_JD_CBJ_GPIO_JD2 (0x5 << 3)
1897 #define RT5670_JD_CBJ_MX0B_12 (0x6 << 3)
1898 #define RT5670_JD_TRI_HPO_SEL_MASK (0x7 << 3)
1899 #define RT5670_JD_TRI_HPO_SEL_SFT (0)
1900 #define RT5670_JD_HPO_GPIO_JD1 (0x0)
1901 #define RT5670_JD_HPO_JD1_1 (0x1)
1902 #define RT5670_JD_HPO_JD1_2 (0x2)
1903 #define RT5670_JD_HPO_JD2 (0x3)
1904 #define RT5670_JD_HPO_JD3 (0x4)
1905 #define RT5670_JD_HPO_GPIO_JD2 (0x5)
1906 #define RT5670_JD_HPO_MX0B_12 (0x6)
1908 /* Digital Misc Control (0xfa) */
1909 #define RT5670_RST_DSP (0x1 << 13)
1910 #define RT5670_IF1_ADC1_IN1_SEL (0x1 << 12)
1912 #define RT5670_IF1_ADC1_IN2_SEL (0x1 << 11)
1914 #define RT5670_IF1_ADC2_IN1_SEL (0x1 << 10)
1916 #define RT5670_MCLK_DET (0x1 << 3)
1918 /* General Control2 (0xfb) */
1919 #define RT5670_RXDC_SRC_MASK (0x1 << 7)
1920 #define RT5670_RXDC_SRC_STO (0x0 << 7)
1921 #define RT5670_RXDC_SRC_MONO (0x1 << 7)
1923 #define RT5670_RXDP2_SEL_MASK (0x1 << 3)
1924 #define RT5670_RXDP2_SEL_IF2 (0x0 << 3)
1925 #define RT5670_RXDP2_SEL_ADC (0x1 << 3)
1974 RT5670_DA_STEREO_FILTER = 0x1,
1975 RT5670_DA_MONO_L_FILTER = (0x1 << 1),
1976 RT5670_DA_MONO_R_FILTER = (0x1 << 2),
1977 RT5670_AD_STEREO_FILTER = (0x1 << 3),
1978 RT5670_AD_MONO_L_FILTER = (0x1 << 4),
1979 RT5670_AD_MONO_R_FILTER = (0x1 << 5),
1980 RT5670_UP_RATE_FILTER = (0x1 << 6),
1981 RT5670_DOWN_RATE_FILTER = (0x1 << 7),
2000 /* 0 = GPIO6; 1 = IN2P; 3 = GPIO7*/
2002 /* 0 = GPIO8; 1 = IN3N; */
2004 /* 0 = GPIO9; 1 = GPIO10; 2 = GPIO5*/