Lines Matching +full:0 +full:x1
16 #define RT5660_RESET 0x00
17 #define RT5660_VENDOR_ID 0xfd
18 #define RT5660_VENDOR_ID1 0xfe
19 #define RT5660_VENDOR_ID2 0xff
21 #define RT5660_SPK_VOL 0x01
22 #define RT5660_LOUT_VOL 0x02
24 #define RT5660_IN1_IN2 0x0d
25 #define RT5660_IN3_IN4 0x0e
27 #define RT5660_DAC1_DIG_VOL 0x19
28 #define RT5660_STO1_ADC_DIG_VOL 0x1c
29 #define RT5660_ADC_BST_VOL1 0x1e
31 #define RT5660_STO1_ADC_MIXER 0x27
32 #define RT5660_AD_DA_MIXER 0x29
33 #define RT5660_STO_DAC_MIXER 0x2a
34 #define RT5660_DIG_INF1_DATA 0x2f
36 #define RT5660_REC_L1_MIXER 0x3b
37 #define RT5660_REC_L2_MIXER 0x3c
38 #define RT5660_REC_R1_MIXER 0x3d
39 #define RT5660_REC_R2_MIXER 0x3e
41 #define RT5660_LOUT_MIXER 0x45
42 #define RT5660_SPK_MIXER 0x46
43 #define RT5660_SPO_MIXER 0x48
44 #define RT5660_SPO_CLSD_RATIO 0x4a
45 #define RT5660_OUT_L_GAIN1 0x4d
46 #define RT5660_OUT_L_GAIN2 0x4e
47 #define RT5660_OUT_L1_MIXER 0x4f
48 #define RT5660_OUT_R_GAIN1 0x50
49 #define RT5660_OUT_R_GAIN2 0x51
50 #define RT5660_OUT_R1_MIXER 0x52
52 #define RT5660_PWR_DIG1 0x61
53 #define RT5660_PWR_DIG2 0x62
54 #define RT5660_PWR_ANLG1 0x63
55 #define RT5660_PWR_ANLG2 0x64
56 #define RT5660_PWR_MIXER 0x65
57 #define RT5660_PWR_VOL 0x66
59 #define RT5660_PRIV_INDEX 0x6a
60 #define RT5660_PRIV_DATA 0x6c
62 #define RT5660_I2S1_SDP 0x70
63 #define RT5660_ADDA_CLK1 0x73
64 #define RT5660_ADDA_CLK2 0x74
65 #define RT5660_DMIC_CTRL1 0x75
67 #define RT5660_GLB_CLK 0x80
68 #define RT5660_PLL_CTRL1 0x81
69 #define RT5660_PLL_CTRL2 0x82
70 #define RT5660_CLSD_AMP_OC_CTRL 0x8c
71 #define RT5660_CLSD_AMP_CTRL 0x8d
72 #define RT5660_LOUT_AMP_CTRL 0x8e
73 #define RT5660_SPK_AMP_SPKVDD 0x92
74 #define RT5660_MICBIAS 0x93
75 #define RT5660_CLSD_OUT_CTRL1 0xa1
76 #define RT5660_CLSD_OUT_CTRL2 0xa2
77 #define RT5660_DIPOLE_MIC_CTRL1 0xa3
78 #define RT5660_DIPOLE_MIC_CTRL2 0xa4
79 #define RT5660_DIPOLE_MIC_CTRL3 0xa5
80 #define RT5660_DIPOLE_MIC_CTRL4 0xa6
81 #define RT5660_DIPOLE_MIC_CTRL5 0xa7
82 #define RT5660_DIPOLE_MIC_CTRL6 0xa8
83 #define RT5660_DIPOLE_MIC_CTRL7 0xa9
84 #define RT5660_DIPOLE_MIC_CTRL8 0xaa
85 #define RT5660_DIPOLE_MIC_CTRL9 0xab
86 #define RT5660_DIPOLE_MIC_CTRL10 0xac
87 #define RT5660_DIPOLE_MIC_CTRL11 0xad
88 #define RT5660_DIPOLE_MIC_CTRL12 0xae
90 #define RT5660_EQ_CTRL1 0xb0
91 #define RT5660_EQ_CTRL2 0xb1
92 #define RT5660_DRC_AGC_CTRL1 0xb3
93 #define RT5660_DRC_AGC_CTRL2 0xb4
94 #define RT5660_DRC_AGC_CTRL3 0xb5
95 #define RT5660_DRC_AGC_CTRL4 0xb6
96 #define RT5660_DRC_AGC_CTRL5 0xb7
97 #define RT5660_JD_CTRL 0xbb
98 #define RT5660_IRQ_CTRL1 0xbd
99 #define RT5660_IRQ_CTRL2 0xbe
100 #define RT5660_INT_IRQ_ST 0xbf
101 #define RT5660_GPIO_CTRL1 0xc0
102 #define RT5660_GPIO_CTRL2 0xc2
103 #define RT5660_WIND_FILTER_CTRL1 0xd3
104 #define RT5660_SV_ZCD1 0xd9
105 #define RT5660_SV_ZCD2 0xda
106 #define RT5660_DRC1_LM_CTRL1 0xe0
107 #define RT5660_DRC1_LM_CTRL2 0xe1
108 #define RT5660_DRC2_LM_CTRL1 0xe2
109 #define RT5660_DRC2_LM_CTRL2 0xe3
110 #define RT5660_MULTI_DRC_CTRL 0xe4
111 #define RT5660_DRC2_CTRL1 0xe5
112 #define RT5660_DRC2_CTRL2 0xe6
113 #define RT5660_DRC2_CTRL3 0xe7
114 #define RT5660_DRC2_CTRL4 0xe8
115 #define RT5660_DRC2_CTRL5 0xe9
116 #define RT5660_ALC_PGA_CTRL1 0xea
117 #define RT5660_ALC_PGA_CTRL2 0xeb
118 #define RT5660_ALC_PGA_CTRL3 0xec
119 #define RT5660_ALC_PGA_CTRL4 0xed
120 #define RT5660_ALC_PGA_CTRL5 0xee
121 #define RT5660_ALC_PGA_CTRL6 0xef
122 #define RT5660_ALC_PGA_CTRL7 0xf0
125 #define RT5660_GEN_CTRL1 0xfa
126 #define RT5660_GEN_CTRL2 0xfb
127 #define RT5660_GEN_CTRL3 0xfc
130 #define RT5660_CHOP_DAC_ADC 0x3d
133 #define RT5660_L_MUTE (0x1 << 15)
135 #define RT5660_VOL_L_MUTE (0x1 << 14)
137 #define RT5660_R_MUTE (0x1 << 7)
139 #define RT5660_VOL_R_MUTE (0x1 << 6)
141 #define RT5660_L_VOL_MASK (0x3f << 8)
143 #define RT5660_R_VOL_MASK (0x3f)
144 #define RT5660_R_VOL_SFT 0
146 /* IN1 and IN2 Control (0x0d) */
147 #define RT5660_IN_DF1 (0x1 << 15)
149 #define RT5660_BST_MASK1 (0x7f << 8)
151 #define RT5660_IN_DF2 (0x1 << 7)
153 #define RT5660_BST_MASK2 (0x7f << 0)
154 #define RT5660_BST_SFT2 0
156 /* IN3 and IN4 Control (0x0e) */
157 #define RT5660_IN_DF3 (0x1 << 15)
159 #define RT5660_BST_MASK3 (0x7f << 8)
161 #define RT5660_IN_DF4 (0x1 << 7)
163 #define RT5660_BST_MASK4 (0x7f << 0)
164 #define RT5660_BST_SFT4 0
166 /* DAC1 Digital Volume (0x19) */
167 #define RT5660_DAC_L1_VOL_MASK (0x7f << 9)
169 #define RT5660_DAC_R1_VOL_MASK (0x7f << 1)
172 /* ADC Digital Volume Control (0x1c) */
173 #define RT5660_ADC_L_VOL_MASK (0x3f << 9)
175 #define RT5660_ADC_R_VOL_MASK (0x3f << 1)
178 /* ADC Boost Volume Control (0x1e) */
179 #define RT5660_STO1_ADC_L_BST_MASK (0x3 << 14)
181 #define RT5660_STO1_ADC_R_BST_MASK (0x3 << 12)
184 /* Stereo ADC Mixer Control (0x27) */
185 #define RT5660_M_ADC_L1 (0x1 << 14)
187 #define RT5660_M_ADC_L2 (0x1 << 13)
189 #define RT5660_M_ADC_R1 (0x1 << 6)
191 #define RT5660_M_ADC_R2 (0x1 << 5)
194 /* ADC Mixer to DAC Mixer Control (0x29) */
195 #define RT5660_M_ADCMIX_L (0x1 << 15)
197 #define RT5660_M_DAC1_L (0x1 << 14)
199 #define RT5660_M_ADCMIX_R (0x1 << 7)
201 #define RT5660_M_DAC1_R (0x1 << 6)
204 /* Stereo DAC Mixer Control (0x2a) */
205 #define RT5660_M_DAC_L1 (0x1 << 14)
207 #define RT5660_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
209 #define RT5660_M_DAC_R1_STO_L (0x1 << 9)
211 #define RT5660_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
213 #define RT5660_M_DAC_R1 (0x1 << 6)
215 #define RT5660_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
217 #define RT5660_M_DAC_L1_STO_R (0x1 << 1)
219 #define RT5660_DAC_L1_STO_R_VOL_MASK (0x1)
220 #define RT5660_DAC_L1_STO_R_VOL_SFT 0
222 /* Digital Interface Data Control (0x2f) */
223 #define RT5660_IF1_DAC_IN_SEL (0x3 << 14)
225 #define RT5660_IF1_ADC_IN_SEL (0x3 << 12)
228 /* REC Left Mixer Control 1 (0x3b) */
229 #define RT5660_G_BST3_RM_L_MASK (0x7 << 4)
231 #define RT5660_G_BST2_RM_L_MASK (0x7 << 1)
234 /* REC Left Mixer Control 2 (0x3c) */
235 #define RT5660_G_BST1_RM_L_MASK (0x7 << 13)
237 #define RT5660_G_OM_L_RM_L_MASK (0x7 << 10)
239 #define RT5660_M_BST3_RM_L (0x1 << 3)
241 #define RT5660_M_BST2_RM_L (0x1 << 2)
243 #define RT5660_M_BST1_RM_L (0x1 << 1)
245 #define RT5660_M_OM_L_RM_L (0x1)
246 #define RT5660_M_OM_L_RM_L_SFT 0
248 /* REC Right Mixer Control 1 (0x3d) */
249 #define RT5660_G_BST3_RM_R_MASK (0x7 << 4)
251 #define RT5660_G_BST2_RM_R_MASK (0x7 << 1)
254 /* REC Right Mixer Control 2 (0x3e) */
255 #define RT5660_G_BST1_RM_R_MASK (0x7 << 13)
257 #define RT5660_G_OM_R_RM_R_MASK (0x7 << 10)
259 #define RT5660_M_BST3_RM_R (0x1 << 3)
261 #define RT5660_M_BST2_RM_R (0x1 << 2)
263 #define RT5660_M_BST1_RM_R (0x1 << 1)
265 #define RT5660_M_OM_R_RM_R (0x1)
266 #define RT5660_M_OM_R_RM_R_SFT 0
268 /* LOUTMIX Control (0x45) */
269 #define RT5660_M_DAC1_LM (0x1 << 14)
271 #define RT5660_M_LOVOL_M (0x1 << 13)
274 /* SPK Mixer Control (0x46) */
275 #define RT5660_G_BST3_SM_MASK (0x3 << 14)
277 #define RT5660_G_BST1_SM_MASK (0x3 << 12)
279 #define RT5660_G_DACl_SM_MASK (0x3 << 10)
281 #define RT5660_G_DACR_SM_MASK (0x3 << 8)
283 #define RT5660_G_OM_L_SM_MASK (0x3 << 6)
285 #define RT5660_M_DACR_SM (0x1 << 5)
287 #define RT5660_M_BST1_SM (0x1 << 4)
289 #define RT5660_M_BST3_SM (0x1 << 3)
291 #define RT5660_M_DACL_SM (0x1 << 2)
293 #define RT5660_M_OM_L_SM (0x1 << 1)
296 /* SPOMIX Control (0x48) */
297 #define RT5660_M_DAC_R_SPM (0x1 << 14)
299 #define RT5660_M_DAC_L_SPM (0x1 << 13)
301 #define RT5660_M_SV_SPM (0x1 << 12)
303 #define RT5660_M_BST1_SPM (0x1 << 11)
306 /* Output Left Mixer Control 1 (0x4d) */
307 #define RT5660_G_BST3_OM_L_MASK (0x7 << 13)
309 #define RT5660_G_BST2_OM_L_MASK (0x7 << 10)
311 #define RT5660_G_BST1_OM_L_MASK (0x7 << 7)
313 #define RT5660_G_RM_L_OM_L_MASK (0x7 << 1)
316 /* Output Left Mixer Control 2 (0x4e) */
317 #define RT5660_G_DAC_R1_OM_L_MASK (0x7 << 10)
319 #define RT5660_G_DAC_L1_OM_L_MASK (0x7 << 7)
322 /* Output Left Mixer Control 3 (0x4f) */
323 #define RT5660_M_BST3_OM_L (0x1 << 5)
325 #define RT5660_M_BST2_OM_L (0x1 << 4)
327 #define RT5660_M_BST1_OM_L (0x1 << 3)
329 #define RT5660_M_RM_L_OM_L (0x1 << 2)
331 #define RT5660_M_DAC_R_OM_L (0x1 << 1)
333 #define RT5660_M_DAC_L_OM_L (0x1)
334 #define RT5660_M_DAC_L_OM_L_SFT 0
336 /* Output Right Mixer Control 1 (0x50) */
337 #define RT5660_G_BST2_OM_R_MASK (0x7 << 10)
339 #define RT5660_G_BST1_OM_R_MASK (0x7 << 7)
341 #define RT5660_G_RM_R_OM_R_MASK (0x7 << 1)
344 /* Output Right Mixer Control 2 (0x51) */
345 #define RT5660_G_DAC_L_OM_R_MASK (0x7 << 10)
347 #define RT5660_G_DAC_R_OM_R_MASK (0x7 << 7)
350 /* Output Right Mixer Control 3 (0x52) */
351 #define RT5660_M_BST2_OM_R (0x1 << 4)
353 #define RT5660_M_BST1_OM_R (0x1 << 3)
355 #define RT5660_M_RM_R_OM_R (0x1 << 2)
357 #define RT5660_M_DAC_L_OM_R (0x1 << 1)
359 #define RT5660_M_DAC_R_OM_R (0x1)
360 #define RT5660_M_DAC_R_OM_R_SFT 0
362 /* Power Management for Digital 1 (0x61) */
363 #define RT5660_PWR_I2S1 (0x1 << 15)
365 #define RT5660_PWR_DAC_L1 (0x1 << 12)
367 #define RT5660_PWR_DAC_R1 (0x1 << 11)
369 #define RT5660_PWR_ADC_L (0x1 << 2)
371 #define RT5660_PWR_ADC_R (0x1 << 1)
373 #define RT5660_PWR_CLS_D (0x1)
374 #define RT5660_PWR_CLS_D_BIT 0
376 /* Power Management for Digital 2 (0x62) */
377 #define RT5660_PWR_ADC_S1F (0x1 << 15)
379 #define RT5660_PWR_DAC_S1F (0x1 << 11)
382 /* Power Management for Analog 1 (0x63) */
383 #define RT5660_PWR_VREF1 (0x1 << 15)
385 #define RT5660_PWR_FV1 (0x1 << 14)
387 #define RT5660_PWR_MB (0x1 << 13)
389 #define RT5660_PWR_BG (0x1 << 11)
391 #define RT5660_PWR_HP_L (0x1 << 7)
393 #define RT5660_PWR_HP_R (0x1 << 6)
395 #define RT5660_PWR_HA (0x1 << 5)
397 #define RT5660_PWR_VREF2 (0x1 << 4)
399 #define RT5660_PWR_FV2 (0x1 << 3)
401 #define RT5660_PWR_LDO2 (0x1 << 2)
404 /* Power Management for Analog 2 (0x64) */
405 #define RT5660_PWR_BST1 (0x1 << 15)
407 #define RT5660_PWR_BST2 (0x1 << 14)
409 #define RT5660_PWR_BST3 (0x1 << 13)
411 #define RT5660_PWR_MB1 (0x1 << 11)
413 #define RT5660_PWR_MB2 (0x1 << 10)
415 #define RT5660_PWR_PLL (0x1 << 9)
418 /* Power Management for Mixer (0x65) */
419 #define RT5660_PWR_OM_L (0x1 << 15)
421 #define RT5660_PWR_OM_R (0x1 << 14)
423 #define RT5660_PWR_SM (0x1 << 13)
425 #define RT5660_PWR_RM_L (0x1 << 11)
427 #define RT5660_PWR_RM_R (0x1 << 10)
430 /* Power Management for Volume (0x66) */
431 #define RT5660_PWR_SV (0x1 << 15)
433 #define RT5660_PWR_LV_L (0x1 << 11)
435 #define RT5660_PWR_LV_R (0x1 << 10)
438 /* I2S1 Audio Serial Data Port Control (0x70) */
439 #define RT5660_I2S_MS_MASK (0x1 << 15)
441 #define RT5660_I2S_MS_M (0x0 << 15)
442 #define RT5660_I2S_MS_S (0x1 << 15)
443 #define RT5660_I2S_O_CP_MASK (0x3 << 10)
445 #define RT5660_I2S_O_CP_OFF (0x0 << 10)
446 #define RT5660_I2S_O_CP_U_LAW (0x1 << 10)
447 #define RT5660_I2S_O_CP_A_LAW (0x2 << 10)
448 #define RT5660_I2S_I_CP_MASK (0x3 << 8)
450 #define RT5660_I2S_I_CP_OFF (0x0 << 8)
451 #define RT5660_I2S_I_CP_U_LAW (0x1 << 8)
452 #define RT5660_I2S_I_CP_A_LAW (0x2 << 8)
453 #define RT5660_I2S_BP_MASK (0x1 << 7)
455 #define RT5660_I2S_BP_NOR (0x0 << 7)
456 #define RT5660_I2S_BP_INV (0x1 << 7)
457 #define RT5660_I2S_DL_MASK (0x3 << 2)
459 #define RT5660_I2S_DL_16 (0x0 << 2)
460 #define RT5660_I2S_DL_20 (0x1 << 2)
461 #define RT5660_I2S_DL_24 (0x2 << 2)
462 #define RT5660_I2S_DL_8 (0x3 << 2)
463 #define RT5660_I2S_DF_MASK (0x3)
464 #define RT5660_I2S_DF_SFT 0
465 #define RT5660_I2S_DF_I2S (0x0)
466 #define RT5660_I2S_DF_LEFT (0x1)
467 #define RT5660_I2S_DF_PCM_A (0x2)
468 #define RT5660_I2S_DF_PCM_B (0x3)
470 /* ADC/DAC Clock Control 1 (0x73) */
471 #define RT5660_I2S_BCLK_MS1_MASK (0x1 << 15)
473 #define RT5660_I2S_BCLK_MS1_32 (0x0 << 15)
474 #define RT5660_I2S_BCLK_MS1_64 (0x1 << 15)
475 #define RT5660_I2S_PD1_MASK (0x7 << 12)
477 #define RT5660_I2S_PD1_1 (0x0 << 12)
478 #define RT5660_I2S_PD1_2 (0x1 << 12)
479 #define RT5660_I2S_PD1_3 (0x2 << 12)
480 #define RT5660_I2S_PD1_4 (0x3 << 12)
481 #define RT5660_I2S_PD1_6 (0x4 << 12)
482 #define RT5660_I2S_PD1_8 (0x5 << 12)
483 #define RT5660_I2S_PD1_12 (0x6 << 12)
484 #define RT5660_I2S_PD1_16 (0x7 << 12)
485 #define RT5660_DAC_OSR_MASK (0x3 << 2)
487 #define RT5660_DAC_OSR_128 (0x0 << 2)
488 #define RT5660_DAC_OSR_64 (0x1 << 2)
489 #define RT5660_DAC_OSR_32 (0x2 << 2)
490 #define RT5660_DAC_OSR_16 (0x3 << 2)
491 #define RT5660_ADC_OSR_MASK (0x3)
492 #define RT5660_ADC_OSR_SFT 0
493 #define RT5660_ADC_OSR_128 (0x0)
494 #define RT5660_ADC_OSR_64 (0x1)
495 #define RT5660_ADC_OSR_32 (0x2)
496 #define RT5660_ADC_OSR_16 (0x3)
498 /* ADC/DAC Clock Control 2 (0x74) */
499 #define RT5660_RESET_ADF (0x1 << 13)
501 #define RT5660_RESET_DAF (0x1 << 12)
503 #define RT5660_DAHPF_EN (0x1 << 11)
505 #define RT5660_ADHPF_EN (0x1 << 10)
508 /* Digital Microphone Control (0x75) */
509 #define RT5660_DMIC_1_EN_MASK (0x1 << 15)
511 #define RT5660_DMIC_1_DIS (0x0 << 15)
512 #define RT5660_DMIC_1_EN (0x1 << 15)
513 #define RT5660_DMIC_1L_LH_MASK (0x1 << 13)
515 #define RT5660_DMIC_1L_LH_RISING (0x0 << 13)
516 #define RT5660_DMIC_1L_LH_FALLING (0x1 << 13)
517 #define RT5660_DMIC_1R_LH_MASK (0x1 << 12)
519 #define RT5660_DMIC_1R_LH_RISING (0x0 << 12)
520 #define RT5660_DMIC_1R_LH_FALLING (0x1 << 12)
521 #define RT5660_SEL_DMIC_DATA_MASK (0x1 << 11)
523 #define RT5660_SEL_DMIC_DATA_GPIO2 (0x0 << 11)
524 #define RT5660_SEL_DMIC_DATA_IN1P (0x1 << 11)
525 #define RT5660_DMIC_CLK_MASK (0x7 << 5)
528 /* Global Clock Control (0x80) */
529 #define RT5660_SCLK_SRC_MASK (0x3 << 14)
531 #define RT5660_SCLK_SRC_MCLK (0x0 << 14)
532 #define RT5660_SCLK_SRC_PLL1 (0x1 << 14)
533 #define RT5660_SCLK_SRC_RCCLK (0x2 << 14)
534 #define RT5660_PLL1_SRC_MASK (0x3 << 12)
536 #define RT5660_PLL1_SRC_MCLK (0x0 << 12)
537 #define RT5660_PLL1_SRC_BCLK1 (0x1 << 12)
538 #define RT5660_PLL1_SRC_RCCLK (0x2 << 12)
539 #define RT5660_PLL1_PD_MASK (0x1 << 3)
541 #define RT5660_PLL1_PD_1 (0x0 << 3)
542 #define RT5660_PLL1_PD_2 (0x1 << 3)
546 /* PLL M/N/K Code Control 1 (0x81) */
547 #define RT5660_PLL_N_MAX 0x1ff
550 #define RT5660_PLL_K_MAX 0x1f
552 #define RT5660_PLL_K_SFT 0
554 /* PLL M/N/K Code Control 2 (0x82) */
555 #define RT5660_PLL_M_MAX 0xf
558 #define RT5660_PLL_M_BP (0x1 << 11)
561 /* Class D Over Current Control (0x8c) */
562 #define RT5660_CLSD_OC_MASK (0x1 << 9)
564 #define RT5660_CLSD_OC_PU (0x0 << 9)
565 #define RT5660_CLSD_OC_PD (0x1 << 9)
566 #define RT5660_AUTO_PD_MASK (0x1 << 8)
568 #define RT5660_AUTO_PD_DIS (0x0 << 8)
569 #define RT5660_AUTO_PD_EN (0x1 << 8)
570 #define RT5660_CLSD_OC_TH_MASK (0x3f)
571 #define RT5660_CLSD_OC_TH_SFT 0
573 /* Class D Output Control (0x8d) */
574 #define RT5660_CLSD_RATIO_MASK (0xf << 12)
577 /* Lout Amp Control 1 (0x8e) */
578 #define RT5660_LOUT_CO_MASK (0x1 << 4)
580 #define RT5660_LOUT_CO_DIS (0x0 << 4)
581 #define RT5660_LOUT_CO_EN (0x1 << 4)
582 #define RT5660_LOUT_CB_MASK (0x1)
583 #define RT5660_LOUT_CB_SFT 0
584 #define RT5660_LOUT_CB_PD (0x0)
585 #define RT5660_LOUT_CB_PU (0x1)
587 /* SPKVDD detection control (0x92) */
588 #define RT5660_SPKVDD_DET_MASK (0x1 << 15)
590 #define RT5660_SPKVDD_DET_DIS (0x0 << 15)
591 #define RT5660_SPKVDD_DET_EN (0x1 << 15)
592 #define RT5660_SPK_AG_MASK (0x1 << 14)
594 #define RT5660_SPK_AG_DIS (0x0 << 14)
595 #define RT5660_SPK_AG_EN (0x1 << 14)
597 /* Micbias Control (0x93) */
598 #define RT5660_MIC1_BS_MASK (0x1 << 15)
600 #define RT5660_MIC1_BS_9AV (0x0 << 15)
601 #define RT5660_MIC1_BS_75AV (0x1 << 15)
602 #define RT5660_MIC2_BS_MASK (0x1 << 14)
604 #define RT5660_MIC2_BS_9AV (0x0 << 14)
605 #define RT5660_MIC2_BS_75AV (0x1 << 14)
606 #define RT5660_MIC1_OVCD_MASK (0x1 << 11)
608 #define RT5660_MIC1_OVCD_DIS (0x0 << 11)
609 #define RT5660_MIC1_OVCD_EN (0x1 << 11)
610 #define RT5660_MIC1_OVTH_MASK (0x3 << 9)
612 #define RT5660_MIC1_OVTH_600UA (0x0 << 9)
613 #define RT5660_MIC1_OVTH_1500UA (0x1 << 9)
614 #define RT5660_MIC1_OVTH_2000UA (0x2 << 9)
615 #define RT5660_MIC2_OVCD_MASK (0x1 << 8)
617 #define RT5660_MIC2_OVCD_DIS (0x0 << 8)
618 #define RT5660_MIC2_OVCD_EN (0x1 << 8)
619 #define RT5660_MIC2_OVTH_MASK (0x3 << 6)
621 #define RT5660_MIC2_OVTH_600UA (0x0 << 6)
622 #define RT5660_MIC2_OVTH_1500UA (0x1 << 6)
623 #define RT5660_MIC2_OVTH_2000UA (0x2 << 6)
624 #define RT5660_PWR_CLK25M_MASK (0x1 << 4)
626 #define RT5660_PWR_CLK25M_PD (0x0 << 4)
627 #define RT5660_PWR_CLK25M_PU (0x1 << 4)
629 /* EQ Control 1 (0xb0) */
630 #define RT5660_EQ_SRC_MASK (0x1 << 15)
632 #define RT5660_EQ_SRC_DAC (0x0 << 15)
633 #define RT5660_EQ_SRC_ADC (0x1 << 15)
634 #define RT5660_EQ_UPD (0x1 << 14)
637 /* Jack Detect Control (0xbb) */
638 #define RT5660_JD_MASK (0x3 << 14)
640 #define RT5660_JD_DIS (0x0 << 14)
641 #define RT5660_JD_GPIO1 (0x1 << 14)
642 #define RT5660_JD_GPIO2 (0x2 << 14)
643 #define RT5660_JD_LOUT_MASK (0x1 << 11)
645 #define RT5660_JD_LOUT_DIS (0x0 << 11)
646 #define RT5660_JD_LOUT_EN (0x1 << 11)
647 #define RT5660_JD_LOUT_TRG_MASK (0x1 << 10)
649 #define RT5660_JD_LOUT_TRG_LO (0x0 << 10)
650 #define RT5660_JD_LOUT_TRG_HI (0x1 << 10)
651 #define RT5660_JD_SPO_MASK (0x1 << 9)
653 #define RT5660_JD_SPO_DIS (0x0 << 9)
654 #define RT5660_JD_SPO_EN (0x1 << 9)
655 #define RT5660_JD_SPO_TRG_MASK (0x1 << 8)
657 #define RT5660_JD_SPO_TRG_LO (0x0 << 8)
658 #define RT5660_JD_SPO_TRG_HI (0x1 << 8)
660 /* IRQ Control 1 (0xbd) */
661 #define RT5660_IRQ_JD_MASK (0x1 << 15)
663 #define RT5660_IRQ_JD_BP (0x0 << 15)
664 #define RT5660_IRQ_JD_NOR (0x1 << 15)
665 #define RT5660_IRQ_OT_MASK (0x1 << 14)
667 #define RT5660_IRQ_OT_BP (0x0 << 14)
668 #define RT5660_IRQ_OT_NOR (0x1 << 14)
669 #define RT5660_JD_STKY_MASK (0x1 << 13)
671 #define RT5660_JD_STKY_DIS (0x0 << 13)
672 #define RT5660_JD_STKY_EN (0x1 << 13)
673 #define RT5660_OT_STKY_MASK (0x1 << 12)
675 #define RT5660_OT_STKY_DIS (0x0 << 12)
676 #define RT5660_OT_STKY_EN (0x1 << 12)
677 #define RT5660_JD_P_MASK (0x1 << 11)
679 #define RT5660_JD_P_NOR (0x0 << 11)
680 #define RT5660_JD_P_INV (0x1 << 11)
681 #define RT5660_OT_P_MASK (0x1 << 10)
683 #define RT5660_OT_P_NOR (0x0 << 10)
684 #define RT5660_OT_P_INV (0x1 << 10)
686 /* IRQ Control 2 (0xbe) */
687 #define RT5660_IRQ_MB1_OC_MASK (0x1 << 15)
689 #define RT5660_IRQ_MB1_OC_BP (0x0 << 15)
690 #define RT5660_IRQ_MB1_OC_NOR (0x1 << 15)
691 #define RT5660_IRQ_MB2_OC_MASK (0x1 << 14)
693 #define RT5660_IRQ_MB2_OC_BP (0x0 << 14)
694 #define RT5660_IRQ_MB2_OC_NOR (0x1 << 14)
695 #define RT5660_MB1_OC_STKY_MASK (0x1 << 11)
697 #define RT5660_MB1_OC_STKY_DIS (0x0 << 11)
698 #define RT5660_MB1_OC_STKY_EN (0x1 << 11)
699 #define RT5660_MB2_OC_STKY_MASK (0x1 << 10)
701 #define RT5660_MB2_OC_STKY_DIS (0x0 << 10)
702 #define RT5660_MB2_OC_STKY_EN (0x1 << 10)
703 #define RT5660_MB1_OC_P_MASK (0x1 << 7)
705 #define RT5660_MB1_OC_P_NOR (0x0 << 7)
706 #define RT5660_MB1_OC_P_INV (0x1 << 7)
707 #define RT5660_MB2_OC_P_MASK (0x1 << 6)
709 #define RT5660_MB2_OC_P_NOR (0x0 << 6)
710 #define RT5660_MB2_OC_P_INV (0x1 << 6)
711 #define RT5660_MB1_OC_CLR (0x1 << 3)
713 #define RT5660_MB2_OC_CLR (0x1 << 2)
716 /* GPIO Control 1 (0xc0) */
717 #define RT5660_GP2_PIN_MASK (0x1 << 14)
719 #define RT5660_GP2_PIN_GPIO2 (0x0 << 14)
720 #define RT5660_GP2_PIN_DMIC1_SDA (0x1 << 14)
721 #define RT5660_GP1_PIN_MASK (0x3 << 12)
723 #define RT5660_GP1_PIN_GPIO1 (0x0 << 12)
724 #define RT5660_GP1_PIN_DMIC1_SCL (0x1 << 12)
725 #define RT5660_GP1_PIN_IRQ (0x2 << 12)
726 #define RT5660_GPIO_M_MASK (0x1 << 9)
728 #define RT5660_GPIO_M_FLT (0x0 << 9)
729 #define RT5660_GPIO_M_PH (0x1 << 9)
731 /* GPIO Control 3 (0xc2) */
732 #define RT5660_GP2_PF_MASK (0x1 << 5)
734 #define RT5660_GP2_PF_IN (0x0 << 5)
735 #define RT5660_GP2_PF_OUT (0x1 << 5)
736 #define RT5660_GP2_OUT_MASK (0x1 << 4)
738 #define RT5660_GP2_OUT_LO (0x0 << 4)
739 #define RT5660_GP2_OUT_HI (0x1 << 4)
740 #define RT5660_GP2_P_MASK (0x1 << 3)
742 #define RT5660_GP2_P_NOR (0x0 << 3)
743 #define RT5660_GP2_P_INV (0x1 << 3)
744 #define RT5660_GP1_PF_MASK (0x1 << 2)
746 #define RT5660_GP1_PF_IN (0x0 << 2)
747 #define RT5660_GP1_PF_OUT (0x1 << 2)
748 #define RT5660_GP1_OUT_MASK (0x1 << 1)
750 #define RT5660_GP1_OUT_LO (0x0 << 1)
751 #define RT5660_GP1_OUT_HI (0x1 << 1)
752 #define RT5660_GP1_P_MASK (0x1)
753 #define RT5660_GP1_P_SFT 0
754 #define RT5660_GP1_P_NOR (0x0)
755 #define RT5660_GP1_P_INV (0x1)
757 /* Soft volume and zero cross control 1 (0xd9) */
758 #define RT5660_SV_MASK (0x1 << 15)
760 #define RT5660_SV_DIS (0x0 << 15)
761 #define RT5660_SV_EN (0x1 << 15)
762 #define RT5660_SPO_SV_MASK (0x1 << 14)
764 #define RT5660_SPO_SV_DIS (0x0 << 14)
765 #define RT5660_SPO_SV_EN (0x1 << 14)
766 #define RT5660_OUT_SV_MASK (0x1 << 12)
768 #define RT5660_OUT_SV_DIS (0x0 << 12)
769 #define RT5660_OUT_SV_EN (0x1 << 12)
770 #define RT5660_ZCD_DIG_MASK (0x1 << 11)
772 #define RT5660_ZCD_DIG_DIS (0x0 << 11)
773 #define RT5660_ZCD_DIG_EN (0x1 << 11)
774 #define RT5660_ZCD_MASK (0x1 << 10)
776 #define RT5660_ZCD_PD (0x0 << 10)
777 #define RT5660_ZCD_PU (0x1 << 10)
778 #define RT5660_SV_DLY_MASK (0xf)
779 #define RT5660_SV_DLY_SFT 0
781 /* Soft volume and zero cross control 2 (0xda) */
782 #define RT5660_ZCD_SPO_MASK (0x1 << 15)
784 #define RT5660_ZCD_SPO_DIS (0x0 << 15)
785 #define RT5660_ZCD_SPO_EN (0x1 << 15)
786 #define RT5660_ZCD_OMR_MASK (0x1 << 8)
788 #define RT5660_ZCD_OMR_DIS (0x0 << 8)
789 #define RT5660_ZCD_OMR_EN (0x1 << 8)
790 #define RT5660_ZCD_OML_MASK (0x1 << 7)
792 #define RT5660_ZCD_OML_DIS (0x0 << 7)
793 #define RT5660_ZCD_OML_EN (0x1 << 7)
794 #define RT5660_ZCD_SPM_MASK (0x1 << 6)
796 #define RT5660_ZCD_SPM_DIS (0x0 << 6)
797 #define RT5660_ZCD_SPM_EN (0x1 << 6)
798 #define RT5660_ZCD_RMR_MASK (0x1 << 5)
800 #define RT5660_ZCD_RMR_DIS (0x0 << 5)
801 #define RT5660_ZCD_RMR_EN (0x1 << 5)
802 #define RT5660_ZCD_RML_MASK (0x1 << 4)
804 #define RT5660_ZCD_RML_DIS (0x0 << 4)
805 #define RT5660_ZCD_RML_EN (0x1 << 4)
807 /* General Control 1 (0xfa) */
808 #define RT5660_PWR_VREF_HP (0x1 << 11)
810 #define RT5660_AUTO_DIS_AMP (0x1 << 6)
811 #define RT5660_MCLK_DET (0x1 << 5)
812 #define RT5660_POW_CLKDET (0x1 << 1)
813 #define RT5660_DIG_GATE_CTRL (0x1)
814 #define RT5660_DIG_GATE_CTRL_SFT 0
817 #define RT5660_SCLK_S_MCLK 0
822 #define RT5660_PLL1_S_MCLK 0