Lines Matching +full:adc +full:- +full:channel +full:- +full:clk +full:- +full:src
1 // SPDX-License-Identifier: GPL-2.0-only
3 * rt5659.c -- RT5659/RT5658 ALSA SoC audio codec driver
9 #include <linux/clk.h>
26 #include <sound/soc-dapm.h>
1137 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2325, 75, 0);
1138 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
1139 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
1140 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
1141 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
1143 static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
1175 SOC_DAPM_ENUM("IF1 01 ADC Swap Source", rt5659_if1_01_adc_enum);
1190 SOC_DAPM_ENUM("IF2 ADC Swap Source", rt5659_if2_adc_enum);
1196 SOC_DAPM_ENUM("IF3 ADC Swap Source", rt5659_if3_adc_enum);
1250 * rt5659_headset_detect - Detect headset.
1297 rt5659->jack_type = SND_JACK_HEADSET; in rt5659_headset_detect()
1302 rt5659->jack_type = SND_JACK_HEADPHONE; in rt5659_headset_detect()
1310 if (rt5659->jack_type == SND_JACK_HEADSET) in rt5659_headset_detect()
1312 rt5659->jack_type = 0; in rt5659_headset_detect()
1315 dev_dbg(component->dev, "jack_type = %d\n", rt5659->jack_type); in rt5659_headset_detect()
1316 return rt5659->jack_type; in rt5659_headset_detect()
1335 &rt5659->jack_detect_work, msecs_to_jiffies(250)); in rt5659_irq()
1345 rt5659->hs_jack = hs_jack; in rt5659_set_jack_detect()
1359 if (!rt5659->component) in rt5659_jack_detect_work()
1362 val = snd_soc_component_read(rt5659->component, RT5659_INT_ST_1) & 0x0080; in rt5659_jack_detect_work()
1365 if (rt5659->jack_type == 0) { in rt5659_jack_detect_work()
1367 report = rt5659_headset_detect(rt5659->component, 1); in rt5659_jack_detect_work()
1371 btn_type = rt5659_button_detect(rt5659->component); in rt5659_jack_detect_work()
1404 dev_err(rt5659->component->dev, in rt5659_jack_detect_work()
1412 report = rt5659->jack_type; in rt5659_jack_detect_work()
1416 report = rt5659_headset_detect(rt5659->component, 0); in rt5659_jack_detect_work()
1419 snd_soc_jack_report(rt5659->hs_jack, report, SND_JACK_HEADSET | in rt5659_jack_detect_work()
1431 if (!rt5659->hs_jack) in rt5659_jack_detect_intel_hd_header()
1435 regmap_read(rt5659->regmap, RT5659_GPIO_STA, &value); in rt5659_jack_detect_intel_hd_header()
1438 if (hp_flag != rt5659->hda_hp_plugged) { in rt5659_jack_detect_intel_hd_header()
1439 rt5659->hda_hp_plugged = hp_flag; in rt5659_jack_detect_intel_hd_header()
1442 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_1, in rt5659_jack_detect_intel_hd_header()
1444 rt5659->jack_type |= SND_JACK_HEADPHONE; in rt5659_jack_detect_intel_hd_header()
1446 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_1, in rt5659_jack_detect_intel_hd_header()
1448 rt5659->jack_type = rt5659->jack_type & in rt5659_jack_detect_intel_hd_header()
1452 snd_soc_jack_report(rt5659->hs_jack, rt5659->jack_type, in rt5659_jack_detect_intel_hd_header()
1457 regmap_read(rt5659->regmap, RT5659_4BTN_IL_CMD_1, &value); in rt5659_jack_detect_intel_hd_header()
1458 regmap_write(rt5659->regmap, RT5659_4BTN_IL_CMD_1, value); in rt5659_jack_detect_intel_hd_header()
1461 if (mic_flag != rt5659->hda_mic_plugged) { in rt5659_jack_detect_intel_hd_header()
1462 rt5659->hda_mic_plugged = mic_flag; in rt5659_jack_detect_intel_hd_header()
1464 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2, in rt5659_jack_detect_intel_hd_header()
1466 rt5659->jack_type |= SND_JACK_MICROPHONE; in rt5659_jack_detect_intel_hd_header()
1468 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2, in rt5659_jack_detect_intel_hd_header()
1470 rt5659->jack_type = rt5659->jack_type in rt5659_jack_detect_intel_hd_header()
1474 snd_soc_jack_report(rt5659->hs_jack, rt5659->jack_type, in rt5659_jack_detect_intel_hd_header()
1522 /* ADC Digital Volume Control */
1523 SOC_DOUBLE("STO1 ADC Capture Switch", RT5659_STO1_ADC_DIG_VOL,
1525 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5659_STO1_ADC_DIG_VOL,
1527 SOC_DOUBLE("Mono ADC Capture Switch", RT5659_MONO_ADC_DIG_VOL,
1529 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5659_MONO_ADC_DIG_VOL,
1531 SOC_DOUBLE("STO2 ADC Capture Switch", RT5659_STO2_ADC_DIG_VOL,
1533 SOC_DOUBLE_TLV("STO2 ADC Capture Volume", RT5659_STO2_ADC_DIG_VOL,
1536 /* ADC Boost Volume Control */
1537 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5659_STO1_BOOST,
1541 SOC_DOUBLE_TLV("Mono ADC Boost Gain Volume", RT5659_MONO_BOOST,
1545 SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5659_STO2_BOOST,
1556 * set_dmic_clk - Set parameter of dmic.
1568 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in set_dmic_clk()
1572 pd = rl6231_get_pre_div(rt5659->regmap, in set_dmic_clk()
1574 idx = rl6231_calc_dmic_clk(rt5659->sysclk / pd); in set_dmic_clk()
1577 dev_err(component->dev, "Failed to set DMIC clock\n"); in set_dmic_clk()
1588 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in set_adc1_clk()
1614 snd_soc_dapm_to_component(w->dapm); in set_adc2_clk()
1639 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5659_charge_pump_event()
1660 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in is_sys_clk_from_pll()
1674 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in is_using_asrc()
1676 switch (w->shift) { in is_using_asrc()
1750 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5659_AD_DA_MIXER,
1757 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5659_AD_DA_MIXER,
1969 /*MX-1B [6:4], MX-1B [2:0]*/
1971 "IF1 DAC2", "IF2 DAC", "IF3 DAC", "Mono ADC MIX"
1990 /* MX-26 [13] */
1992 "DAC MIX", "ADC"
2002 /* STO1 ADC Source */
2003 /* MX-26 [12] */
2013 SOC_DAPM_ENUM("Stereo1 ADC Source", rt5659_sto1_adc_enum);
2016 /* MX-26 [11] */
2029 /* MX-26 [8] */
2042 /* MONO ADC L2 Source */
2043 /* MX-27 [12] */
2053 SOC_DAPM_ENUM("Mono ADC L2 Source", rt5659_mono_adc_l2_enum);
2056 /* MONO ADC L1 Source */
2057 /* MX-27 [11] */
2059 "Mono DAC MIXL", "ADC"
2067 SOC_DAPM_ENUM("Mono ADC L1 Source", rt5659_mono_adc_l1_enum);
2069 /* MONO ADC L Source, MONO ADC R Source*/
2070 /* MX-27 [10:9], MX-27 [2:1] */
2080 SOC_DAPM_ENUM("Mono ADC L Source", rt5659_mono_adc_l_enum);
2087 SOC_DAPM_ENUM("Mono ADC R Source", rt5659_mono_adcr_enum);
2090 /* MX-27 [8] */
2102 /* MONO ADC R2 Source */
2103 /* MX-27 [4] */
2113 SOC_DAPM_ENUM("Mono ADC R2 Source", rt5659_mono_adc_r2_enum);
2115 /* MONO ADC R1 Source */
2116 /* MX-27 [3] */
2118 "Mono DAC MIXR", "ADC"
2126 SOC_DAPM_ENUM("Mono ADC R1 Source", rt5659_mono_adc_r1_enum);
2129 /* MX-27 [0] */
2143 /* MX-29 [11:10], MX-29 [9:8]*/
2163 /* MX-2C [6], MX-2C [4]*/
2183 /* MX-2D [3], MX-2D [2]*/
2203 /* MX-2D [1], MX-2D [0]*/
2222 /* Interface2 ADC Data Input*/
2223 /* MX-2F [13:12] */
2233 SOC_DAPM_ENUM("IF2 ADC IN Source", rt5659_if2_adc_in_enum);
2235 /* Interface3 ADC Data Input*/
2236 /* MX-2F [1:0] */
2246 SOC_DAPM_ENUM("IF3 ADC IN Source", rt5659_if3_adc_in_enum);
2249 /* MX-31 [15] [13] */
2269 /* MX-36 [1:0] */
2282 /* MX-78[4:0] */
2347 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5659_spk_event()
2379 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5659_mono_event()
2401 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5659_hp_event()
2459 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5659_ASRC_1,
2461 SND_SOC_DAPM_SUPPLY_S("ADC Mono L ASRC", 1, RT5659_ASRC_1,
2463 SND_SOC_DAPM_SUPPLY_S("ADC Mono R ASRC", 1, RT5659_ASRC_1,
2492 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2553 /* ADC Mux */
2558 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2560 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2562 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2564 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2566 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2568 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2570 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2572 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2574 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2576 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2582 SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0,
2584 SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0,
2586 /* ADC Mixer */
2587 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5659_PWR_DIG_2,
2589 SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5659_PWR_DIG_2,
2591 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", SND_SOC_NOPM,
2594 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", SND_SOC_NOPM,
2597 SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5659_PWR_DIG_2,
2599 SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5659_MONO_ADC_DIG_VOL,
2602 SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5659_PWR_DIG_2,
2604 SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5659_MONO_ADC_DIG_VOL,
2608 /* ADC PGA */
2616 SND_SOC_DAPM_PGA("Stereo2 ADC LR", SND_SOC_NOPM, 0, 0, NULL, 0),
2618 SND_SOC_DAPM_PGA("Stereo1 ADC Volume L", RT5659_STO1_ADC_DIG_VOL,
2620 SND_SOC_DAPM_PGA("Stereo1 ADC Volume R", RT5659_STO1_ADC_DIG_VOL,
2632 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2633 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2634 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2640 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2648 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2649 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2650 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2657 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM, 0, 0,
2659 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2661 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2663 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2665 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2667 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2671 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2675 SND_SOC_DAPM_MUX("IF3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2693 /* DAC channel Mux */
2822 SND_SOC_DAPM_SUPPLY("SYS CLK DET", RT5659_CLK_DET, 3, 0, NULL, 0),
2840 { "ADC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll },
2841 { "ADC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll },
2842 { "ADC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll },
2843 { "ADC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll },
2849 { "ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc },
2850 { "ADC Mono Left Filter", NULL, "ADC Mono L ASRC", is_using_asrc },
2851 { "ADC Mono Right Filter", NULL, "ADC Mono R ASRC", is_using_asrc },
2856 { "SYS CLK DET", NULL, "CLKDET" },
2925 { "DMIC L1", NULL, "DMIC CLK" },
2927 { "DMIC R1", NULL, "DMIC CLK" },
2929 { "DMIC L2", NULL, "DMIC CLK" },
2931 { "DMIC R2", NULL, "DMIC CLK" },
2946 { "Stereo1 ADC L Mux", "ADC1", "ADC1 L" },
2947 { "Stereo1 ADC L Mux", "ADC2", "ADC2 L" },
2948 { "Stereo1 ADC R Mux", "ADC1", "ADC1 R" },
2949 { "Stereo1 ADC R Mux", "ADC2", "ADC2 R" },
2951 { "Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux" },
2952 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
2953 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC L Mux" },
2954 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
2956 { "Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux" },
2957 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
2958 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC R Mux" },
2959 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
2961 { "Mono ADC L Mux", "ADC1 L", "ADC1 L" },
2962 { "Mono ADC L Mux", "ADC1 R", "ADC1 R" },
2963 { "Mono ADC L Mux", "ADC2 L", "ADC2 L" },
2964 { "Mono ADC L Mux", "ADC2 R", "ADC2 R" },
2966 { "Mono ADC R Mux", "ADC1 L", "ADC1 L" },
2967 { "Mono ADC R Mux", "ADC1 R", "ADC1 R" },
2968 { "Mono ADC R Mux", "ADC2 L", "ADC2 L" },
2969 { "Mono ADC R Mux", "ADC2 R", "ADC2 R" },
2971 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
2972 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2973 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2974 { "Mono ADC L1 Mux", "ADC", "Mono ADC L Mux" },
2976 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2977 { "Mono ADC R1 Mux", "ADC", "Mono ADC R Mux" },
2978 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
2979 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2981 { "Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
2982 { "Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
2983 { "Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter" },
2985 { "Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
2986 { "Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
2987 { "Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter" },
2989 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
2990 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
2991 { "Mono ADC MIXL", NULL, "ADC Mono Left Filter" },
2993 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
2994 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
2995 { "Mono ADC MIXR", NULL, "ADC Mono Right Filter" },
2997 { "Stereo1 ADC Volume L", NULL, "Stereo1 ADC MIXL" },
2998 { "Stereo1 ADC Volume R", NULL, "Stereo1 ADC MIXR" },
3000 { "IF_ADC1", NULL, "Stereo1 ADC Volume L" },
3001 { "IF_ADC1", NULL, "Stereo1 ADC Volume R" },
3002 { "IF_ADC2", NULL, "Mono ADC MIXL" },
3003 { "IF_ADC2", NULL, "Mono ADC MIXR" },
3034 { "IF1 01 ADC Swap Mux", "L/R", "TDM Data Mux" },
3035 { "IF1 01 ADC Swap Mux", "R/L", "TDM Data Mux" },
3036 { "IF1 01 ADC Swap Mux", "L/L", "TDM Data Mux" },
3037 { "IF1 01 ADC Swap Mux", "R/R", "TDM Data Mux" },
3038 { "IF1 23 ADC Swap Mux", "L/R", "TDM Data Mux" },
3039 { "IF1 23 ADC Swap Mux", "R/L", "TDM Data Mux" },
3040 { "IF1 23 ADC Swap Mux", "L/L", "TDM Data Mux" },
3041 { "IF1 23 ADC Swap Mux", "R/R", "TDM Data Mux" },
3042 { "IF1 45 ADC Swap Mux", "L/R", "TDM Data Mux" },
3043 { "IF1 45 ADC Swap Mux", "R/L", "TDM Data Mux" },
3044 { "IF1 45 ADC Swap Mux", "L/L", "TDM Data Mux" },
3045 { "IF1 45 ADC Swap Mux", "R/R", "TDM Data Mux" },
3046 { "IF1 67 ADC Swap Mux", "L/R", "TDM Data Mux" },
3047 { "IF1 67 ADC Swap Mux", "R/L", "TDM Data Mux" },
3048 { "IF1 67 ADC Swap Mux", "L/L", "TDM Data Mux" },
3049 { "IF1 67 ADC Swap Mux", "R/R", "TDM Data Mux" },
3050 { "IF1 ADC", NULL, "IF1 01 ADC Swap Mux" },
3051 { "IF1 ADC", NULL, "IF1 23 ADC Swap Mux" },
3052 { "IF1 ADC", NULL, "IF1 45 ADC Swap Mux" },
3053 { "IF1 ADC", NULL, "IF1 67 ADC Swap Mux" },
3054 { "IF1 ADC", NULL, "I2S1" },
3056 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
3057 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
3058 { "IF2 ADC Mux", "IF_ADC3", "IF_ADC3" },
3059 { "IF2 ADC Mux", "DAC_REF", "DAC_REF" },
3060 { "IF2 ADC", NULL, "IF2 ADC Mux"},
3061 { "IF2 ADC", NULL, "I2S2" },
3063 { "IF3 ADC Mux", "IF_ADC1", "IF_ADC1" },
3064 { "IF3 ADC Mux", "IF_ADC2", "IF_ADC2" },
3065 { "IF3 ADC Mux", "Stereo2_ADC_L/R", "Stereo2 ADC LR" },
3066 { "IF3 ADC Mux", "DAC_REF", "DAC_REF" },
3067 { "IF3 ADC", NULL, "IF3 ADC Mux"},
3068 { "IF3 ADC", NULL, "I2S3" },
3070 { "AIF1TX", NULL, "IF1 ADC" },
3071 { "IF2 ADC Swap Mux", "L/R", "IF2 ADC" },
3072 { "IF2 ADC Swap Mux", "R/L", "IF2 ADC" },
3073 { "IF2 ADC Swap Mux", "L/L", "IF2 ADC" },
3074 { "IF2 ADC Swap Mux", "R/R", "IF2 ADC" },
3075 { "AIF2TX", NULL, "IF2 ADC Swap Mux" },
3076 { "IF3 ADC Swap Mux", "L/R", "IF3 ADC" },
3077 { "IF3 ADC Swap Mux", "R/L", "IF3 ADC" },
3078 { "IF3 ADC Swap Mux", "L/L", "IF3 ADC" },
3079 { "IF3 ADC Swap Mux", "R/R", "IF3 ADC" },
3080 { "AIF3TX", NULL, "IF3 ADC Swap Mux" },
3119 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC Volume L" },
3121 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC Volume R" },
3130 { "DAC L2 Mux", "Mono ADC MIX", "Mono ADC MIXL" },
3136 { "DAC R2 Mux", "Mono ADC MIX", "Mono ADC MIXR" },
3217 { "SPK Amp", NULL, "SYS CLK DET" },
3227 { "Mono Amp", NULL, "SYS CLK DET" },
3234 { "HP Amp", NULL, "SYS CLK DET" },
3249 { "LOUT Amp", NULL, "SYS CLK DET" },
3276 struct snd_soc_component *component = dai->component; in rt5659_hw_params()
3281 rt5659->lrck[dai->id] = params_rate(params); in rt5659_hw_params()
3282 pre_div = rl6231_get_clk_info(rt5659->sysclk, rt5659->lrck[dai->id]); in rt5659_hw_params()
3284 dev_err(component->dev, "Unsupported clock setting %d for DAI %d\n", in rt5659_hw_params()
3285 rt5659->lrck[dai->id], dai->id); in rt5659_hw_params()
3286 return -EINVAL; in rt5659_hw_params()
3290 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size); in rt5659_hw_params()
3291 return -EINVAL; in rt5659_hw_params()
3294 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", in rt5659_hw_params()
3295 rt5659->lrck[dai->id], pre_div, dai->id); in rt5659_hw_params()
3310 return -EINVAL; in rt5659_hw_params()
3313 switch (dai->id) { in rt5659_hw_params()
3333 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); in rt5659_hw_params()
3334 return -EINVAL; in rt5659_hw_params()
3339 switch (rt5659->lrck[dai->id]) { in rt5659_hw_params()
3359 struct snd_soc_component *component = dai->component; in rt5659_set_dai_fmt()
3365 rt5659->master[dai->id] = 1; in rt5659_set_dai_fmt()
3369 rt5659->master[dai->id] = 0; in rt5659_set_dai_fmt()
3372 return -EINVAL; in rt5659_set_dai_fmt()
3382 return -EINVAL; in rt5659_set_dai_fmt()
3398 return -EINVAL; in rt5659_set_dai_fmt()
3401 switch (dai->id) { in rt5659_set_dai_fmt()
3418 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); in rt5659_set_dai_fmt()
3419 return -EINVAL; in rt5659_set_dai_fmt()
3430 if (freq == rt5659->sysclk && clk_id == rt5659->sysclk_src) in rt5659_set_component_sysclk()
3444 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); in rt5659_set_component_sysclk()
3445 return -EINVAL; in rt5659_set_component_sysclk()
3449 rt5659->sysclk = freq; in rt5659_set_component_sysclk()
3450 rt5659->sysclk_src = clk_id; in rt5659_set_component_sysclk()
3452 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", in rt5659_set_component_sysclk()
3466 if (source == rt5659->pll_src && freq_in == rt5659->pll_in && in rt5659_set_component_pll()
3467 freq_out == rt5659->pll_out) in rt5659_set_component_pll()
3471 dev_dbg(component->dev, "PLL disabled\n"); in rt5659_set_component_pll()
3473 rt5659->pll_in = 0; in rt5659_set_component_pll()
3474 rt5659->pll_out = 0; in rt5659_set_component_pll()
3498 dev_err(component->dev, "Unknown PLL source %d\n", source); in rt5659_set_component_pll()
3499 return -EINVAL; in rt5659_set_component_pll()
3504 dev_err(component->dev, "Unsupport input clock %d\n", freq_in); in rt5659_set_component_pll()
3508 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", in rt5659_set_component_pll()
3518 rt5659->pll_in = freq_in; in rt5659_set_component_pll()
3519 rt5659->pll_out = freq_out; in rt5659_set_component_pll()
3520 rt5659->pll_src = source; in rt5659_set_component_pll()
3528 struct snd_soc_component *component = dai->component; in rt5659_set_tdm_slot()
3550 return -EINVAL; in rt5659_set_tdm_slot()
3569 return -EINVAL; in rt5659_set_tdm_slot()
3579 struct snd_soc_component *component = dai->component; in rt5659_set_bclk_ratio()
3582 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio); in rt5659_set_bclk_ratio()
3584 rt5659->bclk[dai->id] = ratio; in rt5659_set_bclk_ratio()
3587 switch (dai->id) { in rt5659_set_bclk_ratio()
3613 regmap_update_bits(rt5659->regmap, RT5659_DIG_MISC, in rt5659_set_bias_level()
3615 regmap_update_bits(rt5659->regmap, RT5659_PWR_DIG_1, in rt5659_set_bias_level()
3617 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1, in rt5659_set_bias_level()
3621 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1, in rt5659_set_bias_level()
3627 if (dapm->bias_level == SND_SOC_BIAS_OFF) { in rt5659_set_bias_level()
3628 ret = clk_prepare_enable(rt5659->mclk); in rt5659_set_bias_level()
3630 dev_err(component->dev, in rt5659_set_bias_level()
3638 regmap_update_bits(rt5659->regmap, RT5659_PWR_DIG_1, in rt5659_set_bias_level()
3640 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1, in rt5659_set_bias_level()
3644 regmap_update_bits(rt5659->regmap, RT5659_DIG_MISC, in rt5659_set_bias_level()
3646 clk_disable_unprepare(rt5659->mclk); in rt5659_set_bias_level()
3660 rt5659->component = component; in rt5659_probe()
3669 regmap_write(rt5659->regmap, RT5659_RESET, 0); in rt5659_remove()
3677 regcache_cache_only(rt5659->regmap, true); in rt5659_suspend()
3678 regcache_mark_dirty(rt5659->regmap); in rt5659_suspend()
3686 regcache_cache_only(rt5659->regmap, false); in rt5659_resume()
3687 regcache_sync(rt5659->regmap); in rt5659_resume()
3709 .name = "rt5659-aif1",
3728 .name = "rt5659-aif2",
3747 .name = "rt5659-aif3",
3807 rt5659->pdata.in1_diff = device_property_read_bool(dev, in rt5659_parse_dt()
3808 "realtek,in1-differential"); in rt5659_parse_dt()
3809 rt5659->pdata.in3_diff = device_property_read_bool(dev, in rt5659_parse_dt()
3810 "realtek,in3-differential"); in rt5659_parse_dt()
3811 rt5659->pdata.in4_diff = device_property_read_bool(dev, in rt5659_parse_dt()
3812 "realtek,in4-differential"); in rt5659_parse_dt()
3815 device_property_read_u32(dev, "realtek,dmic1-data-pin", in rt5659_parse_dt()
3816 &rt5659->pdata.dmic1_data_pin); in rt5659_parse_dt()
3817 device_property_read_u32(dev, "realtek,dmic2-data-pin", in rt5659_parse_dt()
3818 &rt5659->pdata.dmic2_data_pin); in rt5659_parse_dt()
3819 device_property_read_u32(dev, "realtek,jd-src", in rt5659_parse_dt()
3820 &rt5659->pdata.jd_src); in rt5659_parse_dt()
3831 regmap_write(rt5659->regmap, RT5659_BIAS_CUR_CTRL_8, 0xa502); in rt5659_calibrate()
3832 regmap_write(rt5659->regmap, RT5659_CHOP_DAC, 0x3030); in rt5659_calibrate()
3834 regmap_write(rt5659->regmap, RT5659_PRE_DIV_1, 0xef00); in rt5659_calibrate()
3835 regmap_write(rt5659->regmap, RT5659_PRE_DIV_2, 0xeffc); in rt5659_calibrate()
3836 regmap_write(rt5659->regmap, RT5659_MICBIAS_2, 0x0280); in rt5659_calibrate()
3837 regmap_write(rt5659->regmap, RT5659_DIG_MISC, 0x0001); in rt5659_calibrate()
3838 regmap_write(rt5659->regmap, RT5659_GLB_CLK, 0x8000); in rt5659_calibrate()
3840 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0xaa7e); in rt5659_calibrate()
3842 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0xfe7e); in rt5659_calibrate()
3844 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_3, 0x0004); in rt5659_calibrate()
3845 regmap_write(rt5659->regmap, RT5659_PWR_DIG_2, 0x0400); in rt5659_calibrate()
3847 regmap_write(rt5659->regmap, RT5659_PWR_DIG_1, 0x0080); in rt5659_calibrate()
3849 regmap_write(rt5659->regmap, RT5659_DEPOP_1, 0x0009); in rt5659_calibrate()
3851 regmap_write(rt5659->regmap, RT5659_PWR_DIG_1, 0x0f80); in rt5659_calibrate()
3853 regmap_write(rt5659->regmap, RT5659_HP_CHARGE_PUMP_1, 0x0e16); in rt5659_calibrate()
3856 /* Enalbe K ADC Power And Clock */ in rt5659_calibrate()
3857 regmap_write(rt5659->regmap, RT5659_CAL_REC, 0x0505); in rt5659_calibrate()
3859 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_3, 0x0184); in rt5659_calibrate()
3860 regmap_write(rt5659->regmap, RT5659_CALIB_ADC_CTRL, 0x3c05); in rt5659_calibrate()
3861 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x20c1); in rt5659_calibrate()
3864 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x2cc1); in rt5659_calibrate()
3865 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0x5100); in rt5659_calibrate()
3866 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x0014); in rt5659_calibrate()
3867 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0xd100); in rt5659_calibrate()
3870 /* Manual K ADC Offset */ in rt5659_calibrate()
3871 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x2cc1); in rt5659_calibrate()
3872 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0x4900); in rt5659_calibrate()
3873 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x0016); in rt5659_calibrate()
3874 regmap_update_bits(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, in rt5659_calibrate()
3879 regmap_read(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, &value); in rt5659_calibrate()
3886 dev_err(rt5659->component->dev, in rt5659_calibrate()
3895 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x2cc1); in rt5659_calibrate()
3896 regmap_write(rt5659->regmap, RT5659_HP_VOL, 0x0000); in rt5659_calibrate()
3897 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0x4500); in rt5659_calibrate()
3898 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x001f); in rt5659_calibrate()
3899 regmap_update_bits(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, in rt5659_calibrate()
3904 regmap_read(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, &value); in rt5659_calibrate()
3911 dev_err(rt5659->component->dev, in rt5659_calibrate()
3919 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x0000); in rt5659_calibrate()
3920 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x20c0); in rt5659_calibrate()
3924 regmap_write(rt5659->regmap, RT5659_CLASSD_0, 0x2021); in rt5659_calibrate()
3925 regmap_write(rt5659->regmap, RT5659_CLASSD_CTRL_1, 0x0260); in rt5659_calibrate()
3926 regmap_write(rt5659->regmap, RT5659_PWR_MIXER, 0x3000); in rt5659_calibrate()
3927 regmap_write(rt5659->regmap, RT5659_PWR_VOL, 0xc000); in rt5659_calibrate()
3928 regmap_write(rt5659->regmap, RT5659_A_DAC_MUX, 0x000c); in rt5659_calibrate()
3929 regmap_write(rt5659->regmap, RT5659_DIG_MISC, 0x8000); in rt5659_calibrate()
3930 regmap_write(rt5659->regmap, RT5659_SPO_VOL, 0x0808); in rt5659_calibrate()
3931 regmap_write(rt5659->regmap, RT5659_SPK_L_MIXER, 0x001e); in rt5659_calibrate()
3932 regmap_write(rt5659->regmap, RT5659_SPK_R_MIXER, 0x001e); in rt5659_calibrate()
3933 regmap_write(rt5659->regmap, RT5659_CLASSD_1, 0x0803); in rt5659_calibrate()
3934 regmap_write(rt5659->regmap, RT5659_CLASSD_2, 0x0554); in rt5659_calibrate()
3935 regmap_write(rt5659->regmap, RT5659_SPO_AMP_GAIN, 0x1103); in rt5659_calibrate()
3937 /* Enalbe K ADC Power And Clock */ in rt5659_calibrate()
3938 regmap_write(rt5659->regmap, RT5659_CAL_REC, 0x0909); in rt5659_calibrate()
3939 regmap_update_bits(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x0001, in rt5659_calibrate()
3943 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_3, 0x0000); in rt5659_calibrate()
3944 regmap_write(rt5659->regmap, RT5659_CLASSD_0, 0x0021); in rt5659_calibrate()
3945 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_1, 0x3e80); in rt5659_calibrate()
3946 regmap_update_bits(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_1, in rt5659_calibrate()
3951 regmap_read(rt5659->regmap, in rt5659_calibrate()
3959 dev_err(rt5659->component->dev, in rt5659_calibrate()
3969 regmap_write(rt5659->regmap, RT5659_DIG_MISC, 0x0000); in rt5659_calibrate()
3970 regmap_write(rt5659->regmap, RT5659_MONOMIX_IN_GAIN, 0x021f); in rt5659_calibrate()
3971 regmap_write(rt5659->regmap, RT5659_MONO_OUT, 0x480a); in rt5659_calibrate()
3973 regmap_write(rt5659->regmap, RT5659_MONO_GAIN, 0x0003); in rt5659_calibrate()
3974 regmap_write(rt5659->regmap, RT5659_MONO_NG2_CTRL_5, 0x0009); in rt5659_calibrate()
3977 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_3, 0x000f); in rt5659_calibrate()
3978 regmap_write(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e00); in rt5659_calibrate()
3979 regmap_update_bits(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1, in rt5659_calibrate()
3984 regmap_read(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1, in rt5659_calibrate()
3992 dev_err(rt5659->component->dev, in rt5659_calibrate()
4000 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_3, 0x0003); in rt5659_calibrate()
4004 regmap_write(rt5659->regmap, RT5659_CAL_REC, 0x0808); in rt5659_calibrate()
4005 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_3, 0x0000); in rt5659_calibrate()
4006 regmap_write(rt5659->regmap, RT5659_CALIB_ADC_CTRL, 0x2005); in rt5659_calibrate()
4007 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x20c0); in rt5659_calibrate()
4008 regmap_write(rt5659->regmap, RT5659_DEPOP_1, 0x0000); in rt5659_calibrate()
4009 regmap_write(rt5659->regmap, RT5659_CLASSD_1, 0x0011); in rt5659_calibrate()
4010 regmap_write(rt5659->regmap, RT5659_CLASSD_2, 0x0150); in rt5659_calibrate()
4011 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0xfe3e); in rt5659_calibrate()
4012 regmap_write(rt5659->regmap, RT5659_MONO_OUT, 0xc80a); in rt5659_calibrate()
4013 regmap_write(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e04); in rt5659_calibrate()
4014 regmap_write(rt5659->regmap, RT5659_PWR_MIXER, 0x0000); in rt5659_calibrate()
4015 regmap_write(rt5659->regmap, RT5659_PWR_VOL, 0x0000); in rt5659_calibrate()
4016 regmap_write(rt5659->regmap, RT5659_PWR_DIG_1, 0x0000); in rt5659_calibrate()
4017 regmap_write(rt5659->regmap, RT5659_PWR_DIG_2, 0x0000); in rt5659_calibrate()
4018 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0x003e); in rt5659_calibrate()
4019 regmap_write(rt5659->regmap, RT5659_CLASSD_CTRL_1, 0x0060); in rt5659_calibrate()
4020 regmap_write(rt5659->regmap, RT5659_CLASSD_0, 0x2021); in rt5659_calibrate()
4021 regmap_write(rt5659->regmap, RT5659_GLB_CLK, 0x0000); in rt5659_calibrate()
4022 regmap_write(rt5659->regmap, RT5659_MICBIAS_2, 0x0080); in rt5659_calibrate()
4023 regmap_write(rt5659->regmap, RT5659_HP_VOL, 0x8080); in rt5659_calibrate()
4024 regmap_write(rt5659->regmap, RT5659_HP_CHARGE_PUMP_1, 0x0c16); in rt5659_calibrate()
4031 regmap_read(rt5659->regmap, RT5659_GPIO_STA, &value); in rt5659_intel_hd_header_probe_setup()
4033 rt5659->hda_hp_plugged = true; in rt5659_intel_hd_header_probe_setup()
4034 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_1, in rt5659_intel_hd_header_probe_setup()
4037 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_1, in rt5659_intel_hd_header_probe_setup()
4041 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1, in rt5659_intel_hd_header_probe_setup()
4045 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1, in rt5659_intel_hd_header_probe_setup()
4048 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_3, RT5659_PWR_LDO2, in rt5659_intel_hd_header_probe_setup()
4050 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_2, RT5659_PWR_MB1, in rt5659_intel_hd_header_probe_setup()
4052 regmap_update_bits(rt5659->regmap, RT5659_PWR_VOL, RT5659_PWR_MIC_DET, in rt5659_intel_hd_header_probe_setup()
4056 regmap_update_bits(rt5659->regmap, RT5659_4BTN_IL_CMD_2, in rt5659_intel_hd_header_probe_setup()
4058 regmap_read(rt5659->regmap, RT5659_4BTN_IL_CMD_1, &value); in rt5659_intel_hd_header_probe_setup()
4059 regmap_write(rt5659->regmap, RT5659_4BTN_IL_CMD_1, value); in rt5659_intel_hd_header_probe_setup()
4060 regmap_read(rt5659->regmap, RT5659_4BTN_IL_CMD_1, &value); in rt5659_intel_hd_header_probe_setup()
4063 rt5659->hda_mic_plugged = true; in rt5659_intel_hd_header_probe_setup()
4064 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2, in rt5659_intel_hd_header_probe_setup()
4067 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2, in rt5659_intel_hd_header_probe_setup()
4071 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2, in rt5659_intel_hd_header_probe_setup()
4078 struct rt5659_platform_data *pdata = dev_get_platdata(&i2c->dev); in rt5659_i2c_probe()
4083 rt5659 = devm_kzalloc(&i2c->dev, sizeof(struct rt5659_priv), in rt5659_i2c_probe()
4087 return -ENOMEM; in rt5659_i2c_probe()
4092 rt5659->pdata = *pdata; in rt5659_i2c_probe()
4094 rt5659_parse_dt(rt5659, &i2c->dev); in rt5659_i2c_probe()
4096 rt5659->gpiod_ldo1_en = devm_gpiod_get_optional(&i2c->dev, "ldo1-en", in rt5659_i2c_probe()
4098 if (IS_ERR(rt5659->gpiod_ldo1_en)) in rt5659_i2c_probe()
4099 dev_warn(&i2c->dev, "Request ldo1-en GPIO failed\n"); in rt5659_i2c_probe()
4101 rt5659->gpiod_reset = devm_gpiod_get_optional(&i2c->dev, "reset", in rt5659_i2c_probe()
4107 rt5659->regmap = devm_regmap_init_i2c(i2c, &rt5659_regmap); in rt5659_i2c_probe()
4108 if (IS_ERR(rt5659->regmap)) { in rt5659_i2c_probe()
4109 ret = PTR_ERR(rt5659->regmap); in rt5659_i2c_probe()
4110 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", in rt5659_i2c_probe()
4115 regmap_read(rt5659->regmap, RT5659_DEVICE_ID, &val); in rt5659_i2c_probe()
4117 dev_err(&i2c->dev, in rt5659_i2c_probe()
4119 return -ENODEV; in rt5659_i2c_probe()
4122 regmap_write(rt5659->regmap, RT5659_RESET, 0); in rt5659_i2c_probe()
4125 rt5659->mclk = devm_clk_get(&i2c->dev, "mclk"); in rt5659_i2c_probe()
4126 if (IS_ERR(rt5659->mclk)) { in rt5659_i2c_probe()
4127 if (PTR_ERR(rt5659->mclk) != -ENOENT) in rt5659_i2c_probe()
4128 return PTR_ERR(rt5659->mclk); in rt5659_i2c_probe()
4130 rt5659->mclk = NULL; in rt5659_i2c_probe()
4136 if (rt5659->pdata.in1_diff) in rt5659_i2c_probe()
4137 regmap_update_bits(rt5659->regmap, RT5659_IN1_IN2, in rt5659_i2c_probe()
4139 if (rt5659->pdata.in3_diff) in rt5659_i2c_probe()
4140 regmap_update_bits(rt5659->regmap, RT5659_IN3_IN4, in rt5659_i2c_probe()
4142 if (rt5659->pdata.in4_diff) in rt5659_i2c_probe()
4143 regmap_update_bits(rt5659->regmap, RT5659_IN3_IN4, in rt5659_i2c_probe()
4147 if (rt5659->pdata.dmic1_data_pin != RT5659_DMIC1_NULL || in rt5659_i2c_probe()
4148 rt5659->pdata.dmic2_data_pin != RT5659_DMIC2_NULL) { in rt5659_i2c_probe()
4149 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1, in rt5659_i2c_probe()
4152 switch (rt5659->pdata.dmic1_data_pin) { in rt5659_i2c_probe()
4154 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1, in rt5659_i2c_probe()
4159 regmap_update_bits(rt5659->regmap, in rt5659_i2c_probe()
4163 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1, in rt5659_i2c_probe()
4165 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1, in rt5659_i2c_probe()
4170 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1, in rt5659_i2c_probe()
4172 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1, in rt5659_i2c_probe()
4177 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1, in rt5659_i2c_probe()
4179 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1, in rt5659_i2c_probe()
4185 dev_dbg(&i2c->dev, "no DMIC1\n"); in rt5659_i2c_probe()
4189 switch (rt5659->pdata.dmic2_data_pin) { in rt5659_i2c_probe()
4191 regmap_update_bits(rt5659->regmap, in rt5659_i2c_probe()
4198 regmap_update_bits(rt5659->regmap, in rt5659_i2c_probe()
4202 regmap_update_bits(rt5659->regmap, in rt5659_i2c_probe()
4209 regmap_update_bits(rt5659->regmap, in rt5659_i2c_probe()
4213 regmap_update_bits(rt5659->regmap, in rt5659_i2c_probe()
4220 regmap_update_bits(rt5659->regmap, in rt5659_i2c_probe()
4224 regmap_update_bits(rt5659->regmap, in rt5659_i2c_probe()
4231 dev_dbg(&i2c->dev, "no DMIC2\n"); in rt5659_i2c_probe()
4236 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1, in rt5659_i2c_probe()
4245 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1, in rt5659_i2c_probe()
4250 switch (rt5659->pdata.jd_src) { in rt5659_i2c_probe()
4252 regmap_write(rt5659->regmap, RT5659_EJD_CTRL_1, 0xa880); in rt5659_i2c_probe()
4253 regmap_write(rt5659->regmap, RT5659_RC_CLK_CTRL, 0x9000); in rt5659_i2c_probe()
4254 regmap_write(rt5659->regmap, RT5659_GPIO_CTRL_1, 0xc800); in rt5659_i2c_probe()
4255 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1, in rt5659_i2c_probe()
4257 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_2, 0x0001); in rt5659_i2c_probe()
4258 regmap_write(rt5659->regmap, RT5659_IRQ_CTRL_2, 0x0040); in rt5659_i2c_probe()
4259 INIT_DELAYED_WORK(&rt5659->jack_detect_work, in rt5659_i2c_probe()
4263 regmap_write(rt5659->regmap, RT5659_GPIO_CTRL_3, 0x8000); in rt5659_i2c_probe()
4264 regmap_write(rt5659->regmap, RT5659_RC_CLK_CTRL, 0x0900); in rt5659_i2c_probe()
4265 regmap_write(rt5659->regmap, RT5659_EJD_CTRL_1, 0x70c0); in rt5659_i2c_probe()
4266 regmap_write(rt5659->regmap, RT5659_JD_CTRL_1, 0x2000); in rt5659_i2c_probe()
4267 regmap_write(rt5659->regmap, RT5659_IRQ_CTRL_1, 0x0040); in rt5659_i2c_probe()
4268 INIT_DELAYED_WORK(&rt5659->jack_detect_work, in rt5659_i2c_probe()
4276 if (i2c->irq) { in rt5659_i2c_probe()
4277 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, in rt5659_i2c_probe()
4281 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret); in rt5659_i2c_probe()
4284 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1, in rt5659_i2c_probe()
4288 return devm_snd_soc_register_component(&i2c->dev, in rt5659_i2c_probe()
4297 regmap_write(rt5659->regmap, RT5659_RESET, 0); in rt5659_i2c_shutdown()