Lines Matching +full:adc +full:- +full:channel +full:- +full:clk +full:- +full:src
1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <sound/soc-dapm.h>
51 /* ratio for input clk freq */
71 { 32, 3 }, /* OSR 32, SRC 1/8 */
72 { 64, 2 }, /* OSR 64, SRC 1/4 */
73 { 128, 1 }, /* OSR 128, SRC 1/2 */
74 { 256, 0 }, /* OSR 256, SRC 1 */
183 static const DECLARE_TLV_DB_MINMAX(adc_vol_tlv, -12800, 3600);
184 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
207 "ADC channel 1", "ADC channel 2", "ADC channel 3", "ADC channel 4"
236 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in adc_power_control()
242 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1, in adc_power_control()
244 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2, in adc_power_control()
247 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1, in adc_power_control()
249 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2, in adc_power_control()
258 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in aiftx_power_control()
262 regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0001); in aiftx_power_control()
263 regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0000); in aiftx_power_control()
295 SND_SOC_DAPM_PGA("ADC CH1", NAU8540_REG_ANALOG_PWR, 0, 0, NULL, 0),
296 SND_SOC_DAPM_PGA("ADC CH2", NAU8540_REG_ANALOG_PWR, 1, 0, NULL, 0),
297 SND_SOC_DAPM_PGA("ADC CH3", NAU8540_REG_ANALOG_PWR, 2, 0, NULL, 0),
298 SND_SOC_DAPM_PGA("ADC CH4", NAU8540_REG_ANALOG_PWR, 3, 0, NULL, 0),
324 {"ADC CH1", NULL, "ADC1"},
325 {"ADC CH2", NULL, "ADC2"},
326 {"ADC CH3", NULL, "ADC3"},
327 {"ADC CH4", NULL, "ADC4"},
334 {"Digital CH1 Mux", "ADC channel 1", "ADC CH1"},
335 {"Digital CH1 Mux", "ADC channel 2", "ADC CH2"},
336 {"Digital CH1 Mux", "ADC channel 3", "ADC CH3"},
337 {"Digital CH1 Mux", "ADC channel 4", "ADC CH4"},
339 {"Digital CH2 Mux", "ADC channel 1", "ADC CH1"},
340 {"Digital CH2 Mux", "ADC channel 2", "ADC CH2"},
341 {"Digital CH2 Mux", "ADC channel 3", "ADC CH3"},
342 {"Digital CH2 Mux", "ADC channel 4", "ADC CH4"},
344 {"Digital CH3 Mux", "ADC channel 1", "ADC CH1"},
345 {"Digital CH3 Mux", "ADC channel 2", "ADC CH2"},
346 {"Digital CH3 Mux", "ADC channel 3", "ADC CH3"},
347 {"Digital CH3 Mux", "ADC channel 4", "ADC CH4"},
349 {"Digital CH4 Mux", "ADC channel 1", "ADC CH1"},
350 {"Digital CH4 Mux", "ADC channel 2", "ADC CH2"},
351 {"Digital CH4 Mux", "ADC channel 3", "ADC CH3"},
352 {"Digital CH4 Mux", "ADC channel 4", "ADC CH4"},
363 return -EINVAL; in nau8540_clock_check()
366 dev_err(nau8540->dev, "exceed the maximum frequency of CLK_ADC\n"); in nau8540_clock_check()
367 return -EINVAL; in nau8540_clock_check()
376 struct snd_soc_component *component = dai->component; in nau8540_hw_params()
381 * ADC clock frequency is defined as Over Sampling Rate (OSR) in nau8540_hw_params()
386 regmap_read(nau8540->regmap, NAU8540_REG_ADC_SAMPLE_RATE, &osr); in nau8540_hw_params()
389 return -EINVAL; in nau8540_hw_params()
390 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC, in nau8540_hw_params()
408 return -EINVAL; in nau8540_hw_params()
411 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0, in nau8540_hw_params()
419 struct snd_soc_component *component = dai->component; in nau8540_set_fmt()
430 return -EINVAL; in nau8540_set_fmt()
440 return -EINVAL; in nau8540_set_fmt()
461 return -EINVAL; in nau8540_set_fmt()
464 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0, in nau8540_set_fmt()
467 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1, in nau8540_set_fmt()
469 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2, in nau8540_set_fmt()
476 * nau8540_set_tdm_slot - configure DAI TX TDM.
479 * 0xf for normal 4 channel TDM.
480 * 0xf0 for shifted 4 channel TDM
490 struct snd_soc_component *component = dai->component; in nau8540_set_tdm_slot()
495 return -EINVAL; in nau8540_set_tdm_slot()
504 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL4, in nau8540_set_tdm_slot()
507 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1, in nau8540_set_tdm_slot()
509 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2, in nau8540_set_tdm_slot()
528 .name = "nau8540-hifi",
540 * nau8540_calc_fll_param - Calculate FLL parameters.
556 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar. in nau8540_calc_fll_param()
565 return -EINVAL; in nau8540_calc_fll_param()
566 fll_param->clk_ref_div = fll_pre_scalar[i].val; in nau8540_calc_fll_param()
574 return -EINVAL; in nau8540_calc_fll_param()
575 fll_param->ratio = fll_ratio[i].val; in nau8540_calc_fll_param()
578 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be in nau8540_calc_fll_param()
593 return -EINVAL; in nau8540_calc_fll_param()
594 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val; in nau8540_calc_fll_param()
596 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional in nau8540_calc_fll_param()
599 fvco = div_u64(fvco_max << 16, fref * fll_param->ratio); in nau8540_calc_fll_param()
600 fll_param->fll_int = (fvco >> 16) & 0x3FF; in nau8540_calc_fll_param()
601 fll_param->fll_frac = fvco & 0xFFFF; in nau8540_calc_fll_param()
610 NAU8540_CLK_SRC_MCLK | fll_param->mclk_src); in nau8540_fll_apply()
613 fll_param->ratio | (0x6 << NAU8540_ICTRL_LATCH_SFT)); in nau8540_fll_apply()
614 /* FLL 16-bit fractional input */ in nau8540_fll_apply()
615 regmap_write(regmap, NAU8540_REG_FLL2, fll_param->fll_frac); in nau8540_fll_apply()
616 /* FLL 10-bit integer input */ in nau8540_fll_apply()
618 NAU8540_FLL_INTEGER_MASK, fll_param->fll_int); in nau8540_fll_apply()
619 /* FLL pre-scaler */ in nau8540_fll_apply()
622 fll_param->clk_ref_div << NAU8540_FLL_REF_DIV_SFT); in nau8540_fll_apply()
627 if (fll_param->fll_frac) { in nau8540_fll_apply()
655 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3, in nau8540_set_pll()
661 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3, in nau8540_set_pll()
668 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3, in nau8540_set_pll()
675 dev_err(nau8540->dev, "Invalid clock id (%d)\n", pll_id); in nau8540_set_pll()
676 return -EINVAL; in nau8540_set_pll()
678 dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n", in nau8540_set_pll()
684 dev_err(nau8540->dev, "Unsupported input clock %d\n", freq_in); in nau8540_set_pll()
687 dev_dbg(nau8540->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n", in nau8540_set_pll()
691 nau8540_fll_apply(nau8540->regmap, &fll_param); in nau8540_set_pll()
693 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC, in nau8540_set_pll()
707 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC, in nau8540_set_sysclk()
709 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6, in nau8540_set_sysclk()
714 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6, in nau8540_set_sysclk()
716 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC, in nau8540_set_sysclk()
721 dev_err(nau8540->dev, "Invalid clock id (%d)\n", clk_id); in nau8540_set_sysclk()
722 return -EINVAL; in nau8540_set_sysclk()
725 dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n", in nau8540_set_sysclk()
739 struct regmap *regmap = nau8540->regmap; in nau8540_init_regs()
754 /* ADC OSR selection, CLK_ADC = Fs * OSR; in nau8540_init_regs()
755 * Channel time alignment enable. in nau8540_init_regs()
778 regcache_cache_only(nau8540->regmap, true); in nau8540_suspend()
779 regcache_mark_dirty(nau8540->regmap); in nau8540_suspend()
788 regcache_cache_only(nau8540->regmap, false); in nau8540_resume()
789 regcache_sync(nau8540->regmap); in nau8540_resume()
829 struct device *dev = &i2c->dev; in nau8540_i2c_probe()
836 return -ENOMEM; in nau8540_i2c_probe()
840 nau8540->regmap = devm_regmap_init_i2c(i2c, &nau8540_regmap_config); in nau8540_i2c_probe()
841 if (IS_ERR(nau8540->regmap)) in nau8540_i2c_probe()
842 return PTR_ERR(nau8540->regmap); in nau8540_i2c_probe()
843 ret = regmap_read(nau8540->regmap, NAU8540_REG_I2C_DEVICE_ID, &value); in nau8540_i2c_probe()
850 nau8540->dev = dev; in nau8540_i2c_probe()
851 nau8540_reset_chip(nau8540->regmap); in nau8540_i2c_probe()