Lines Matching +full:0 +full:x1
21 #define RG_VOW13M_CK_PDN_MASK 0x1
22 #define RG_VOW13M_CK_PDN_MASK_SFT (0x1 << 13)
24 #define RG_VOW32K_CK_PDN_MASK 0x1
25 #define RG_VOW32K_CK_PDN_MASK_SFT (0x1 << 12)
27 #define RG_AUD_INTRP_CK_PDN_MASK 0x1
28 #define RG_AUD_INTRP_CK_PDN_MASK_SFT (0x1 << 8)
30 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK 0x1
31 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK_SFT (0x1 << 7)
33 #define RG_AUDNCP_CK_PDN_MASK 0x1
34 #define RG_AUDNCP_CK_PDN_MASK_SFT (0x1 << 6)
36 #define RG_ZCD13M_CK_PDN_MASK 0x1
37 #define RG_ZCD13M_CK_PDN_MASK_SFT (0x1 << 5)
39 #define RG_AUDIF_CK_PDN_MASK 0x1
40 #define RG_AUDIF_CK_PDN_MASK_SFT (0x1 << 2)
42 #define RG_AUD_CK_PDN_MASK 0x1
43 #define RG_AUD_CK_PDN_MASK_SFT (0x1 << 1)
44 #define RG_ACCDET_CK_PDN_SFT 0
45 #define RG_ACCDET_CK_PDN_MASK 0x1
46 #define RG_ACCDET_CK_PDN_MASK_SFT (0x1 << 0)
49 #define RG_AUD_TOP_CKPDN_CON0_SET_SFT 0
50 #define RG_AUD_TOP_CKPDN_CON0_SET_MASK 0x3fff
51 #define RG_AUD_TOP_CKPDN_CON0_SET_MASK_SFT (0x3fff << 0)
54 #define RG_AUD_TOP_CKPDN_CON0_CLR_SFT 0
55 #define RG_AUD_TOP_CKPDN_CON0_CLR_MASK 0x3fff
56 #define RG_AUD_TOP_CKPDN_CON0_CLR_MASK_SFT (0x3fff << 0)
60 #define RG_AUDIF_CK_CKSEL_MASK 0x1
61 #define RG_AUDIF_CK_CKSEL_MASK_SFT (0x1 << 3)
63 #define RG_AUD_CK_CKSEL_MASK 0x1
64 #define RG_AUD_CK_CKSEL_MASK_SFT (0x1 << 2)
67 #define RG_AUD_TOP_CKSEL_CON0_SET_SFT 0
68 #define RG_AUD_TOP_CKSEL_CON0_SET_MASK 0xf
69 #define RG_AUD_TOP_CKSEL_CON0_SET_MASK_SFT (0xf << 0)
72 #define RG_AUD_TOP_CKSEL_CON0_CLR_SFT 0
73 #define RG_AUD_TOP_CKSEL_CON0_CLR_MASK 0xf
74 #define RG_AUD_TOP_CKSEL_CON0_CLR_MASK_SFT (0xf << 0)
78 #define RG_VOW13M_CK_TSTSEL_MASK 0x1
79 #define RG_VOW13M_CK_TSTSEL_MASK_SFT (0x1 << 9)
81 #define RG_VOW13M_CK_TST_DIS_MASK 0x1
82 #define RG_VOW13M_CK_TST_DIS_MASK_SFT (0x1 << 8)
84 #define RG_AUD26M_CK_TSTSEL_MASK 0x1
85 #define RG_AUD26M_CK_TSTSEL_MASK_SFT (0x1 << 4)
87 #define RG_AUDIF_CK_TSTSEL_MASK 0x1
88 #define RG_AUDIF_CK_TSTSEL_MASK_SFT (0x1 << 3)
90 #define RG_AUD_CK_TSTSEL_MASK 0x1
91 #define RG_AUD_CK_TSTSEL_MASK_SFT (0x1 << 2)
92 #define RG_AUD26M_CK_TST_DIS_SFT 0
93 #define RG_AUD26M_CK_TST_DIS_MASK 0x1
94 #define RG_AUD26M_CK_TST_DIS_MASK_SFT (0x1 << 0)
97 #define RG_AUD_INTRP_CK_PDN_HWEN_SFT 0
98 #define RG_AUD_INTRP_CK_PDN_HWEN_MASK 0x1
99 #define RG_AUD_INTRP_CK_PDN_HWEN_MASK_SFT (0x1 << 0)
102 #define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_SFT 0
103 #define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_MASK 0xffff
104 #define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_MASK_SFT (0xffff << 0)
107 #define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_SFT 0
108 #define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_MASK 0xffff
109 #define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_MASK_SFT (0xffff << 0)
113 #define RG_AUDNCP_RST_MASK 0x1
114 #define RG_AUDNCP_RST_MASK_SFT (0x1 << 3)
116 #define RG_ZCD_RST_MASK 0x1
117 #define RG_ZCD_RST_MASK_SFT (0x1 << 2)
119 #define RG_ACCDET_RST_MASK 0x1
120 #define RG_ACCDET_RST_MASK_SFT (0x1 << 1)
121 #define RG_AUDIO_RST_SFT 0
122 #define RG_AUDIO_RST_MASK 0x1
123 #define RG_AUDIO_RST_MASK_SFT (0x1 << 0)
126 #define RG_AUD_TOP_RST_CON0_SET_SFT 0
127 #define RG_AUD_TOP_RST_CON0_SET_MASK 0xf
128 #define RG_AUD_TOP_RST_CON0_SET_MASK_SFT (0xf << 0)
131 #define RG_AUD_TOP_RST_CON0_CLR_SFT 0
132 #define RG_AUD_TOP_RST_CON0_CLR_MASK 0xf
133 #define RG_AUD_TOP_RST_CON0_CLR_MASK_SFT (0xf << 0)
137 #define BANK_AUDZCD_SWRST_MASK 0x1
138 #define BANK_AUDZCD_SWRST_MASK_SFT (0x1 << 2)
140 #define BANK_AUDIO_SWRST_MASK 0x1
141 #define BANK_AUDIO_SWRST_MASK_SFT (0x1 << 1)
142 #define BANK_ACCDET_SWRST_SFT 0
143 #define BANK_ACCDET_SWRST_MASK 0x1
144 #define BANK_ACCDET_SWRST_MASK_SFT (0x1 << 0)
147 #define RG_INT_EN_AUDIO_SFT 0
148 #define RG_INT_EN_AUDIO_MASK 0x1
149 #define RG_INT_EN_AUDIO_MASK_SFT (0x1 << 0)
151 #define RG_INT_EN_ACCDET_MASK 0x1
152 #define RG_INT_EN_ACCDET_MASK_SFT (0x1 << 5)
154 #define RG_INT_EN_ACCDET_EINT0_MASK 0x1
155 #define RG_INT_EN_ACCDET_EINT0_MASK_SFT (0x1 << 6)
157 #define RG_INT_EN_ACCDET_EINT1_MASK 0x1
158 #define RG_INT_EN_ACCDET_EINT1_MASK_SFT (0x1 << 7)
161 #define RG_AUD_INT_CON0_SET_SFT 0
162 #define RG_AUD_INT_CON0_SET_MASK 0xffff
163 #define RG_AUD_INT_CON0_SET_MASK_SFT (0xffff << 0)
166 #define RG_AUD_INT_CON0_CLR_SFT 0
167 #define RG_AUD_INT_CON0_CLR_MASK 0xffff
168 #define RG_AUD_INT_CON0_CLR_MASK_SFT (0xffff << 0)
171 #define RG_INT_MASK_AUDIO_SFT 0
172 #define RG_INT_MASK_AUDIO_MASK 0x1
173 #define RG_INT_MASK_AUDIO_MASK_SFT (0x1 << 0)
175 #define RG_INT_MASK_ACCDET_MASK 0x1
176 #define RG_INT_MASK_ACCDET_MASK_SFT (0x1 << 5)
178 #define RG_INT_MASK_ACCDET_EINT0_MASK 0x1
179 #define RG_INT_MASK_ACCDET_EINT0_MASK_SFT (0x1 << 6)
181 #define RG_INT_MASK_ACCDET_EINT1_MASK 0x1
182 #define RG_INT_MASK_ACCDET_EINT1_MASK_SFT (0x1 << 7)
185 #define RG_AUD_INT_MASK_CON0_SET_SFT 0
186 #define RG_AUD_INT_MASK_CON0_SET_MASK 0xff
187 #define RG_AUD_INT_MASK_CON0_SET_MASK_SFT (0xff << 0)
190 #define RG_AUD_INT_MASK_CON0_CLR_SFT 0
191 #define RG_AUD_INT_MASK_CON0_CLR_MASK 0xff
192 #define RG_AUD_INT_MASK_CON0_CLR_MASK_SFT (0xff << 0)
195 #define RG_INT_STATUS_AUDIO_SFT 0
196 #define RG_INT_STATUS_AUDIO_MASK 0x1
197 #define RG_INT_STATUS_AUDIO_MASK_SFT (0x1 << 0)
199 #define RG_INT_STATUS_ACCDET_MASK 0x1
200 #define RG_INT_STATUS_ACCDET_MASK_SFT (0x1 << 5)
202 #define RG_INT_STATUS_ACCDET_EINT0_MASK 0x1
203 #define RG_INT_STATUS_ACCDET_EINT0_MASK_SFT (0x1 << 6)
205 #define RG_INT_STATUS_ACCDET_EINT1_MASK 0x1
206 #define RG_INT_STATUS_ACCDET_EINT1_MASK_SFT (0x1 << 7)
209 #define RG_INT_RAW_STATUS_AUDIO_SFT 0
210 #define RG_INT_RAW_STATUS_AUDIO_MASK 0x1
211 #define RG_INT_RAW_STATUS_AUDIO_MASK_SFT (0x1 << 0)
213 #define RG_INT_RAW_STATUS_ACCDET_MASK 0x1
214 #define RG_INT_RAW_STATUS_ACCDET_MASK_SFT (0x1 << 5)
216 #define RG_INT_RAW_STATUS_ACCDET_EINT0_MASK 0x1
217 #define RG_INT_RAW_STATUS_ACCDET_EINT0_MASK_SFT (0x1 << 6)
219 #define RG_INT_RAW_STATUS_ACCDET_EINT1_MASK 0x1
220 #define RG_INT_RAW_STATUS_ACCDET_EINT1_MASK_SFT (0x1 << 7)
223 #define RG_AUD_TOP_INT_POLARITY_SFT 0
224 #define RG_AUD_TOP_INT_POLARITY_MASK 0x1
225 #define RG_AUD_TOP_INT_POLARITY_MASK_SFT (0x1 << 0)
228 #define RG_DIVCKS_CHG_SFT 0
229 #define RG_DIVCKS_CHG_MASK 0x1
230 #define RG_DIVCKS_CHG_MASK_SFT (0x1 << 0)
233 #define RG_DIVCKS_ON_SFT 0
234 #define RG_DIVCKS_ON_MASK 0x1
235 #define RG_DIVCKS_ON_MASK_SFT (0x1 << 0)
238 #define RG_DIVCKS_PRG_SFT 0
239 #define RG_DIVCKS_PRG_MASK 0x1ff
240 #define RG_DIVCKS_PRG_MASK_SFT (0x1ff << 0)
243 #define RG_DIVCKS_PWD_NCP_SFT 0
244 #define RG_DIVCKS_PWD_NCP_MASK 0x1
245 #define RG_DIVCKS_PWD_NCP_MASK_SFT (0x1 << 0)
248 #define RG_DIVCKS_PWD_NCP_ST_SEL_SFT 0
249 #define RG_DIVCKS_PWD_NCP_ST_SEL_MASK 0x3
250 #define RG_DIVCKS_PWD_NCP_ST_SEL_MASK_SFT (0x3 << 0)
253 #define RG_AUD_TOP_MON_SEL_SFT 0
254 #define RG_AUD_TOP_MON_SEL_MASK 0x7
255 #define RG_AUD_TOP_MON_SEL_MASK_SFT (0x7 << 0)
257 #define RG_AUD_CLK_INT_MON_FLAG_SEL_MASK 0xff
258 #define RG_AUD_CLK_INT_MON_FLAG_SEL_MASK_SFT (0xff << 3)
260 #define RG_AUD_CLK_INT_MON_FLAG_EN_MASK 0x1
261 #define RG_AUD_CLK_INT_MON_FLAG_EN_MASK_SFT (0x1 << 11)
264 #define AUDIO_DIG_ANA_ID_SFT 0
265 #define AUDIO_DIG_ANA_ID_MASK 0xff
266 #define AUDIO_DIG_ANA_ID_MASK_SFT (0xff << 0)
268 #define AUDIO_DIG_DIG_ID_MASK 0xff
269 #define AUDIO_DIG_DIG_ID_MASK_SFT (0xff << 8)
272 #define AUDIO_DIG_ANA_MINOR_REV_SFT 0
273 #define AUDIO_DIG_ANA_MINOR_REV_MASK 0xf
274 #define AUDIO_DIG_ANA_MINOR_REV_MASK_SFT (0xf << 0)
276 #define AUDIO_DIG_ANA_MAJOR_REV_MASK 0xf
277 #define AUDIO_DIG_ANA_MAJOR_REV_MASK_SFT (0xf << 4)
279 #define AUDIO_DIG_DIG_MINOR_REV_MASK 0xf
280 #define AUDIO_DIG_DIG_MINOR_REV_MASK_SFT (0xf << 8)
282 #define AUDIO_DIG_DIG_MAJOR_REV_MASK 0xf
283 #define AUDIO_DIG_DIG_MAJOR_REV_MASK_SFT (0xf << 12)
286 #define AUDIO_DIG_DSN_CBS_SFT 0
287 #define AUDIO_DIG_DSN_CBS_MASK 0x3
288 #define AUDIO_DIG_DSN_CBS_MASK_SFT (0x3 << 0)
290 #define AUDIO_DIG_DSN_BIX_MASK 0x3
291 #define AUDIO_DIG_DSN_BIX_MASK_SFT (0x3 << 2)
293 #define AUDIO_DIG_ESP_MASK 0xff
294 #define AUDIO_DIG_ESP_MASK_SFT (0xff << 8)
297 #define AUDIO_DIG_DSN_FPI_SFT 0
298 #define AUDIO_DIG_DSN_FPI_MASK 0xff
299 #define AUDIO_DIG_DSN_FPI_MASK_SFT (0xff << 0)
303 #define AFE_UL_LR_SWAP_MASK 0x1
304 #define AFE_UL_LR_SWAP_MASK_SFT (0x1 << 15)
306 #define AFE_DL_LR_SWAP_MASK 0x1
307 #define AFE_DL_LR_SWAP_MASK_SFT (0x1 << 14)
308 #define AFE_ON_SFT 0
309 #define AFE_ON_MASK 0x1
310 #define AFE_ON_MASK_SFT (0x1 << 0)
313 #define DL_2_SRC_ON_TMP_CTL_PRE_SFT 0
314 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK 0x1
315 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0)
319 #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK 0x7
320 #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK_SFT (0x7 << 11)
322 #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK 0x7
323 #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK_SFT (0x7 << 8)
325 #define C_TWO_DIGITAL_MIC_CTL_MASK 0x1
326 #define C_TWO_DIGITAL_MIC_CTL_MASK_SFT (0x1 << 7)
330 #define DMIC_LOW_POWER_MODE_CTL_MASK 0x3
331 #define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)
333 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1
334 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)
336 #define UL_LOOP_BACK_MODE_CTL_MASK 0x1
337 #define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)
339 #define UL_SDM_3_LEVEL_CTL_MASK 0x1
340 #define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)
341 #define UL_SRC_ON_TMP_CTL_SFT 0
342 #define UL_SRC_ON_TMP_CTL_MASK 0x1
343 #define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)
347 #define MTKAIF_SINE_ON_MASK 0x1
348 #define MTKAIF_SINE_ON_MASK_SFT (0x1 << 2)
350 #define UL_SINE_ON_MASK 0x1
351 #define UL_SINE_ON_MASK_SFT (0x1 << 1)
352 #define DL_SINE_ON_SFT 0
353 #define DL_SINE_ON_MASK 0x1
354 #define DL_SINE_ON_MASK_SFT (0x1 << 0)
358 #define PDN_AFE_CTL_MASK 0x1
359 #define PDN_AFE_CTL_MASK_SFT (0x1 << 7)
361 #define PDN_DAC_CTL_MASK 0x1
362 #define PDN_DAC_CTL_MASK_SFT (0x1 << 6)
364 #define PDN_ADC_CTL_MASK 0x1
365 #define PDN_ADC_CTL_MASK_SFT (0x1 << 5)
367 #define PDN_I2S_DL_CTL_MASK 0x1
368 #define PDN_I2S_DL_CTL_MASK_SFT (0x1 << 3)
370 #define PWR_CLK_DIS_CTL_MASK 0x1
371 #define PWR_CLK_DIS_CTL_MASK_SFT (0x1 << 2)
373 #define PDN_AFE_TESTMODEL_CTL_MASK 0x1
374 #define PDN_AFE_TESTMODEL_CTL_MASK_SFT (0x1 << 1)
375 #define PDN_RESERVED_SFT 0
376 #define PDN_RESERVED_MASK 0x1
377 #define PDN_RESERVED_MASK_SFT (0x1 << 0)
381 #define AUDIO_SYS_TOP_MON_SWAP_MASK 0x3
382 #define AUDIO_SYS_TOP_MON_SWAP_MASK_SFT (0x3 << 14)
384 #define AUDIO_SYS_TOP_MON_SEL_MASK 0x1f
385 #define AUDIO_SYS_TOP_MON_SEL_MASK_SFT (0x1f << 8)
386 #define AFE_MON_SEL_SFT 0
387 #define AFE_MON_SEL_MASK 0xff
388 #define AFE_MON_SEL_MASK_SFT (0xff << 0)
392 #define CCI_AUD_ANACK_SEL_MASK 0x1
393 #define CCI_AUD_ANACK_SEL_MASK_SFT (0x1 << 15)
395 #define CCI_AUDIO_FIFO_WPTR_MASK 0x7
396 #define CCI_AUDIO_FIFO_WPTR_MASK_SFT (0x7 << 12)
398 #define CCI_SCRAMBLER_CG_EN_MASK 0x1
399 #define CCI_SCRAMBLER_CG_EN_MASK_SFT (0x1 << 11)
401 #define CCI_LCH_INV_MASK 0x1
402 #define CCI_LCH_INV_MASK_SFT (0x1 << 10)
404 #define CCI_RAND_EN_MASK 0x1
405 #define CCI_RAND_EN_MASK_SFT (0x1 << 9)
407 #define CCI_SPLT_SCRMB_CLK_ON_MASK 0x1
408 #define CCI_SPLT_SCRMB_CLK_ON_MASK_SFT (0x1 << 8)
410 #define CCI_SPLT_SCRMB_ON_MASK 0x1
411 #define CCI_SPLT_SCRMB_ON_MASK_SFT (0x1 << 7)
413 #define CCI_AUD_IDAC_TEST_EN_MASK 0x1
414 #define CCI_AUD_IDAC_TEST_EN_MASK_SFT (0x1 << 6)
416 #define CCI_ZERO_PAD_DISABLE_MASK 0x1
417 #define CCI_ZERO_PAD_DISABLE_MASK_SFT (0x1 << 5)
419 #define CCI_AUD_SPLIT_TEST_EN_MASK 0x1
420 #define CCI_AUD_SPLIT_TEST_EN_MASK_SFT (0x1 << 4)
422 #define CCI_AUD_SDM_MUTEL_MASK 0x1
423 #define CCI_AUD_SDM_MUTEL_MASK_SFT (0x1 << 3)
425 #define CCI_AUD_SDM_MUTER_MASK 0x1
426 #define CCI_AUD_SDM_MUTER_MASK_SFT (0x1 << 2)
428 #define CCI_AUD_SDM_7BIT_SEL_MASK 0x1
429 #define CCI_AUD_SDM_7BIT_SEL_MASK_SFT (0x1 << 1)
430 #define CCI_SCRAMBLER_EN_SFT 0
431 #define CCI_SCRAMBLER_EN_MASK 0x1
432 #define CCI_SCRAMBLER_EN_MASK_SFT (0x1 << 0)
436 #define AUD_SDM_TEST_L_MASK 0xff
437 #define AUD_SDM_TEST_L_MASK_SFT (0xff << 8)
438 #define AUD_SDM_TEST_R_SFT 0
439 #define AUD_SDM_TEST_R_MASK 0xff
440 #define AUD_SDM_TEST_R_MASK_SFT (0xff << 0)
444 #define CCI_AUD_DAC_ANA_MUTE_MASK 0x1
445 #define CCI_AUD_DAC_ANA_MUTE_MASK_SFT (0x1 << 7)
447 #define CCI_AUD_DAC_ANA_RSTB_SEL_MASK 0x1
448 #define CCI_AUD_DAC_ANA_RSTB_SEL_MASK_SFT (0x1 << 6)
450 #define CCI_AUDIO_FIFO_CLKIN_INV_MASK 0x1
451 #define CCI_AUDIO_FIFO_CLKIN_INV_MASK_SFT (0x1 << 4)
453 #define CCI_AUDIO_FIFO_ENABLE_MASK 0x1
454 #define CCI_AUDIO_FIFO_ENABLE_MASK_SFT (0x1 << 3)
456 #define CCI_ACD_MODE_MASK 0x1
457 #define CCI_ACD_MODE_MASK_SFT (0x1 << 2)
459 #define CCI_AFIFO_CLK_PWDB_MASK 0x1
460 #define CCI_AFIFO_CLK_PWDB_MASK_SFT (0x1 << 1)
461 #define CCI_ACD_FUNC_RSTB_SFT 0
462 #define CCI_ACD_FUNC_RSTB_MASK 0x1
463 #define CCI_ACD_FUNC_RSTB_MASK_SFT (0x1 << 0)
467 #define SDM_ANA13M_TESTCK_SEL_MASK 0x1
468 #define SDM_ANA13M_TESTCK_SEL_MASK_SFT (0x1 << 15)
470 #define SDM_ANA13M_TESTCK_SRC_SEL_MASK 0x7
471 #define SDM_ANA13M_TESTCK_SRC_SEL_MASK_SFT (0x7 << 12)
473 #define SDM_TESTCK_SRC_SEL_MASK 0x7
474 #define SDM_TESTCK_SRC_SEL_MASK_SFT (0x7 << 8)
476 #define DIGMIC_TESTCK_SRC_SEL_MASK 0x7
477 #define DIGMIC_TESTCK_SRC_SEL_MASK_SFT (0x7 << 4)
478 #define DIGMIC_TESTCK_SEL_SFT 0
479 #define DIGMIC_TESTCK_SEL_MASK 0x1
480 #define DIGMIC_TESTCK_SEL_MASK_SFT (0x1 << 0)
484 #define UL_FIFO_WCLK_INV_MASK 0x1
485 #define UL_FIFO_WCLK_INV_MASK_SFT (0x1 << 8)
487 #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK 0x1
488 #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 6)
490 #define UL_FIFO_WDATA_TESTEN_MASK 0x1
491 #define UL_FIFO_WDATA_TESTEN_MASK_SFT (0x1 << 5)
493 #define UL_FIFO_WDATA_TESTSRC_SEL_MASK 0x1
494 #define UL_FIFO_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 4)
496 #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK 0x1
497 #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK_SFT (0x1 << 3)
498 #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_SFT 0
499 #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK 0x7
500 #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK_SFT (0x7 << 0)
504 #define R_AUD_DAC_POS_LARGE_MONO_MASK 0xff
505 #define R_AUD_DAC_POS_LARGE_MONO_MASK_SFT (0xff << 8)
506 #define R_AUD_DAC_NEG_LARGE_MONO_SFT 0
507 #define R_AUD_DAC_NEG_LARGE_MONO_MASK 0xff
508 #define R_AUD_DAC_NEG_LARGE_MONO_MASK_SFT (0xff << 0)
512 #define R_AUD_DAC_POS_SMALL_MONO_MASK 0xf
513 #define R_AUD_DAC_POS_SMALL_MONO_MASK_SFT (0xf << 12)
515 #define R_AUD_DAC_NEG_SMALL_MONO_MASK 0xf
516 #define R_AUD_DAC_NEG_SMALL_MONO_MASK_SFT (0xf << 8)
518 #define R_AUD_DAC_POS_TINY_MONO_MASK 0x3
519 #define R_AUD_DAC_POS_TINY_MONO_MASK_SFT (0x3 << 6)
521 #define R_AUD_DAC_NEG_TINY_MONO_MASK 0x3
522 #define R_AUD_DAC_NEG_TINY_MONO_MASK_SFT (0x3 << 4)
524 #define R_AUD_DAC_MONO_SEL_MASK 0x1
525 #define R_AUD_DAC_MONO_SEL_MASK_SFT (0x1 << 3)
526 #define R_AUD_DAC_SW_RSTB_SFT 0
527 #define R_AUD_DAC_SW_RSTB_MASK 0x1
528 #define R_AUD_DAC_SW_RSTB_MASK_SFT (0x1 << 0)
532 #define AUD_SCR_OUT_L_MASK 0xff
533 #define AUD_SCR_OUT_L_MASK_SFT (0xff << 8)
534 #define AUD_SCR_OUT_R_SFT 0
535 #define AUD_SCR_OUT_R_MASK 0xff
536 #define AUD_SCR_OUT_R_MASK_SFT (0xff << 0)
540 #define ASYNC_TEST_OUT_BCK_MASK 0x1
541 #define ASYNC_TEST_OUT_BCK_MASK_SFT (0x1 << 15)
543 #define RGS_AUDRCTUNE1READ_MASK 0x1f
544 #define RGS_AUDRCTUNE1READ_MASK_SFT (0x1f << 8)
545 #define RGS_AUDRCTUNE0READ_SFT 0
546 #define RGS_AUDRCTUNE0READ_MASK 0x1f
547 #define RGS_AUDRCTUNE0READ_MASK_SFT (0x1f << 0)
551 #define AFE_RESERVED_MASK 0x7fff
552 #define AFE_RESERVED_MASK_SFT (0x7fff << 1)
553 #define RG_MTKAIF_RXIF_FIFO_INTEN_SFT 0
554 #define RG_MTKAIF_RXIF_FIFO_INTEN_MASK 0x1
555 #define RG_MTKAIF_RXIF_FIFO_INTEN_MASK_SFT (0x1 << 0)
559 #define MTKAIF_RXIF_WR_FULL_STATUS_MASK 0x1
560 #define MTKAIF_RXIF_WR_FULL_STATUS_MASK_SFT (0x1 << 1)
561 #define MTKAIF_RXIF_RD_EMPTY_STATUS_SFT 0
562 #define MTKAIF_RXIF_RD_EMPTY_STATUS_MASK 0x1
563 #define MTKAIF_RXIF_RD_EMPTY_STATUS_MASK_SFT (0x1 << 0)
567 #define MTKAIFTX_V3_SYNC_OUT_MASK 0x1
568 #define MTKAIFTX_V3_SYNC_OUT_MASK_SFT (0x1 << 14)
570 #define MTKAIFTX_V3_SDATA_OUT2_MASK 0x1
571 #define MTKAIFTX_V3_SDATA_OUT2_MASK_SFT (0x1 << 13)
573 #define MTKAIFTX_V3_SDATA_OUT1_MASK 0x1
574 #define MTKAIFTX_V3_SDATA_OUT1_MASK_SFT (0x1 << 12)
575 #define MTKAIF_RXIF_FIFO_STATUS_SFT 0
576 #define MTKAIF_RXIF_FIFO_STATUS_MASK 0xfff
577 #define MTKAIF_RXIF_FIFO_STATUS_MASK_SFT (0xfff << 0)
581 #define MTKAIFRX_V3_SYNC_IN_MASK 0x1
582 #define MTKAIFRX_V3_SYNC_IN_MASK_SFT (0x1 << 14)
584 #define MTKAIFRX_V3_SDATA_IN2_MASK 0x1
585 #define MTKAIFRX_V3_SDATA_IN2_MASK_SFT (0x1 << 13)
587 #define MTKAIFRX_V3_SDATA_IN1_MASK 0x1
588 #define MTKAIFRX_V3_SDATA_IN1_MASK_SFT (0x1 << 12)
590 #define MTKAIF_RXIF_SEARCH_FAIL_FLAG_MASK 0x1
591 #define MTKAIF_RXIF_SEARCH_FAIL_FLAG_MASK_SFT (0x1 << 11)
593 #define MTKAIF_RXIF_INVALID_FLAG_MASK 0x1
594 #define MTKAIF_RXIF_INVALID_FLAG_MASK_SFT (0x1 << 8)
595 #define MTKAIF_RXIF_INVALID_CYCLE_SFT 0
596 #define MTKAIF_RXIF_INVALID_CYCLE_MASK 0xff
597 #define MTKAIF_RXIF_INVALID_CYCLE_MASK_SFT (0xff << 0)
601 #define MTKAIF_TXIF_IN_CH2_MASK 0xff
602 #define MTKAIF_TXIF_IN_CH2_MASK_SFT (0xff << 8)
603 #define MTKAIF_TXIF_IN_CH1_SFT 0
604 #define MTKAIF_TXIF_IN_CH1_MASK 0xff
605 #define MTKAIF_TXIF_IN_CH1_MASK_SFT (0xff << 0)
609 #define MTKAIF_RXIF_OUT_CH2_MASK 0xff
610 #define MTKAIF_RXIF_OUT_CH2_MASK_SFT (0xff << 8)
611 #define MTKAIF_RXIF_OUT_CH1_SFT 0
612 #define MTKAIF_RXIF_OUT_CH1_MASK 0xff
613 #define MTKAIF_RXIF_OUT_CH1_MASK_SFT (0xff << 0)
617 #define RG_MTKAIF_RXIF_CLKINV_MASK 0x1
618 #define RG_MTKAIF_RXIF_CLKINV_MASK_SFT (0x1 << 15)
620 #define RG_MTKAIF_RXIF_PROTOCOL2_MASK 0x1
621 #define RG_MTKAIF_RXIF_PROTOCOL2_MASK_SFT (0x1 << 8)
623 #define RG_MTKAIF_BYPASS_SRC_MODE_MASK 0x3
624 #define RG_MTKAIF_BYPASS_SRC_MODE_MASK_SFT (0x3 << 6)
626 #define RG_MTKAIF_BYPASS_SRC_TEST_MASK 0x1
627 #define RG_MTKAIF_BYPASS_SRC_TEST_MASK_SFT (0x1 << 5)
629 #define RG_MTKAIF_TXIF_PROTOCOL2_MASK 0x1
630 #define RG_MTKAIF_TXIF_PROTOCOL2_MASK_SFT (0x1 << 4)
632 #define RG_MTKAIF_PMIC_TXIF_8TO5_MASK 0x1
633 #define RG_MTKAIF_PMIC_TXIF_8TO5_MASK_SFT (0x1 << 2)
635 #define RG_MTKAIF_LOOPBACK_TEST2_MASK 0x1
636 #define RG_MTKAIF_LOOPBACK_TEST2_MASK_SFT (0x1 << 1)
637 #define RG_MTKAIF_LOOPBACK_TEST1_SFT 0
638 #define RG_MTKAIF_LOOPBACK_TEST1_MASK 0x1
639 #define RG_MTKAIF_LOOPBACK_TEST1_MASK_SFT (0x1 << 0)
643 #define RG_MTKAIF_RXIF_VOICE_MODE_MASK 0xf
644 #define RG_MTKAIF_RXIF_VOICE_MODE_MASK_SFT (0xf << 12)
646 #define RG_MTKAIF_RXIF_DATA_BIT_MASK 0x7
647 #define RG_MTKAIF_RXIF_DATA_BIT_MASK_SFT (0x7 << 8)
649 #define RG_MTKAIF_RXIF_FIFO_RSP_MASK 0x7
650 #define RG_MTKAIF_RXIF_FIFO_RSP_MASK_SFT (0x7 << 4)
652 #define RG_MTKAIF_RXIF_DETECT_ON_MASK 0x1
653 #define RG_MTKAIF_RXIF_DETECT_ON_MASK_SFT (0x1 << 3)
654 #define RG_MTKAIF_RXIF_DATA_MODE_SFT 0
655 #define RG_MTKAIF_RXIF_DATA_MODE_MASK 0x1
656 #define RG_MTKAIF_RXIF_DATA_MODE_MASK_SFT (0x1 << 0)
660 #define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_MASK 0xf
661 #define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_MASK_SFT (0xf << 12)
663 #define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_MASK 0xf
664 #define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_MASK_SFT (0xf << 8)
666 #define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_MASK 0xf
667 #define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_MASK_SFT (0xf << 4)
668 #define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_SFT 0
669 #define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_MASK 0xf
670 #define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_MASK_SFT (0xf << 0)
674 #define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK 0x1
675 #define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK_SFT (0x1 << 12)
676 #define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_SFT 0
677 #define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_MASK 0xfff
678 #define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_MASK_SFT (0xfff << 0)
682 #define RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_MASK 0x1
683 #define RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_MASK_SFT (0x1 << 7)
685 #define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK 0x7
686 #define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK_SFT (0x7 << 4)
688 #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK 0x1
689 #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT (0x1 << 3)
693 #define RG_MTKAIF_SYNC_WORD2_MASK 0x7
694 #define RG_MTKAIF_SYNC_WORD2_MASK_SFT (0x7 << 4)
695 #define RG_MTKAIF_SYNC_WORD1_SFT 0
696 #define RG_MTKAIF_SYNC_WORD1_MASK 0x7
697 #define RG_MTKAIF_SYNC_WORD1_MASK_SFT (0x7 << 0)
701 #define SGEN_AMP_DIV_CH1_CTL_MASK 0xf
702 #define SGEN_AMP_DIV_CH1_CTL_MASK_SFT (0xf << 12)
704 #define SGEN_DAC_EN_CTL_MASK 0x1
705 #define SGEN_DAC_EN_CTL_MASK_SFT (0x1 << 7)
707 #define SGEN_MUTE_SW_CTL_MASK 0x1
708 #define SGEN_MUTE_SW_CTL_MASK_SFT (0x1 << 6)
710 #define R_AUD_SDM_MUTE_L_MASK 0x1
711 #define R_AUD_SDM_MUTE_L_MASK_SFT (0x1 << 5)
713 #define R_AUD_SDM_MUTE_R_MASK 0x1
714 #define R_AUD_SDM_MUTE_R_MASK_SFT (0x1 << 4)
718 #define C_SGEN_RCH_INV_5BIT_MASK 0x1
719 #define C_SGEN_RCH_INV_5BIT_MASK_SFT (0x1 << 15)
721 #define C_SGEN_RCH_INV_8BIT_MASK 0x1
722 #define C_SGEN_RCH_INV_8BIT_MASK_SFT (0x1 << 14)
723 #define SGEN_FREQ_DIV_CH1_CTL_SFT 0
724 #define SGEN_FREQ_DIV_CH1_CTL_MASK 0x1f
725 #define SGEN_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 0)
729 #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK 0x1
730 #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK_SFT (0x1 << 5)
732 #define RG_UL_ASYNC_FIFO_SOFT_RST_MASK 0x1
733 #define RG_UL_ASYNC_FIFO_SOFT_RST_MASK_SFT (0x1 << 4)
735 #define RG_AMIC_UL_ADC_CLK_SEL_MASK 0x1
736 #define RG_AMIC_UL_ADC_CLK_SEL_MASK_SFT (0x1 << 1)
740 #define DCCLK_DIV_MASK 0x7ff
741 #define DCCLK_DIV_MASK_SFT (0x7ff << 5)
743 #define DCCLK_INV_MASK 0x1
744 #define DCCLK_INV_MASK_SFT (0x1 << 4)
746 #define DCCLK_PDN_MASK 0x1
747 #define DCCLK_PDN_MASK_SFT (0x1 << 1)
748 #define DCCLK_GEN_ON_SFT 0
749 #define DCCLK_GEN_ON_MASK 0x1
750 #define DCCLK_GEN_ON_MASK_SFT (0x1 << 0)
754 #define RESYNC_SRC_SEL_MASK 0x3
755 #define RESYNC_SRC_SEL_MASK_SFT (0x3 << 10)
757 #define RESYNC_SRC_CK_INV_MASK 0x1
758 #define RESYNC_SRC_CK_INV_MASK_SFT (0x1 << 9)
760 #define DCCLK_RESYNC_BYPASS_MASK 0x1
761 #define DCCLK_RESYNC_BYPASS_MASK_SFT (0x1 << 8)
763 #define DCCLK_PHASE_SEL_MASK 0xf
764 #define DCCLK_PHASE_SEL_MASK_SFT (0xf << 4)
768 #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK 0x1
769 #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT (0x1 << 15)
771 #define RG_AUD_PAD_TOP_PHASE_MODE2_MASK 0x7f
772 #define RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT (0x7f << 8)
774 #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK 0x1
775 #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT (0x1 << 7)
776 #define RG_AUD_PAD_TOP_PHASE_MODE_SFT 0
777 #define RG_AUD_PAD_TOP_PHASE_MODE_MASK 0x7f
778 #define RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT (0x7f << 0)
782 #define RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK 0x7
783 #define RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK_SFT (0x7 << 12)
785 #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK 0x1
786 #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK_SFT (0x1 << 11)
788 #define RG_AUD_PAD_TOP_TX_FIFO_ON_MASK 0x1
789 #define RG_AUD_PAD_TOP_TX_FIFO_ON_MASK_SFT (0x1 << 8)
792 #define ADDA_AUD_PAD_TOP_MON_SFT 0
793 #define ADDA_AUD_PAD_TOP_MON_MASK 0xffff
794 #define ADDA_AUD_PAD_TOP_MON_MASK_SFT (0xffff << 0)
797 #define ADDA_AUD_PAD_TOP_MON1_SFT 0
798 #define ADDA_AUD_PAD_TOP_MON1_MASK 0xffff
799 #define ADDA_AUD_PAD_TOP_MON1_MASK_SFT (0xffff << 0)
803 #define NLE_RCH_HPGAIN_SEL_MASK 0x1
804 #define NLE_RCH_HPGAIN_SEL_MASK_SFT (0x1 << 10)
806 #define NLE_RCH_CH_SEL_MASK 0x1
807 #define NLE_RCH_CH_SEL_MASK_SFT (0x1 << 9)
809 #define NLE_RCH_ON_MASK 0x1
810 #define NLE_RCH_ON_MASK_SFT (0x1 << 8)
812 #define NLE_LCH_HPGAIN_SEL_MASK 0x1
813 #define NLE_LCH_HPGAIN_SEL_MASK_SFT (0x1 << 2)
815 #define NLE_LCH_CH_SEL_MASK 0x1
816 #define NLE_LCH_CH_SEL_MASK_SFT (0x1 << 1)
817 #define NLE_LCH_ON_SFT 0
818 #define NLE_LCH_ON_MASK 0x1
819 #define NLE_LCH_ON_MASK_SFT (0x1 << 0)
822 #define NLE_MONITOR_SFT 0
823 #define NLE_MONITOR_MASK 0x3fff
824 #define NLE_MONITOR_MASK_SFT (0x3fff << 0)
827 #define CK_CG_EN_MON_SFT 0
828 #define CK_CG_EN_MON_MASK 0x3f
829 #define CK_CG_EN_MON_MASK_SFT (0x3f << 0)
833 #define PDN_VOW_MASK 0x1
834 #define PDN_VOW_MASK_SFT (0x1 << 15)
836 #define VOW_1P6M_800K_SEL_MASK 0x1
837 #define VOW_1P6M_800K_SEL_MASK_SFT (0x1 << 14)
839 #define VOW_DIGMIC_ON_MASK 0x1
840 #define VOW_DIGMIC_ON_MASK_SFT (0x1 << 13)
842 #define VOW_CK_DIV_RST_MASK 0x1
843 #define VOW_CK_DIV_RST_MASK_SFT (0x1 << 12)
845 #define VOW_ON_MASK 0x1
846 #define VOW_ON_MASK_SFT (0x1 << 11)
848 #define VOW_DIGMIC_CK_PHASE_SEL_MASK 0x7
849 #define VOW_DIGMIC_CK_PHASE_SEL_MASK_SFT (0x7 << 8)
851 #define MAIN_DMIC_CK_VOW_SEL_MASK 0x1
852 #define MAIN_DMIC_CK_VOW_SEL_MASK_SFT (0x1 << 7)
854 #define VOW_SDM_3_LEVEL_MASK 0x1
855 #define VOW_SDM_3_LEVEL_MASK_SFT (0x1 << 6)
857 #define VOW_LOOP_BACK_MODE_MASK 0x1
858 #define VOW_LOOP_BACK_MODE_MASK_SFT (0x1 << 5)
860 #define VOW_INTR_SOURCE_SEL_MASK 0x1
861 #define VOW_INTR_SOURCE_SEL_MASK_SFT (0x1 << 4)
863 #define VOW_INTR_CLR_MASK 0x1
864 #define VOW_INTR_CLR_MASK_SFT (0x1 << 3)
866 #define S_N_VALUE_RST_MASK 0x1
867 #define S_N_VALUE_RST_MASK_SFT (0x1 << 2)
869 #define SAMPLE_BASE_MODE_MASK 0x1
870 #define SAMPLE_BASE_MODE_MASK_SFT (0x1 << 1)
871 #define VOW_INTR_FLAG_SFT 0
872 #define VOW_INTR_FLAG_MASK 0x1
873 #define VOW_INTR_FLAG_MASK_SFT (0x1 << 0)
876 #define AMPREF_SFT 0
877 #define AMPREF_MASK 0xffff
878 #define AMPREF_MASK_SFT (0xffff << 0)
881 #define TIMERINI_SFT 0
882 #define TIMERINI_MASK 0xffff
883 #define TIMERINI_MASK_SFT (0xffff << 0)
887 #define B_DEFAULT_MASK 0x7
888 #define B_DEFAULT_MASK_SFT (0x7 << 12)
890 #define A_DEFAULT_MASK 0x7
891 #define A_DEFAULT_MASK_SFT (0x7 << 8)
893 #define B_INI_MASK 0x7
894 #define B_INI_MASK_SFT (0x7 << 4)
895 #define A_INI_SFT 0
896 #define A_INI_MASK 0x7
897 #define A_INI_MASK_SFT (0x7 << 0)
901 #define K_BETA_RISE_MASK 0xf
902 #define K_BETA_RISE_MASK_SFT (0xf << 12)
904 #define K_BETA_FALL_MASK 0xf
905 #define K_BETA_FALL_MASK_SFT (0xf << 8)
907 #define K_ALPHA_RISE_MASK 0xf
908 #define K_ALPHA_RISE_MASK_SFT (0xf << 4)
909 #define K_ALPHA_FALL_SFT 0
910 #define K_ALPHA_FALL_MASK 0xf
911 #define K_ALPHA_FALL_MASK_SFT (0xf << 0)
915 #define VOW_TXIF_SCK_INV_MASK 0x1
916 #define VOW_TXIF_SCK_INV_MASK_SFT (0x1 << 15)
918 #define VOW_ADC_TESTCK_SRC_SEL_MASK 0x7
919 #define VOW_ADC_TESTCK_SRC_SEL_MASK_SFT (0x7 << 12)
921 #define VOW_ADC_TESTCK_SEL_MASK 0x1
922 #define VOW_ADC_TESTCK_SEL_MASK_SFT (0x1 << 11)
924 #define VOW_ADC_CLK_INV_MASK 0x1
925 #define VOW_ADC_CLK_INV_MASK_SFT (0x1 << 10)
927 #define VOW_TXIF_MONO_MASK 0x1
928 #define VOW_TXIF_MONO_MASK_SFT (0x1 << 9)
930 #define VOW_TXIF_SCK_DIV_MASK 0x1f
931 #define VOW_TXIF_SCK_DIV_MASK_SFT (0x1f << 4)
932 #define K_GAMMA_SFT 0
933 #define K_GAMMA_MASK 0xf
934 #define K_GAMMA_MASK_SFT (0xf << 0)
937 #define N_MIN_SFT 0
938 #define N_MIN_MASK 0xffff
939 #define N_MIN_MASK_SFT (0xffff << 0)
943 #define RG_WINDOW_SIZE_SEL_MASK 0x1
944 #define RG_WINDOW_SIZE_SEL_MASK_SFT (0x1 << 12)
946 #define RG_FLR_BYPASS_MASK 0x1
947 #define RG_FLR_BYPASS_MASK_SFT (0x1 << 11)
949 #define RG_FLR_RATIO_MASK 0x7
950 #define RG_FLR_RATIO_MASK_SFT (0x7 << 8)
952 #define RG_BUCK_DVFS_DONE_SW_CTL_MASK 0x1
953 #define RG_BUCK_DVFS_DONE_SW_CTL_MASK_SFT (0x1 << 7)
955 #define RG_BUCK_DVFS_DONE_HW_MODE_MASK 0x1
956 #define RG_BUCK_DVFS_DONE_HW_MODE_MASK_SFT (0x1 << 6)
957 #define RG_BUCK_DVFS_HW_CNT_THR_SFT 0
958 #define RG_BUCK_DVFS_HW_CNT_THR_MASK 0x3f
959 #define RG_BUCK_DVFS_HW_CNT_THR_MASK_SFT (0x3f << 0)
962 #define VOW_DOWNCNT_SFT 0
963 #define VOW_DOWNCNT_MASK 0xffff
964 #define VOW_DOWNCNT_MASK_SFT (0xffff << 0)
968 #define K_TMP_MON_MASK 0xf
969 #define K_TMP_MON_MASK_SFT (0xf << 10)
971 #define SLT_COUNTER_MON_MASK 0x7
972 #define SLT_COUNTER_MON_MASK_SFT (0x7 << 7)
974 #define VOW_B_MASK 0x7
975 #define VOW_B_MASK_SFT (0x7 << 4)
977 #define VOW_A_MASK 0x7
978 #define VOW_A_MASK_SFT (0x7 << 1)
979 #define SECOND_CNT_START_SFT 0
980 #define SECOND_CNT_START_MASK 0x1
981 #define SECOND_CNT_START_MASK_SFT (0x1 << 0)
984 #define VOW_S_L_SFT 0
985 #define VOW_S_L_MASK 0xffff
986 #define VOW_S_L_MASK_SFT (0xffff << 0)
989 #define VOW_S_H_SFT 0
990 #define VOW_S_H_MASK 0xffff
991 #define VOW_S_H_MASK_SFT (0xffff << 0)
994 #define VOW_N_L_SFT 0
995 #define VOW_N_L_MASK 0xffff
996 #define VOW_N_L_MASK_SFT (0xffff << 0)
999 #define VOW_N_H_SFT 0
1000 #define VOW_N_H_MASK 0xffff
1001 #define VOW_N_H_MASK_SFT (0xffff << 0)
1005 #define VOW_SN_INI_CFG_EN_MASK 0x1
1006 #define VOW_SN_INI_CFG_EN_MASK_SFT (0x1 << 15)
1007 #define VOW_SN_INI_CFG_VAL_SFT 0
1008 #define VOW_SN_INI_CFG_VAL_MASK 0x7fff
1009 #define VOW_SN_INI_CFG_VAL_MASK_SFT (0x7fff << 0)
1013 #define VOW_TGEN_EN_MASK 0x1
1014 #define VOW_TGEN_EN_MASK_SFT (0x1 << 15)
1016 #define VOW_TGEN_MUTE_SW_MASK 0x1
1017 #define VOW_TGEN_MUTE_SW_MASK_SFT (0x1 << 14)
1018 #define VOW_TGEN_FREQ_DIV_SFT 0
1019 #define VOW_TGEN_FREQ_DIV_MASK 0x3fff
1020 #define VOW_TGEN_FREQ_DIV_MASK_SFT (0x3fff << 0)
1024 #define BUCK_DVFS_DONE_MASK 0x1
1025 #define BUCK_DVFS_DONE_MASK_SFT (0x1 << 15)
1027 #define VOW_32K_MODE_MASK 0x1
1028 #define VOW_32K_MODE_MASK_SFT (0x1 << 13)
1030 #define RG_BUCK_CLK_DIV_MASK 0x1f
1031 #define RG_BUCK_CLK_DIV_MASK_SFT (0x1f << 8)
1033 #define RG_A1P6M_EN_SEL_MASK 0x1
1034 #define RG_A1P6M_EN_SEL_MASK_SFT (0x1 << 7)
1036 #define VOW_CLK_SEL_MASK 0x1
1037 #define VOW_CLK_SEL_MASK_SFT (0x1 << 6)
1039 #define VOW_INTR_SW_MODE_MASK 0x1
1040 #define VOW_INTR_SW_MODE_MASK_SFT (0x1 << 5)
1042 #define VOW_INTR_SW_VAL_MASK 0x1
1043 #define VOW_INTR_SW_VAL_MASK_SFT (0x1 << 4)
1045 #define VOW_CIC_MODE_SEL_MASK 0x3
1046 #define VOW_CIC_MODE_SEL_MASK_SFT (0x3 << 2)
1047 #define RG_VOW_POSDIV_SFT 0
1048 #define RG_VOW_POSDIV_MASK 0x3
1049 #define RG_VOW_POSDIV_MASK_SFT (0x3 << 0)
1053 #define VOW_HPF_DC_TEST_MASK 0xf
1054 #define VOW_HPF_DC_TEST_MASK_SFT (0xf << 12)
1056 #define VOW_IRQ_LATCH_SNR_EN_MASK 0x1
1057 #define VOW_IRQ_LATCH_SNR_EN_MASK_SFT (0x1 << 10)
1059 #define VOW_DMICCLK_PDN_MASK 0x1
1060 #define VOW_DMICCLK_PDN_MASK_SFT (0x1 << 9)
1062 #define VOW_POSDIVCLK_PDN_MASK 0x1
1063 #define VOW_POSDIVCLK_PDN_MASK_SFT (0x1 << 8)
1065 #define RG_BASELINE_ALPHA_ORDER_MASK 0xf
1066 #define RG_BASELINE_ALPHA_ORDER_MASK_SFT (0xf << 4)
1068 #define RG_MTKAIF_HPF_BYPASS_MASK 0x1
1069 #define RG_MTKAIF_HPF_BYPASS_MASK_SFT (0x1 << 2)
1071 #define RG_SNRDET_HPF_BYPASS_MASK 0x1
1072 #define RG_SNRDET_HPF_BYPASS_MASK_SFT (0x1 << 1)
1073 #define RG_HPF_ON_SFT 0
1074 #define RG_HPF_ON_MASK 0x1
1075 #define RG_HPF_ON_MASK_SFT (0x1 << 0)
1079 #define RG_PERIODIC_EN_MASK 0x1
1080 #define RG_PERIODIC_EN_MASK_SFT (0x1 << 15)
1082 #define RG_PERIODIC_CNT_CLR_MASK 0x1
1083 #define RG_PERIODIC_CNT_CLR_MASK_SFT (0x1 << 14)
1084 #define RG_PERIODIC_CNT_PERIOD_SFT 0
1085 #define RG_PERIODIC_CNT_PERIOD_MASK 0x3fff
1086 #define RG_PERIODIC_CNT_PERIOD_MASK_SFT (0x3fff << 0)
1090 #define RG_PERIODIC_CNT_SET_MASK 0x1
1091 #define RG_PERIODIC_CNT_SET_MASK_SFT (0x1 << 15)
1093 #define RG_PERIODIC_CNT_PAUSE_MASK 0x1
1094 #define RG_PERIODIC_CNT_PAUSE_MASK_SFT (0x1 << 14)
1095 #define RG_PERIODIC_CNT_SET_VALUE_SFT 0
1096 #define RG_PERIODIC_CNT_SET_VALUE_MASK 0x3fff
1097 #define RG_PERIODIC_CNT_SET_VALUE_MASK_SFT (0x3fff << 0)
1101 #define AUDPREAMPLON_PERIODIC_MODE_MASK 0x1
1102 #define AUDPREAMPLON_PERIODIC_MODE_MASK_SFT (0x1 << 15)
1104 #define AUDPREAMPLON_PERIODIC_INVERSE_MASK 0x1
1105 #define AUDPREAMPLON_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
1106 #define AUDPREAMPLON_PERIODIC_ON_CYCLE_SFT 0
1107 #define AUDPREAMPLON_PERIODIC_ON_CYCLE_MASK 0x3fff
1108 #define AUDPREAMPLON_PERIODIC_ON_CYCLE_MASK_SFT (0x3fff << 0)
1112 #define AUDPREAMPLDCPRECHARGE_PERIODIC_MODE_MASK 0x1
1113 #define AUDPREAMPLDCPRECHARGE_PERIODIC_MODE_MASK_SFT (0x1 << 15)
1115 #define AUDPREAMPLDCPRECHARGE_PERIODIC_INVERSE_MASK 0x1
1116 #define AUDPREAMPLDCPRECHARGE_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
1117 #define AUDPREAMPLDCPRECHARGE_PERIODIC_ON_CYCLE_SFT 0
1118 #define AUDPREAMPLDCPRECHARGE_PERIODIC_ON_CYCLE_MASK 0x3fff
1119 #define AUDPREAMPLDCPRECHARGE_PERIODIC_ON_CYCLE_MASK_SFT (0x3fff << 0)
1123 #define AUDADCLPWRUP_PERIODIC_MODE_MASK 0x1
1124 #define AUDADCLPWRUP_PERIODIC_MODE_MASK_SFT (0x1 << 15)
1126 #define AUDADCLPWRUP_PERIODIC_INVERSE_MASK 0x1
1127 #define AUDADCLPWRUP_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
1128 #define AUDADCLPWRUP_PERIODIC_ON_CYCLE_SFT 0
1129 #define AUDADCLPWRUP_PERIODIC_ON_CYCLE_MASK 0x3fff
1130 #define AUDADCLPWRUP_PERIODIC_ON_CYCLE_MASK_SFT (0x3fff << 0)
1134 #define AUDGLBVOWLPWEN_PERIODIC_MODE_MASK 0x1
1135 #define AUDGLBVOWLPWEN_PERIODIC_MODE_MASK_SFT (0x1 << 15)
1137 #define AUDGLBVOWLPWEN_PERIODIC_INVERSE_MASK 0x1
1138 #define AUDGLBVOWLPWEN_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
1139 #define AUDGLBVOWLPWEN_PERIODIC_ON_CYCLE_SFT 0
1140 #define AUDGLBVOWLPWEN_PERIODIC_ON_CYCLE_MASK 0x3fff
1141 #define AUDGLBVOWLPWEN_PERIODIC_ON_CYCLE_MASK_SFT (0x3fff << 0)
1145 #define AUDDIGMICEN_PERIODIC_MODE_MASK 0x1
1146 #define AUDDIGMICEN_PERIODIC_MODE_MASK_SFT (0x1 << 15)
1148 #define AUDDIGMICEN_PERIODIC_INVERSE_MASK 0x1
1149 #define AUDDIGMICEN_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
1150 #define AUDDIGMICEN_PERIODIC_ON_CYCLE_SFT 0
1151 #define AUDDIGMICEN_PERIODIC_ON_CYCLE_MASK 0x3fff
1152 #define AUDDIGMICEN_PERIODIC_ON_CYCLE_MASK_SFT (0x3fff << 0)
1156 #define AUDPWDBMICBIAS0_PERIODIC_MODE_MASK 0x1
1157 #define AUDPWDBMICBIAS0_PERIODIC_MODE_MASK_SFT (0x1 << 15)
1159 #define AUDPWDBMICBIAS0_PERIODIC_INVERSE_MASK 0x1
1160 #define AUDPWDBMICBIAS0_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
1161 #define AUDPWDBMICBIAS0_PERIODIC_ON_CYCLE_SFT 0
1162 #define AUDPWDBMICBIAS0_PERIODIC_ON_CYCLE_MASK 0x3fff
1163 #define AUDPWDBMICBIAS0_PERIODIC_ON_CYCLE_MASK_SFT (0x3fff << 0)
1167 #define AUDPWDBMICBIAS1_PERIODIC_MODE_MASK 0x1
1168 #define AUDPWDBMICBIAS1_PERIODIC_MODE_MASK_SFT (0x1 << 15)
1170 #define AUDPWDBMICBIAS1_PERIODIC_INVERSE_MASK 0x1
1171 #define AUDPWDBMICBIAS1_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
1172 #define AUDPWDBMICBIAS1_PERIODIC_ON_CYCLE_SFT 0
1173 #define AUDPWDBMICBIAS1_PERIODIC_ON_CYCLE_MASK 0x3fff
1174 #define AUDPWDBMICBIAS1_PERIODIC_ON_CYCLE_MASK_SFT (0x3fff << 0)
1178 #define XO_VOW_CK_EN_PERIODIC_MODE_MASK 0x1
1179 #define XO_VOW_CK_EN_PERIODIC_MODE_MASK_SFT (0x1 << 15)
1181 #define XO_VOW_CK_EN_PERIODIC_INVERSE_MASK 0x1
1182 #define XO_VOW_CK_EN_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
1183 #define XO_VOW_CK_EN_PERIODIC_ON_CYCLE_SFT 0
1184 #define XO_VOW_CK_EN_PERIODIC_ON_CYCLE_MASK 0x3fff
1185 #define XO_VOW_CK_EN_PERIODIC_ON_CYCLE_MASK_SFT (0x3fff << 0)
1189 #define AUDGLB_PWRDN_PERIODIC_MODE_MASK 0x1
1190 #define AUDGLB_PWRDN_PERIODIC_MODE_MASK_SFT (0x1 << 15)
1192 #define AUDGLB_PWRDN_PERIODIC_INVERSE_MASK 0x1
1193 #define AUDGLB_PWRDN_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
1194 #define AUDGLB_PWRDN_PERIODIC_ON_CYCLE_SFT 0
1195 #define AUDGLB_PWRDN_PERIODIC_ON_CYCLE_MASK 0x3fff
1196 #define AUDGLB_PWRDN_PERIODIC_ON_CYCLE_MASK_SFT (0x3fff << 0)
1200 #define VOW_ON_PERIODIC_MODE_MASK 0x1
1201 #define VOW_ON_PERIODIC_MODE_MASK_SFT (0x1 << 15)
1203 #define VOW_ON_PERIODIC_INVERSE_MASK 0x1
1204 #define VOW_ON_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
1205 #define VOW_ON_PERIODIC_ON_CYCLE_SFT 0
1206 #define VOW_ON_PERIODIC_ON_CYCLE_MASK 0x3fff
1207 #define VOW_ON_PERIODIC_ON_CYCLE_MASK_SFT (0x3fff << 0)
1211 #define DMIC_ON_PERIODIC_MODE_MASK 0x1
1212 #define DMIC_ON_PERIODIC_MODE_MASK_SFT (0x1 << 15)
1214 #define DMIC_ON_PERIODIC_INVERSE_MASK 0x1
1215 #define DMIC_ON_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
1216 #define DMIC_ON_PERIODIC_ON_CYCLE_SFT 0
1217 #define DMIC_ON_PERIODIC_ON_CYCLE_MASK 0x3fff
1218 #define DMIC_ON_PERIODIC_ON_CYCLE_MASK_SFT (0x3fff << 0)
1222 #define PDN_VOW_F32K_CK_MASK 0x1
1223 #define PDN_VOW_F32K_CK_MASK_SFT (0x1 << 15)
1224 #define AUDPREAMPLON_PERIODIC_OFF_CYCLE_SFT 0
1225 #define AUDPREAMPLON_PERIODIC_OFF_CYCLE_MASK 0x3fff
1226 #define AUDPREAMPLON_PERIODIC_OFF_CYCLE_MASK_SFT (0x3fff << 0)
1230 #define VOW_SNRDET_PERIODIC_CFG_MASK 0x1
1231 #define VOW_SNRDET_PERIODIC_CFG_MASK_SFT (0x1 << 15)
1232 #define AUDPREAMPLDCPRECHARGE_PERIODIC_OFF_CYCLE_SFT 0
1233 #define AUDPREAMPLDCPRECHARGE_PERIODIC_OFF_CYCLE_MASK 0x3fff
1234 #define AUDPREAMPLDCPRECHARGE_PERIODIC_OFF_CYCLE_MASK_SFT (0x3fff << 0)
1237 #define AUDADCLPWRUP_PERIODIC_OFF_CYCLE_SFT 0
1238 #define AUDADCLPWRUP_PERIODIC_OFF_CYCLE_MASK 0x3fff
1239 #define AUDADCLPWRUP_PERIODIC_OFF_CYCLE_MASK_SFT (0x3fff << 0)
1242 #define AUDGLBVOWLPWEN_PERIODIC_OFF_CYCLE_SFT 0
1243 #define AUDGLBVOWLPWEN_PERIODIC_OFF_CYCLE_MASK 0x3fff
1244 #define AUDGLBVOWLPWEN_PERIODIC_OFF_CYCLE_MASK_SFT (0x3fff << 0)
1247 #define AUDDIGMICEN_PERIODIC_OFF_CYCLE_SFT 0
1248 #define AUDDIGMICEN_PERIODIC_OFF_CYCLE_MASK 0x3fff
1249 #define AUDDIGMICEN_PERIODIC_OFF_CYCLE_MASK_SFT (0x3fff << 0)
1252 #define AUDPWDBMICBIAS0_PERIODIC_OFF_CYCLE_SFT 0
1253 #define AUDPWDBMICBIAS0_PERIODIC_OFF_CYCLE_MASK 0x3fff
1254 #define AUDPWDBMICBIAS0_PERIODIC_OFF_CYCLE_MASK_SFT (0x3fff << 0)
1257 #define AUDPWDBMICBIAS1_PERIODIC_OFF_CYCLE_SFT 0
1258 #define AUDPWDBMICBIAS1_PERIODIC_OFF_CYCLE_MASK 0x3fff
1259 #define AUDPWDBMICBIAS1_PERIODIC_OFF_CYCLE_MASK_SFT (0x3fff << 0)
1263 #define CLKSQ_EN_VOW_PERIODIC_MODE_MASK 0x1
1264 #define CLKSQ_EN_VOW_PERIODIC_MODE_MASK_SFT (0x1 << 15)
1265 #define XO_VOW_CK_EN_PERIODIC_OFF_CYCLE_SFT 0
1266 #define XO_VOW_CK_EN_PERIODIC_OFF_CYCLE_MASK 0x3fff
1267 #define XO_VOW_CK_EN_PERIODIC_OFF_CYCLE_MASK_SFT (0x3fff << 0)
1270 #define AUDGLB_PWRDN_PERIODIC_OFF_CYCLE_SFT 0
1271 #define AUDGLB_PWRDN_PERIODIC_OFF_CYCLE_MASK 0x3fff
1272 #define AUDGLB_PWRDN_PERIODIC_OFF_CYCLE_MASK_SFT (0x3fff << 0)
1275 #define VOW_ON_PERIODIC_OFF_CYCLE_SFT 0
1276 #define VOW_ON_PERIODIC_OFF_CYCLE_MASK 0x3fff
1277 #define VOW_ON_PERIODIC_OFF_CYCLE_MASK_SFT (0x3fff << 0)
1280 #define DMIC_ON_PERIODIC_OFF_CYCLE_SFT 0
1281 #define DMIC_ON_PERIODIC_OFF_CYCLE_MASK 0x3fff
1282 #define DMIC_ON_PERIODIC_OFF_CYCLE_MASK_SFT (0x3fff << 0)
1285 #define VOW_PERIODIC_MON_SFT 0
1286 #define VOW_PERIODIC_MON_MASK 0xffff
1287 #define VOW_PERIODIC_MON_MASK_SFT (0xffff << 0)
1290 #define VOW_PERIODIC_COUNT_MON_SFT 0
1291 #define VOW_PERIODIC_COUNT_MON_MASK 0xffff
1292 #define VOW_PERIODIC_COUNT_MON_MASK_SFT (0xffff << 0)
1295 #define AUDENC_ANA_ID_SFT 0
1296 #define AUDENC_ANA_ID_MASK 0xff
1297 #define AUDENC_ANA_ID_MASK_SFT (0xff << 0)
1299 #define AUDENC_DIG_ID_MASK 0xff
1300 #define AUDENC_DIG_ID_MASK_SFT (0xff << 8)
1303 #define AUDENC_ANA_MINOR_REV_SFT 0
1304 #define AUDENC_ANA_MINOR_REV_MASK 0xf
1305 #define AUDENC_ANA_MINOR_REV_MASK_SFT (0xf << 0)
1307 #define AUDENC_ANA_MAJOR_REV_MASK 0xf
1308 #define AUDENC_ANA_MAJOR_REV_MASK_SFT (0xf << 4)
1310 #define AUDENC_DIG_MINOR_REV_MASK 0xf
1311 #define AUDENC_DIG_MINOR_REV_MASK_SFT (0xf << 8)
1313 #define AUDENC_DIG_MAJOR_REV_MASK 0xf
1314 #define AUDENC_DIG_MAJOR_REV_MASK_SFT (0xf << 12)
1317 #define AUDENC_DSN_CBS_SFT 0
1318 #define AUDENC_DSN_CBS_MASK 0x3
1319 #define AUDENC_DSN_CBS_MASK_SFT (0x3 << 0)
1321 #define AUDENC_DSN_BIX_MASK 0x3
1322 #define AUDENC_DSN_BIX_MASK_SFT (0x3 << 2)
1324 #define AUDENC_DSN_ESP_MASK 0xff
1325 #define AUDENC_DSN_ESP_MASK_SFT (0xff << 8)
1328 #define AUDENC_DSN_FPI_SFT 0
1329 #define AUDENC_DSN_FPI_MASK 0xff
1330 #define AUDENC_DSN_FPI_MASK_SFT (0xff << 0)
1333 #define RG_AUDPREAMPLON_SFT 0
1334 #define RG_AUDPREAMPLON_MASK 0x1
1335 #define RG_AUDPREAMPLON_MASK_SFT (0x1 << 0)
1337 #define RG_AUDPREAMPLDCCEN_MASK 0x1
1338 #define RG_AUDPREAMPLDCCEN_MASK_SFT (0x1 << 1)
1340 #define RG_AUDPREAMPLDCPRECHARGE_MASK 0x1
1341 #define RG_AUDPREAMPLDCPRECHARGE_MASK_SFT (0x1 << 2)
1343 #define RG_AUDPREAMPLPGATEST_MASK 0x1
1344 #define RG_AUDPREAMPLPGATEST_MASK_SFT (0x1 << 3)
1346 #define RG_AUDPREAMPLVSCALE_MASK 0x3
1347 #define RG_AUDPREAMPLVSCALE_MASK_SFT (0x3 << 4)
1349 #define RG_AUDPREAMPLINPUTSEL_MASK 0x3
1350 #define RG_AUDPREAMPLINPUTSEL_MASK_SFT (0x3 << 6)
1352 #define RG_AUDPREAMPLGAIN_MASK 0x7
1353 #define RG_AUDPREAMPLGAIN_MASK_SFT (0x7 << 8)
1355 #define RG_AUDADCLPWRUP_MASK 0x1
1356 #define RG_AUDADCLPWRUP_MASK_SFT (0x1 << 12)
1358 #define RG_AUDADCLINPUTSEL_MASK 0x3
1359 #define RG_AUDADCLINPUTSEL_MASK_SFT (0x3 << 13)
1362 #define RG_AUDPREAMPRON_SFT 0
1363 #define RG_AUDPREAMPRON_MASK 0x1
1364 #define RG_AUDPREAMPRON_MASK_SFT (0x1 << 0)
1366 #define RG_AUDPREAMPRDCCEN_MASK 0x1
1367 #define RG_AUDPREAMPRDCCEN_MASK_SFT (0x1 << 1)
1369 #define RG_AUDPREAMPRDCPRECHARGE_MASK 0x1
1370 #define RG_AUDPREAMPRDCPRECHARGE_MASK_SFT (0x1 << 2)
1372 #define RG_AUDPREAMPRPGATEST_MASK 0x1
1373 #define RG_AUDPREAMPRPGATEST_MASK_SFT (0x1 << 3)
1375 #define RG_AUDPREAMPRVSCALE_MASK 0x3
1376 #define RG_AUDPREAMPRVSCALE_MASK_SFT (0x3 << 4)
1378 #define RG_AUDPREAMPRINPUTSEL_MASK 0x3
1379 #define RG_AUDPREAMPRINPUTSEL_MASK_SFT (0x3 << 6)
1381 #define RG_AUDPREAMPRGAIN_MASK 0x7
1382 #define RG_AUDPREAMPRGAIN_MASK_SFT (0x7 << 8)
1384 #define RG_AUDIO_VOW_EN_MASK 0x1
1385 #define RG_AUDIO_VOW_EN_MASK_SFT (0x1 << 11)
1387 #define RG_AUDADCRPWRUP_MASK 0x1
1388 #define RG_AUDADCRPWRUP_MASK_SFT (0x1 << 12)
1390 #define RG_AUDADCRINPUTSEL_MASK 0x3
1391 #define RG_AUDADCRINPUTSEL_MASK_SFT (0x3 << 13)
1393 #define RG_CLKSQ_EN_VOW_MASK 0x1
1394 #define RG_CLKSQ_EN_VOW_MASK_SFT (0x1 << 15)
1397 #define RG_AUDULHALFBIAS_SFT 0
1398 #define RG_AUDULHALFBIAS_MASK 0x1
1399 #define RG_AUDULHALFBIAS_MASK_SFT (0x1 << 0)
1401 #define RG_AUDGLBVOWLPWEN_MASK 0x1
1402 #define RG_AUDGLBVOWLPWEN_MASK_SFT (0x1 << 1)
1404 #define RG_AUDPREAMPLPEN_MASK 0x1
1405 #define RG_AUDPREAMPLPEN_MASK_SFT (0x1 << 2)
1407 #define RG_AUDADC1STSTAGELPEN_MASK 0x1
1408 #define RG_AUDADC1STSTAGELPEN_MASK_SFT (0x1 << 3)
1410 #define RG_AUDADC2NDSTAGELPEN_MASK 0x1
1411 #define RG_AUDADC2NDSTAGELPEN_MASK_SFT (0x1 << 4)
1413 #define RG_AUDADCFLASHLPEN_MASK 0x1
1414 #define RG_AUDADCFLASHLPEN_MASK_SFT (0x1 << 5)
1416 #define RG_AUDPREAMPIDDTEST_MASK 0x3
1417 #define RG_AUDPREAMPIDDTEST_MASK_SFT (0x3 << 6)
1419 #define RG_AUDADC1STSTAGEIDDTEST_MASK 0x3
1420 #define RG_AUDADC1STSTAGEIDDTEST_MASK_SFT (0x3 << 8)
1422 #define RG_AUDADC2NDSTAGEIDDTEST_MASK 0x3
1423 #define RG_AUDADC2NDSTAGEIDDTEST_MASK_SFT (0x3 << 10)
1425 #define RG_AUDADCREFBUFIDDTEST_MASK 0x3
1426 #define RG_AUDADCREFBUFIDDTEST_MASK_SFT (0x3 << 12)
1428 #define RG_AUDADCFLASHIDDTEST_MASK 0x3
1429 #define RG_AUDADCFLASHIDDTEST_MASK_SFT (0x3 << 14)
1432 #define RG_AUDADCDAC0P25FS_SFT 0
1433 #define RG_AUDADCDAC0P25FS_MASK 0x1
1434 #define RG_AUDADCDAC0P25FS_MASK_SFT (0x1 << 0)
1436 #define RG_AUDADCCLKSEL_MASK 0x1
1437 #define RG_AUDADCCLKSEL_MASK_SFT (0x1 << 1)
1439 #define RG_AUDADCCLKSOURCE_MASK 0x3
1440 #define RG_AUDADCCLKSOURCE_MASK_SFT (0x3 << 2)
1442 #define RG_AUDPREAMPAAFEN_MASK 0x1
1443 #define RG_AUDPREAMPAAFEN_MASK_SFT (0x1 << 8)
1445 #define RG_DCCVCMBUFLPMODSEL_MASK 0x1
1446 #define RG_DCCVCMBUFLPMODSEL_MASK_SFT (0x1 << 9)
1448 #define RG_DCCVCMBUFLPSWEN_MASK 0x1
1449 #define RG_DCCVCMBUFLPSWEN_MASK_SFT (0x1 << 10)
1451 #define RG_CMSTBENH_MASK 0x1
1452 #define RG_CMSTBENH_MASK_SFT (0x1 << 11)
1454 #define RG_PGABODYSW_MASK 0x1
1455 #define RG_PGABODYSW_MASK_SFT (0x1 << 12)
1458 #define RG_AUDADC1STSTAGESDENB_SFT 0
1459 #define RG_AUDADC1STSTAGESDENB_MASK 0x1
1460 #define RG_AUDADC1STSTAGESDENB_MASK_SFT (0x1 << 0)
1462 #define RG_AUDADC2NDSTAGERESET_MASK 0x1
1463 #define RG_AUDADC2NDSTAGERESET_MASK_SFT (0x1 << 1)
1465 #define RG_AUDADC3RDSTAGERESET_MASK 0x1
1466 #define RG_AUDADC3RDSTAGERESET_MASK_SFT (0x1 << 2)
1468 #define RG_AUDADCFSRESET_MASK 0x1
1469 #define RG_AUDADCFSRESET_MASK_SFT (0x1 << 3)
1471 #define RG_AUDADCWIDECM_MASK 0x1
1472 #define RG_AUDADCWIDECM_MASK_SFT (0x1 << 4)
1474 #define RG_AUDADCNOPATEST_MASK 0x1
1475 #define RG_AUDADCNOPATEST_MASK_SFT (0x1 << 5)
1477 #define RG_AUDADCBYPASS_MASK 0x1
1478 #define RG_AUDADCBYPASS_MASK_SFT (0x1 << 6)
1480 #define RG_AUDADCFFBYPASS_MASK 0x1
1481 #define RG_AUDADCFFBYPASS_MASK_SFT (0x1 << 7)
1483 #define RG_AUDADCDACFBCURRENT_MASK 0x1
1484 #define RG_AUDADCDACFBCURRENT_MASK_SFT (0x1 << 8)
1486 #define RG_AUDADCDACIDDTEST_MASK 0x3
1487 #define RG_AUDADCDACIDDTEST_MASK_SFT (0x3 << 9)
1489 #define RG_AUDADCDACNRZ_MASK 0x1
1490 #define RG_AUDADCDACNRZ_MASK_SFT (0x1 << 11)
1492 #define RG_AUDADCNODEM_MASK 0x1
1493 #define RG_AUDADCNODEM_MASK_SFT (0x1 << 12)
1495 #define RG_AUDADCDACTEST_MASK 0x1
1496 #define RG_AUDADCDACTEST_MASK_SFT (0x1 << 13)
1499 #define RG_AUDRCTUNEL_SFT 0
1500 #define RG_AUDRCTUNEL_MASK 0x1f
1501 #define RG_AUDRCTUNEL_MASK_SFT (0x1f << 0)
1503 #define RG_AUDRCTUNELSEL_MASK 0x1
1504 #define RG_AUDRCTUNELSEL_MASK_SFT (0x1 << 5)
1506 #define RG_AUDRCTUNER_MASK 0x1f
1507 #define RG_AUDRCTUNER_MASK_SFT (0x1f << 8)
1509 #define RG_AUDRCTUNERSEL_MASK 0x1
1510 #define RG_AUDRCTUNERSEL_MASK_SFT (0x1 << 13)
1513 #define RG_CLKSQ_EN_SFT 0
1514 #define RG_CLKSQ_EN_MASK 0x1
1515 #define RG_CLKSQ_EN_MASK_SFT (0x1 << 0)
1517 #define RG_CLKSQ_IN_SEL_TEST_MASK 0x1
1518 #define RG_CLKSQ_IN_SEL_TEST_MASK_SFT (0x1 << 1)
1520 #define RG_CM_REFGENSEL_MASK 0x1
1521 #define RG_CM_REFGENSEL_MASK_SFT (0x1 << 2)
1523 #define RG_AUDSPARE_MASK 0xf
1524 #define RG_AUDSPARE_MASK_SFT (0xf << 4)
1526 #define RG_AUDENCSPARE_MASK 0x3f
1527 #define RG_AUDENCSPARE_MASK_SFT (0x3f << 8)
1530 #define RG_AUDENCSPARE2_SFT 0
1531 #define RG_AUDENCSPARE2_MASK 0xff
1532 #define RG_AUDENCSPARE2_MASK_SFT (0xff << 0)
1535 #define RG_AUDDIGMICEN_SFT 0
1536 #define RG_AUDDIGMICEN_MASK 0x1
1537 #define RG_AUDDIGMICEN_MASK_SFT (0x1 << 0)
1539 #define RG_AUDDIGMICBIAS_MASK 0x3
1540 #define RG_AUDDIGMICBIAS_MASK_SFT (0x3 << 1)
1542 #define RG_DMICHPCLKEN_MASK 0x1
1543 #define RG_DMICHPCLKEN_MASK_SFT (0x1 << 3)
1545 #define RG_AUDDIGMICPDUTY_MASK 0x3
1546 #define RG_AUDDIGMICPDUTY_MASK_SFT (0x3 << 4)
1548 #define RG_AUDDIGMICNDUTY_MASK 0x3
1549 #define RG_AUDDIGMICNDUTY_MASK_SFT (0x3 << 6)
1551 #define RG_DMICMONEN_MASK 0x1
1552 #define RG_DMICMONEN_MASK_SFT (0x1 << 8)
1554 #define RG_DMICMONSEL_MASK 0x7
1555 #define RG_DMICMONSEL_MASK_SFT (0x7 << 9)
1557 #define RG_AUDSPAREVMIC_MASK 0xf
1558 #define RG_AUDSPAREVMIC_MASK_SFT (0xf << 12)
1561 #define RG_AUDPWDBMICBIAS0_SFT 0
1562 #define RG_AUDPWDBMICBIAS0_MASK 0x1
1563 #define RG_AUDPWDBMICBIAS0_MASK_SFT (0x1 << 0)
1565 #define RG_AUDMICBIAS0BYPASSEN_MASK 0x1
1566 #define RG_AUDMICBIAS0BYPASSEN_MASK_SFT (0x1 << 1)
1568 #define RG_AUDMICBIAS0LOWPEN_MASK 0x1
1569 #define RG_AUDMICBIAS0LOWPEN_MASK_SFT (0x1 << 2)
1571 #define RG_AUDMICBIAS0VREF_MASK 0x7
1572 #define RG_AUDMICBIAS0VREF_MASK_SFT (0x7 << 4)
1574 #define RG_AUDMICBIAS0DCSW0P1EN_MASK 0x1
1575 #define RG_AUDMICBIAS0DCSW0P1EN_MASK_SFT (0x1 << 8)
1577 #define RG_AUDMICBIAS0DCSW0P2EN_MASK 0x1
1578 #define RG_AUDMICBIAS0DCSW0P2EN_MASK_SFT (0x1 << 9)
1580 #define RG_AUDMICBIAS0DCSW0NEN_MASK 0x1
1581 #define RG_AUDMICBIAS0DCSW0NEN_MASK_SFT (0x1 << 10)
1583 #define RG_AUDMICBIAS0DCSW2P1EN_MASK 0x1
1584 #define RG_AUDMICBIAS0DCSW2P1EN_MASK_SFT (0x1 << 12)
1586 #define RG_AUDMICBIAS0DCSW2P2EN_MASK 0x1
1587 #define RG_AUDMICBIAS0DCSW2P2EN_MASK_SFT (0x1 << 13)
1589 #define RG_AUDMICBIAS0DCSW2NEN_MASK 0x1
1590 #define RG_AUDMICBIAS0DCSW2NEN_MASK_SFT (0x1 << 14)
1593 #define RG_AUDPWDBMICBIAS1_SFT 0
1594 #define RG_AUDPWDBMICBIAS1_MASK 0x1
1595 #define RG_AUDPWDBMICBIAS1_MASK_SFT (0x1 << 0)
1597 #define RG_AUDMICBIAS1BYPASSEN_MASK 0x1
1598 #define RG_AUDMICBIAS1BYPASSEN_MASK_SFT (0x1 << 1)
1600 #define RG_AUDMICBIAS1LOWPEN_MASK 0x1
1601 #define RG_AUDMICBIAS1LOWPEN_MASK_SFT (0x1 << 2)
1603 #define RG_AUDMICBIAS1VREF_MASK 0x7
1604 #define RG_AUDMICBIAS1VREF_MASK_SFT (0x7 << 4)
1606 #define RG_AUDMICBIAS1DCSW1PEN_MASK 0x1
1607 #define RG_AUDMICBIAS1DCSW1PEN_MASK_SFT (0x1 << 8)
1609 #define RG_AUDMICBIAS1DCSW1NEN_MASK 0x1
1610 #define RG_AUDMICBIAS1DCSW1NEN_MASK_SFT (0x1 << 9)
1612 #define RG_BANDGAPGEN_MASK 0x1
1613 #define RG_BANDGAPGEN_MASK_SFT (0x1 << 12)
1615 #define RG_MTEST_EN_MASK 0x1
1616 #define RG_MTEST_EN_MASK_SFT (0x1 << 13)
1618 #define RG_MTEST_SEL_MASK 0x1
1619 #define RG_MTEST_SEL_MASK_SFT (0x1 << 14)
1621 #define RG_MTEST_CURRENT_MASK 0x1
1622 #define RG_MTEST_CURRENT_MASK_SFT (0x1 << 15)
1625 #define RG_AUDACCDETMICBIAS0PULLLOW_SFT 0
1626 #define RG_AUDACCDETMICBIAS0PULLLOW_MASK 0x1
1627 #define RG_AUDACCDETMICBIAS0PULLLOW_MASK_SFT (0x1 << 0)
1629 #define RG_AUDACCDETMICBIAS1PULLLOW_MASK 0x1
1630 #define RG_AUDACCDETMICBIAS1PULLLOW_MASK_SFT (0x1 << 1)
1632 #define RG_AUDACCDETVIN1PULLLOW_MASK 0x1
1633 #define RG_AUDACCDETVIN1PULLLOW_MASK_SFT (0x1 << 2)
1635 #define RG_AUDACCDETVTHACAL_MASK 0x1
1636 #define RG_AUDACCDETVTHACAL_MASK_SFT (0x1 << 4)
1638 #define RG_AUDACCDETVTHBCAL_MASK 0x1
1639 #define RG_AUDACCDETVTHBCAL_MASK_SFT (0x1 << 5)
1641 #define RG_AUDACCDETTVDET_MASK 0x1
1642 #define RG_AUDACCDETTVDET_MASK_SFT (0x1 << 6)
1644 #define RG_ACCDETSEL_MASK 0x1
1645 #define RG_ACCDETSEL_MASK_SFT (0x1 << 7)
1647 #define RG_SWBUFMODSEL_MASK 0x1
1648 #define RG_SWBUFMODSEL_MASK_SFT (0x1 << 8)
1650 #define RG_SWBUFSWEN_MASK 0x1
1651 #define RG_SWBUFSWEN_MASK_SFT (0x1 << 9)
1653 #define RG_EINTCOMPVTH_MASK 0x1
1654 #define RG_EINTCOMPVTH_MASK_SFT (0x1 << 10)
1656 #define RG_EINTCONFIGACCDET_MASK 0x1
1657 #define RG_EINTCONFIGACCDET_MASK_SFT (0x1 << 11)
1659 #define RG_EINTHIRENB_MASK 0x1
1660 #define RG_EINTHIRENB_MASK_SFT (0x1 << 12)
1662 #define RG_ACCDET2AUXRESBYPASS_MASK 0x1
1663 #define RG_ACCDET2AUXRESBYPASS_MASK_SFT (0x1 << 13)
1665 #define RG_ACCDET2AUXBUFFERBYPASS_MASK 0x1
1666 #define RG_ACCDET2AUXBUFFERBYPASS_MASK_SFT (0x1 << 14)
1668 #define RG_ACCDET2AUXSWEN_MASK 0x1
1669 #define RG_ACCDET2AUXSWEN_MASK_SFT (0x1 << 15)
1672 #define RGS_AUDRCTUNELREAD_SFT 0
1673 #define RGS_AUDRCTUNELREAD_MASK 0x1f
1674 #define RGS_AUDRCTUNELREAD_MASK_SFT (0x1f << 0)
1676 #define RGS_AUDRCTUNERREAD_MASK 0x1f
1677 #define RGS_AUDRCTUNERREAD_MASK_SFT (0x1f << 8)
1680 #define AUDDEC_ANA_ID_SFT 0
1681 #define AUDDEC_ANA_ID_MASK 0xff
1682 #define AUDDEC_ANA_ID_MASK_SFT (0xff << 0)
1684 #define AUDDEC_DIG_ID_MASK 0xff
1685 #define AUDDEC_DIG_ID_MASK_SFT (0xff << 8)
1688 #define AUDDEC_ANA_MINOR_REV_SFT 0
1689 #define AUDDEC_ANA_MINOR_REV_MASK 0xf
1690 #define AUDDEC_ANA_MINOR_REV_MASK_SFT (0xf << 0)
1692 #define AUDDEC_ANA_MAJOR_REV_MASK 0xf
1693 #define AUDDEC_ANA_MAJOR_REV_MASK_SFT (0xf << 4)
1695 #define AUDDEC_DIG_MINOR_REV_MASK 0xf
1696 #define AUDDEC_DIG_MINOR_REV_MASK_SFT (0xf << 8)
1698 #define AUDDEC_DIG_MAJOR_REV_MASK 0xf
1699 #define AUDDEC_DIG_MAJOR_REV_MASK_SFT (0xf << 12)
1702 #define AUDDEC_DSN_CBS_SFT 0
1703 #define AUDDEC_DSN_CBS_MASK 0x3
1704 #define AUDDEC_DSN_CBS_MASK_SFT (0x3 << 0)
1706 #define AUDDEC_DSN_BIX_MASK 0x3
1707 #define AUDDEC_DSN_BIX_MASK_SFT (0x3 << 2)
1709 #define AUDDEC_DSN_ESP_MASK 0xff
1710 #define AUDDEC_DSN_ESP_MASK_SFT (0xff << 8)
1713 #define AUDDEC_DSN_FPI_SFT 0
1714 #define AUDDEC_DSN_FPI_MASK 0xff
1715 #define AUDDEC_DSN_FPI_MASK_SFT (0xff << 0)
1718 #define RG_AUDDACLPWRUP_VAUDP15_SFT 0
1719 #define RG_AUDDACLPWRUP_VAUDP15_MASK 0x1
1720 #define RG_AUDDACLPWRUP_VAUDP15_MASK_SFT (0x1 << 0)
1722 #define RG_AUDDACRPWRUP_VAUDP15_MASK 0x1
1723 #define RG_AUDDACRPWRUP_VAUDP15_MASK_SFT (0x1 << 1)
1725 #define RG_AUD_DAC_PWR_UP_VA28_MASK 0x1
1726 #define RG_AUD_DAC_PWR_UP_VA28_MASK_SFT (0x1 << 2)
1728 #define RG_AUD_DAC_PWL_UP_VA28_MASK 0x1
1729 #define RG_AUD_DAC_PWL_UP_VA28_MASK_SFT (0x1 << 3)
1731 #define RG_AUDHPLPWRUP_VAUDP15_MASK 0x1
1732 #define RG_AUDHPLPWRUP_VAUDP15_MASK_SFT (0x1 << 4)
1734 #define RG_AUDHPRPWRUP_VAUDP15_MASK 0x1
1735 #define RG_AUDHPRPWRUP_VAUDP15_MASK_SFT (0x1 << 5)
1737 #define RG_AUDHPLPWRUP_IBIAS_VAUDP15_MASK 0x1
1738 #define RG_AUDHPLPWRUP_IBIAS_VAUDP15_MASK_SFT (0x1 << 6)
1740 #define RG_AUDHPRPWRUP_IBIAS_VAUDP15_MASK 0x1
1741 #define RG_AUDHPRPWRUP_IBIAS_VAUDP15_MASK_SFT (0x1 << 7)
1743 #define RG_AUDHPLMUXINPUTSEL_VAUDP15_MASK 0x3
1744 #define RG_AUDHPLMUXINPUTSEL_VAUDP15_MASK_SFT (0x3 << 8)
1746 #define RG_AUDHPRMUXINPUTSEL_VAUDP15_MASK 0x3
1747 #define RG_AUDHPRMUXINPUTSEL_VAUDP15_MASK_SFT (0x3 << 10)
1749 #define RG_AUDHPLSCDISABLE_VAUDP15_MASK 0x1
1750 #define RG_AUDHPLSCDISABLE_VAUDP15_MASK_SFT (0x1 << 12)
1752 #define RG_AUDHPRSCDISABLE_VAUDP15_MASK 0x1
1753 #define RG_AUDHPRSCDISABLE_VAUDP15_MASK_SFT (0x1 << 13)
1755 #define RG_AUDHPLBSCCURRENT_VAUDP15_MASK 0x1
1756 #define RG_AUDHPLBSCCURRENT_VAUDP15_MASK_SFT (0x1 << 14)
1758 #define RG_AUDHPRBSCCURRENT_VAUDP15_MASK 0x1
1759 #define RG_AUDHPRBSCCURRENT_VAUDP15_MASK_SFT (0x1 << 15)
1762 #define RG_AUDHPLOUTPWRUP_VAUDP15_SFT 0
1763 #define RG_AUDHPLOUTPWRUP_VAUDP15_MASK 0x1
1764 #define RG_AUDHPLOUTPWRUP_VAUDP15_MASK_SFT (0x1 << 0)
1766 #define RG_AUDHPROUTPWRUP_VAUDP15_MASK 0x1
1767 #define RG_AUDHPROUTPWRUP_VAUDP15_MASK_SFT (0x1 << 1)
1769 #define RG_AUDHPLOUTAUXPWRUP_VAUDP15_MASK 0x1
1770 #define RG_AUDHPLOUTAUXPWRUP_VAUDP15_MASK_SFT (0x1 << 2)
1772 #define RG_AUDHPROUTAUXPWRUP_VAUDP15_MASK 0x1
1773 #define RG_AUDHPROUTAUXPWRUP_VAUDP15_MASK_SFT (0x1 << 3)
1775 #define RG_HPLAUXFBRSW_EN_VAUDP15_MASK 0x1
1776 #define RG_HPLAUXFBRSW_EN_VAUDP15_MASK_SFT (0x1 << 4)
1778 #define RG_HPRAUXFBRSW_EN_VAUDP15_MASK 0x1
1779 #define RG_HPRAUXFBRSW_EN_VAUDP15_MASK_SFT (0x1 << 5)
1781 #define RG_HPLSHORT2HPLAUX_EN_VAUDP15_MASK 0x1
1782 #define RG_HPLSHORT2HPLAUX_EN_VAUDP15_MASK_SFT (0x1 << 6)
1784 #define RG_HPRSHORT2HPRAUX_EN_VAUDP15_MASK 0x1
1785 #define RG_HPRSHORT2HPRAUX_EN_VAUDP15_MASK_SFT (0x1 << 7)
1787 #define RG_HPLOUTSTGCTRL_VAUDP15_MASK 0x7
1788 #define RG_HPLOUTSTGCTRL_VAUDP15_MASK_SFT (0x7 << 8)
1790 #define RG_HPROUTSTGCTRL_VAUDP15_MASK 0x7
1791 #define RG_HPROUTSTGCTRL_VAUDP15_MASK_SFT (0x7 << 11)
1794 #define RG_HPLOUTPUTSTBENH_VAUDP15_SFT 0
1795 #define RG_HPLOUTPUTSTBENH_VAUDP15_MASK 0x7
1796 #define RG_HPLOUTPUTSTBENH_VAUDP15_MASK_SFT (0x7 << 0)
1798 #define RG_HPROUTPUTSTBENH_VAUDP15_MASK 0x7
1799 #define RG_HPROUTPUTSTBENH_VAUDP15_MASK_SFT (0x7 << 4)
1801 #define RG_AUDHPSTARTUP_VAUDP15_MASK 0x1
1802 #define RG_AUDHPSTARTUP_VAUDP15_MASK_SFT (0x1 << 13)
1804 #define RG_AUDREFN_DERES_EN_VAUDP15_MASK 0x1
1805 #define RG_AUDREFN_DERES_EN_VAUDP15_MASK_SFT (0x1 << 14)
1807 #define RG_HPPSHORT2VCM_VAUDP15_MASK 0x1
1808 #define RG_HPPSHORT2VCM_VAUDP15_MASK_SFT (0x1 << 15)
1812 #define RG_HPINPUTSTBENH_VAUDP15_MASK 0x1
1813 #define RG_HPINPUTSTBENH_VAUDP15_MASK_SFT (0x1 << 13)
1815 #define RG_HPINPUTRESET0_VAUDP15_MASK 0x1
1816 #define RG_HPINPUTRESET0_VAUDP15_MASK_SFT (0x1 << 14)
1818 #define RG_HPOUTPUTRESET0_VAUDP15_MASK 0x1
1819 #define RG_HPOUTPUTRESET0_VAUDP15_MASK_SFT (0x1 << 15)
1822 #define RG_ABIDEC_RSVD0_VAUDP28_SFT 0
1823 #define RG_ABIDEC_RSVD0_VAUDP28_MASK 0xff
1824 #define RG_ABIDEC_RSVD0_VAUDP28_MASK_SFT (0xff << 0)
1827 #define RG_AUDHPDECMGAINADJ_VAUDP15_SFT 0
1828 #define RG_AUDHPDECMGAINADJ_VAUDP15_MASK 0x7
1829 #define RG_AUDHPDECMGAINADJ_VAUDP15_MASK_SFT (0x7 << 0)
1831 #define RG_AUDHPDEDMGAINADJ_VAUDP15_MASK 0x7
1832 #define RG_AUDHPDEDMGAINADJ_VAUDP15_MASK_SFT (0x7 << 4)
1835 #define RG_AUDHSPWRUP_VAUDP15_SFT 0
1836 #define RG_AUDHSPWRUP_VAUDP15_MASK 0x1
1837 #define RG_AUDHSPWRUP_VAUDP15_MASK_SFT (0x1 << 0)
1839 #define RG_AUDHSPWRUP_IBIAS_VAUDP15_MASK 0x1
1840 #define RG_AUDHSPWRUP_IBIAS_VAUDP15_MASK_SFT (0x1 << 1)
1842 #define RG_AUDHSMUXINPUTSEL_VAUDP15_MASK 0x3
1843 #define RG_AUDHSMUXINPUTSEL_VAUDP15_MASK_SFT (0x3 << 2)
1845 #define RG_AUDHSSCDISABLE_VAUDP15_MASK 0x1
1846 #define RG_AUDHSSCDISABLE_VAUDP15_MASK_SFT (0x1 << 4)
1848 #define RG_AUDHSBSCCURRENT_VAUDP15_MASK 0x1
1849 #define RG_AUDHSBSCCURRENT_VAUDP15_MASK_SFT (0x1 << 5)
1851 #define RG_AUDHSSTARTUP_VAUDP15_MASK 0x1
1852 #define RG_AUDHSSTARTUP_VAUDP15_MASK_SFT (0x1 << 6)
1854 #define RG_HSOUTPUTSTBENH_VAUDP15_MASK 0x1
1855 #define RG_HSOUTPUTSTBENH_VAUDP15_MASK_SFT (0x1 << 7)
1857 #define RG_HSINPUTSTBENH_VAUDP15_MASK 0x1
1858 #define RG_HSINPUTSTBENH_VAUDP15_MASK_SFT (0x1 << 8)
1860 #define RG_HSINPUTRESET0_VAUDP15_MASK 0x1
1861 #define RG_HSINPUTRESET0_VAUDP15_MASK_SFT (0x1 << 9)
1863 #define RG_HSOUTPUTRESET0_VAUDP15_MASK 0x1
1864 #define RG_HSOUTPUTRESET0_VAUDP15_MASK_SFT (0x1 << 10)
1866 #define RG_HSOUT_SHORTVCM_VAUDP15_MASK 0x1
1867 #define RG_HSOUT_SHORTVCM_VAUDP15_MASK_SFT (0x1 << 11)
1870 #define RG_AUDLOLPWRUP_VAUDP15_SFT 0
1871 #define RG_AUDLOLPWRUP_VAUDP15_MASK 0x1
1872 #define RG_AUDLOLPWRUP_VAUDP15_MASK_SFT (0x1 << 0)
1874 #define RG_AUDLOLPWRUP_IBIAS_VAUDP15_MASK 0x1
1875 #define RG_AUDLOLPWRUP_IBIAS_VAUDP15_MASK_SFT (0x1 << 1)
1877 #define RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK 0x3
1878 #define RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK_SFT (0x3 << 2)
1880 #define RG_AUDLOLSCDISABLE_VAUDP15_MASK 0x1
1881 #define RG_AUDLOLSCDISABLE_VAUDP15_MASK_SFT (0x1 << 4)
1883 #define RG_AUDLOLBSCCURRENT_VAUDP15_MASK 0x1
1884 #define RG_AUDLOLBSCCURRENT_VAUDP15_MASK_SFT (0x1 << 5)
1886 #define RG_AUDLOSTARTUP_VAUDP15_MASK 0x1
1887 #define RG_AUDLOSTARTUP_VAUDP15_MASK_SFT (0x1 << 6)
1889 #define RG_LOINPUTSTBENH_VAUDP15_MASK 0x1
1890 #define RG_LOINPUTSTBENH_VAUDP15_MASK_SFT (0x1 << 7)
1892 #define RG_LOOUTPUTSTBENH_VAUDP15_MASK 0x1
1893 #define RG_LOOUTPUTSTBENH_VAUDP15_MASK_SFT (0x1 << 8)
1895 #define RG_LOINPUTRESET0_VAUDP15_MASK 0x1
1896 #define RG_LOINPUTRESET0_VAUDP15_MASK_SFT (0x1 << 9)
1898 #define RG_LOOUTPUTRESET0_VAUDP15_MASK 0x1
1899 #define RG_LOOUTPUTRESET0_VAUDP15_MASK_SFT (0x1 << 10)
1901 #define RG_LOOUT_SHORTVCM_VAUDP15_MASK 0x1
1902 #define RG_LOOUT_SHORTVCM_VAUDP15_MASK_SFT (0x1 << 11)
1905 #define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_SFT 0
1906 #define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_MASK 0xf
1907 #define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_MASK_SFT (0xf << 0)
1909 #define RG_AUDTRIMBUF_GAINSEL_VAUDP15_MASK 0x3
1910 #define RG_AUDTRIMBUF_GAINSEL_VAUDP15_MASK_SFT (0x3 << 4)
1912 #define RG_AUDTRIMBUF_EN_VAUDP15_MASK 0x1
1913 #define RG_AUDTRIMBUF_EN_VAUDP15_MASK_SFT (0x1 << 6)
1915 #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_MASK 0x3
1916 #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_MASK_SFT (0x3 << 8)
1918 #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_MASK 0x3
1919 #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_MASK_SFT (0x3 << 10)
1921 #define RG_AUDHPSPKDET_EN_VAUDP15_MASK 0x1
1922 #define RG_AUDHPSPKDET_EN_VAUDP15_MASK_SFT (0x1 << 12)
1925 #define RG_ABIDEC_RSVD0_VA28_SFT 0
1926 #define RG_ABIDEC_RSVD0_VA28_MASK 0xff
1927 #define RG_ABIDEC_RSVD0_VA28_MASK_SFT (0xff << 0)
1929 #define RG_ABIDEC_RSVD0_VAUDP15_MASK 0xff
1930 #define RG_ABIDEC_RSVD0_VAUDP15_MASK_SFT (0xff << 8)
1933 #define RG_ABIDEC_RSVD1_VAUDP15_SFT 0
1934 #define RG_ABIDEC_RSVD1_VAUDP15_MASK 0xff
1935 #define RG_ABIDEC_RSVD1_VAUDP15_MASK_SFT (0xff << 0)
1937 #define RG_ABIDEC_RSVD2_VAUDP15_MASK 0xff
1938 #define RG_ABIDEC_RSVD2_VAUDP15_MASK_SFT (0xff << 8)
1941 #define RG_AUDZCDMUXSEL_VAUDP15_SFT 0
1942 #define RG_AUDZCDMUXSEL_VAUDP15_MASK 0x7
1943 #define RG_AUDZCDMUXSEL_VAUDP15_MASK_SFT (0x7 << 0)
1945 #define RG_AUDZCDCLKSEL_VAUDP15_MASK 0x1
1946 #define RG_AUDZCDCLKSEL_VAUDP15_MASK_SFT (0x1 << 3)
1948 #define RG_AUDBIASADJ_0_VAUDP15_MASK 0x1ff
1949 #define RG_AUDBIASADJ_0_VAUDP15_MASK_SFT (0x1ff << 7)
1952 #define RG_AUDBIASADJ_1_VAUDP15_SFT 0
1953 #define RG_AUDBIASADJ_1_VAUDP15_MASK 0xff
1954 #define RG_AUDBIASADJ_1_VAUDP15_MASK_SFT (0xff << 0)
1956 #define RG_AUDIBIASPWRDN_VAUDP15_MASK 0x1
1957 #define RG_AUDIBIASPWRDN_VAUDP15_MASK_SFT (0x1 << 8)
1960 #define RG_RSTB_DECODER_VA28_SFT 0
1961 #define RG_RSTB_DECODER_VA28_MASK 0x1
1962 #define RG_RSTB_DECODER_VA28_MASK_SFT (0x1 << 0)
1964 #define RG_SEL_DECODER_96K_VA28_MASK 0x1
1965 #define RG_SEL_DECODER_96K_VA28_MASK_SFT (0x1 << 1)
1967 #define RG_SEL_DELAY_VCORE_MASK 0x1
1968 #define RG_SEL_DELAY_VCORE_MASK_SFT (0x1 << 2)
1970 #define RG_AUDGLB_PWRDN_VA28_MASK 0x1
1971 #define RG_AUDGLB_PWRDN_VA28_MASK_SFT (0x1 << 4)
1973 #define RG_RSTB_ENCODER_VA28_MASK 0x1
1974 #define RG_RSTB_ENCODER_VA28_MASK_SFT (0x1 << 5)
1976 #define RG_SEL_ENCODER_96K_VA28_MASK 0x1
1977 #define RG_SEL_ENCODER_96K_VA28_MASK_SFT (0x1 << 6)
1980 #define RG_HCLDO_EN_VA18_SFT 0
1981 #define RG_HCLDO_EN_VA18_MASK 0x1
1982 #define RG_HCLDO_EN_VA18_MASK_SFT (0x1 << 0)
1984 #define RG_HCLDO_PDDIS_EN_VA18_MASK 0x1
1985 #define RG_HCLDO_PDDIS_EN_VA18_MASK_SFT (0x1 << 1)
1987 #define RG_HCLDO_REMOTE_SENSE_VA18_MASK 0x1
1988 #define RG_HCLDO_REMOTE_SENSE_VA18_MASK_SFT (0x1 << 2)
1990 #define RG_LCLDO_EN_VA18_MASK 0x1
1991 #define RG_LCLDO_EN_VA18_MASK_SFT (0x1 << 4)
1993 #define RG_LCLDO_PDDIS_EN_VA18_MASK 0x1
1994 #define RG_LCLDO_PDDIS_EN_VA18_MASK_SFT (0x1 << 5)
1996 #define RG_LCLDO_REMOTE_SENSE_VA18_MASK 0x1
1997 #define RG_LCLDO_REMOTE_SENSE_VA18_MASK_SFT (0x1 << 6)
1999 #define RG_LCLDO_ENC_EN_VA28_MASK 0x1
2000 #define RG_LCLDO_ENC_EN_VA28_MASK_SFT (0x1 << 8)
2002 #define RG_LCLDO_ENC_PDDIS_EN_VA28_MASK 0x1
2003 #define RG_LCLDO_ENC_PDDIS_EN_VA28_MASK_SFT (0x1 << 9)
2005 #define RG_LCLDO_ENC_REMOTE_SENSE_VA28_MASK 0x1
2006 #define RG_LCLDO_ENC_REMOTE_SENSE_VA28_MASK_SFT (0x1 << 10)
2008 #define RG_VA33REFGEN_EN_VA18_MASK 0x1
2009 #define RG_VA33REFGEN_EN_VA18_MASK_SFT (0x1 << 12)
2011 #define RG_VA28REFGEN_EN_VA28_MASK 0x1
2012 #define RG_VA28REFGEN_EN_VA28_MASK_SFT (0x1 << 13)
2014 #define RG_HCLDO_VOSEL_VA18_MASK 0x1
2015 #define RG_HCLDO_VOSEL_VA18_MASK_SFT (0x1 << 14)
2017 #define RG_LCLDO_VOSEL_VA18_MASK 0x1
2018 #define RG_LCLDO_VOSEL_VA18_MASK_SFT (0x1 << 15)
2021 #define RG_NVREG_EN_VAUDP15_SFT 0
2022 #define RG_NVREG_EN_VAUDP15_MASK 0x1
2023 #define RG_NVREG_EN_VAUDP15_MASK_SFT (0x1 << 0)
2025 #define RG_NVREG_PULL0V_VAUDP15_MASK 0x1
2026 #define RG_NVREG_PULL0V_VAUDP15_MASK_SFT (0x1 << 1)
2028 #define RG_AUDPMU_RSD0_VAUDP15_MASK 0xf
2029 #define RG_AUDPMU_RSD0_VAUDP15_MASK_SFT (0xf << 4)
2031 #define RG_AUDPMU_RSD0_VA18_MASK 0xf
2032 #define RG_AUDPMU_RSD0_VA18_MASK_SFT (0xf << 8)
2034 #define RG_AUDPMU_RSD0_VA28_MASK 0xf
2035 #define RG_AUDPMU_RSD0_VA28_MASK_SFT (0xf << 12)
2038 #define RG_AUDZCDENABLE_SFT 0
2039 #define RG_AUDZCDENABLE_MASK 0x1
2040 #define RG_AUDZCDENABLE_MASK_SFT (0x1 << 0)
2042 #define RG_AUDZCDGAINSTEPTIME_MASK 0x7
2043 #define RG_AUDZCDGAINSTEPTIME_MASK_SFT (0x7 << 1)
2045 #define RG_AUDZCDGAINSTEPSIZE_MASK 0x3
2046 #define RG_AUDZCDGAINSTEPSIZE_MASK_SFT (0x3 << 4)
2048 #define RG_AUDZCDTIMEOUTMODESEL_MASK 0x1
2049 #define RG_AUDZCDTIMEOUTMODESEL_MASK_SFT (0x1 << 6)
2052 #define RG_AUDLOLGAIN_SFT 0
2053 #define RG_AUDLOLGAIN_MASK 0x1f
2054 #define RG_AUDLOLGAIN_MASK_SFT (0x1f << 0)
2056 #define RG_AUDLORGAIN_MASK 0x1f
2057 #define RG_AUDLORGAIN_MASK_SFT (0x1f << 7)
2060 #define RG_AUDHPLGAIN_SFT 0
2061 #define RG_AUDHPLGAIN_MASK 0x1f
2062 #define RG_AUDHPLGAIN_MASK_SFT (0x1f << 0)
2064 #define RG_AUDHPRGAIN_MASK 0x1f
2065 #define RG_AUDHPRGAIN_MASK_SFT (0x1f << 7)
2068 #define RG_AUDHSGAIN_SFT 0
2069 #define RG_AUDHSGAIN_MASK 0x1f
2070 #define RG_AUDHSGAIN_MASK_SFT (0x1f << 0)
2073 #define RG_AUDIVLGAIN_SFT 0
2074 #define RG_AUDIVLGAIN_MASK 0x7
2075 #define RG_AUDIVLGAIN_MASK_SFT (0x7 << 0)
2077 #define RG_AUDIVRGAIN_MASK 0x7
2078 #define RG_AUDIVRGAIN_MASK_SFT (0x7 << 8)
2081 #define RG_AUDINTGAIN1_SFT 0
2082 #define RG_AUDINTGAIN1_MASK 0x3f
2083 #define RG_AUDINTGAIN1_MASK_SFT (0x3f << 0)
2085 #define RG_AUDINTGAIN2_MASK 0x3f
2086 #define RG_AUDINTGAIN2_MASK_SFT (0x3f << 8)
2089 #define MT6358_DRV_CON3 0x3c
2090 #define MT6358_GPIO_DIR0 0x88
2092 #define MT6358_GPIO_MODE2 0xd8 /* mosi */
2093 #define MT6358_GPIO_MODE2_SET 0xda
2094 #define MT6358_GPIO_MODE2_CLR 0xdc
2096 #define MT6358_GPIO_MODE3 0xde /* miso */
2097 #define MT6358_GPIO_MODE3_SET 0xe0
2098 #define MT6358_GPIO_MODE3_CLR 0xe2
2100 #define MT6358_TOP_CKPDN_CON0 0x10c
2101 #define MT6358_TOP_CKPDN_CON0_SET 0x10e
2102 #define MT6358_TOP_CKPDN_CON0_CLR 0x110
2104 #define MT6358_TOP_CKHWEN_CON0 0x12a
2105 #define MT6358_TOP_CKHWEN_CON0_SET 0x12c
2106 #define MT6358_TOP_CKHWEN_CON0_CLR 0x12e
2108 #define MT6358_OTP_CON0 0x38a
2109 #define MT6358_OTP_CON8 0x39a
2110 #define MT6358_OTP_CON11 0x3a0
2111 #define MT6358_OTP_CON12 0x3a2
2112 #define MT6358_OTP_CON13 0x3a4
2114 #define MT6358_DCXO_CW13 0x7aa
2115 #define MT6358_DCXO_CW14 0x7ac
2117 #define MT6358_AUXADC_CON10 0x11a0
2120 #define MT6358_AUD_TOP_ID 0x2200
2121 #define MT6358_AUD_TOP_REV0 0x2202
2122 #define MT6358_AUD_TOP_DBI 0x2204
2123 #define MT6358_AUD_TOP_DXI 0x2206
2124 #define MT6358_AUD_TOP_CKPDN_TPM0 0x2208
2125 #define MT6358_AUD_TOP_CKPDN_TPM1 0x220a
2126 #define MT6358_AUD_TOP_CKPDN_CON0 0x220c
2127 #define MT6358_AUD_TOP_CKPDN_CON0_SET 0x220e
2128 #define MT6358_AUD_TOP_CKPDN_CON0_CLR 0x2210
2129 #define MT6358_AUD_TOP_CKSEL_CON0 0x2212
2130 #define MT6358_AUD_TOP_CKSEL_CON0_SET 0x2214
2131 #define MT6358_AUD_TOP_CKSEL_CON0_CLR 0x2216
2132 #define MT6358_AUD_TOP_CKTST_CON0 0x2218
2133 #define MT6358_AUD_TOP_CLK_HWEN_CON0 0x221a
2134 #define MT6358_AUD_TOP_CLK_HWEN_CON0_SET 0x221c
2135 #define MT6358_AUD_TOP_CLK_HWEN_CON0_CLR 0x221e
2136 #define MT6358_AUD_TOP_RST_CON0 0x2220
2137 #define MT6358_AUD_TOP_RST_CON0_SET 0x2222
2138 #define MT6358_AUD_TOP_RST_CON0_CLR 0x2224
2139 #define MT6358_AUD_TOP_RST_BANK_CON0 0x2226
2140 #define MT6358_AUD_TOP_INT_CON0 0x2228
2141 #define MT6358_AUD_TOP_INT_CON0_SET 0x222a
2142 #define MT6358_AUD_TOP_INT_CON0_CLR 0x222c
2143 #define MT6358_AUD_TOP_INT_MASK_CON0 0x222e
2144 #define MT6358_AUD_TOP_INT_MASK_CON0_SET 0x2230
2145 #define MT6358_AUD_TOP_INT_MASK_CON0_CLR 0x2232
2146 #define MT6358_AUD_TOP_INT_STATUS0 0x2234
2147 #define MT6358_AUD_TOP_INT_RAW_STATUS0 0x2236
2148 #define MT6358_AUD_TOP_INT_MISC_CON0 0x2238
2149 #define MT6358_AUDNCP_CLKDIV_CON0 0x223a
2150 #define MT6358_AUDNCP_CLKDIV_CON1 0x223c
2151 #define MT6358_AUDNCP_CLKDIV_CON2 0x223e
2152 #define MT6358_AUDNCP_CLKDIV_CON3 0x2240
2153 #define MT6358_AUDNCP_CLKDIV_CON4 0x2242
2154 #define MT6358_AUD_TOP_MON_CON0 0x2244
2155 #define MT6358_AUDIO_DIG_DSN_ID 0x2280
2156 #define MT6358_AUDIO_DIG_DSN_REV0 0x2282
2157 #define MT6358_AUDIO_DIG_DSN_DBI 0x2284
2158 #define MT6358_AUDIO_DIG_DSN_DXI 0x2286
2159 #define MT6358_AFE_UL_DL_CON0 0x2288
2160 #define MT6358_AFE_DL_SRC2_CON0_L 0x228a
2161 #define MT6358_AFE_UL_SRC_CON0_H 0x228c
2162 #define MT6358_AFE_UL_SRC_CON0_L 0x228e
2163 #define MT6358_AFE_TOP_CON0 0x2290
2164 #define MT6358_AUDIO_TOP_CON0 0x2292
2165 #define MT6358_AFE_MON_DEBUG0 0x2294
2166 #define MT6358_AFUNC_AUD_CON0 0x2296
2167 #define MT6358_AFUNC_AUD_CON1 0x2298
2168 #define MT6358_AFUNC_AUD_CON2 0x229a
2169 #define MT6358_AFUNC_AUD_CON3 0x229c
2170 #define MT6358_AFUNC_AUD_CON4 0x229e
2171 #define MT6358_AFUNC_AUD_CON5 0x22a0
2172 #define MT6358_AFUNC_AUD_CON6 0x22a2
2173 #define MT6358_AFUNC_AUD_MON0 0x22a4
2174 #define MT6358_AUDRC_TUNE_MON0 0x22a6
2175 #define MT6358_AFE_ADDA_MTKAIF_FIFO_CFG0 0x22a8
2176 #define MT6358_AFE_ADDA_MTKAIF_FIFO_LOG_MON1 0x22aa
2177 #define MT6358_AFE_ADDA_MTKAIF_MON0 0x22ac
2178 #define MT6358_AFE_ADDA_MTKAIF_MON1 0x22ae
2179 #define MT6358_AFE_ADDA_MTKAIF_MON2 0x22b0
2180 #define MT6358_AFE_ADDA_MTKAIF_MON3 0x22b2
2181 #define MT6358_AFE_ADDA_MTKAIF_CFG0 0x22b4
2182 #define MT6358_AFE_ADDA_MTKAIF_RX_CFG0 0x22b6
2183 #define MT6358_AFE_ADDA_MTKAIF_RX_CFG1 0x22b8
2184 #define MT6358_AFE_ADDA_MTKAIF_RX_CFG2 0x22ba
2185 #define MT6358_AFE_ADDA_MTKAIF_RX_CFG3 0x22bc
2186 #define MT6358_AFE_ADDA_MTKAIF_TX_CFG1 0x22be
2187 #define MT6358_AFE_SGEN_CFG0 0x22c0
2188 #define MT6358_AFE_SGEN_CFG1 0x22c2
2189 #define MT6358_AFE_ADC_ASYNC_FIFO_CFG 0x22c4
2190 #define MT6358_AFE_DCCLK_CFG0 0x22c6
2191 #define MT6358_AFE_DCCLK_CFG1 0x22c8
2192 #define MT6358_AUDIO_DIG_CFG 0x22ca
2193 #define MT6358_AFE_AUD_PAD_TOP 0x22cc
2194 #define MT6358_AFE_AUD_PAD_TOP_MON 0x22ce
2195 #define MT6358_AFE_AUD_PAD_TOP_MON1 0x22d0
2196 #define MT6358_AFE_DL_NLE_CFG 0x22d2
2197 #define MT6358_AFE_DL_NLE_MON 0x22d4
2198 #define MT6358_AFE_CG_EN_MON 0x22d6
2199 #define MT6358_AUDIO_DIG_2ND_DSN_ID 0x2300
2200 #define MT6358_AUDIO_DIG_2ND_DSN_REV0 0x2302
2201 #define MT6358_AUDIO_DIG_2ND_DSN_DBI 0x2304
2202 #define MT6358_AUDIO_DIG_2ND_DSN_DXI 0x2306
2203 #define MT6358_AFE_PMIC_NEWIF_CFG3 0x2308
2204 #define MT6358_AFE_VOW_TOP 0x230a
2205 #define MT6358_AFE_VOW_CFG0 0x230c
2206 #define MT6358_AFE_VOW_CFG1 0x230e
2207 #define MT6358_AFE_VOW_CFG2 0x2310
2208 #define MT6358_AFE_VOW_CFG3 0x2312
2209 #define MT6358_AFE_VOW_CFG4 0x2314
2210 #define MT6358_AFE_VOW_CFG5 0x2316
2211 #define MT6358_AFE_VOW_CFG6 0x2318
2212 #define MT6358_AFE_VOW_MON0 0x231a
2213 #define MT6358_AFE_VOW_MON1 0x231c
2214 #define MT6358_AFE_VOW_MON2 0x231e
2215 #define MT6358_AFE_VOW_MON3 0x2320
2216 #define MT6358_AFE_VOW_MON4 0x2322
2217 #define MT6358_AFE_VOW_MON5 0x2324
2218 #define MT6358_AFE_VOW_SN_INI_CFG 0x2326
2219 #define MT6358_AFE_VOW_TGEN_CFG0 0x2328
2220 #define MT6358_AFE_VOW_POSDIV_CFG0 0x232a
2221 #define MT6358_AFE_VOW_HPF_CFG0 0x232c
2222 #define MT6358_AFE_VOW_PERIODIC_CFG0 0x232e
2223 #define MT6358_AFE_VOW_PERIODIC_CFG1 0x2330
2224 #define MT6358_AFE_VOW_PERIODIC_CFG2 0x2332
2225 #define MT6358_AFE_VOW_PERIODIC_CFG3 0x2334
2226 #define MT6358_AFE_VOW_PERIODIC_CFG4 0x2336
2227 #define MT6358_AFE_VOW_PERIODIC_CFG5 0x2338
2228 #define MT6358_AFE_VOW_PERIODIC_CFG6 0x233a
2229 #define MT6358_AFE_VOW_PERIODIC_CFG7 0x233c
2230 #define MT6358_AFE_VOW_PERIODIC_CFG8 0x233e
2231 #define MT6358_AFE_VOW_PERIODIC_CFG9 0x2340
2232 #define MT6358_AFE_VOW_PERIODIC_CFG10 0x2342
2233 #define MT6358_AFE_VOW_PERIODIC_CFG11 0x2344
2234 #define MT6358_AFE_VOW_PERIODIC_CFG12 0x2346
2235 #define MT6358_AFE_VOW_PERIODIC_CFG13 0x2348
2236 #define MT6358_AFE_VOW_PERIODIC_CFG14 0x234a
2237 #define MT6358_AFE_VOW_PERIODIC_CFG15 0x234c
2238 #define MT6358_AFE_VOW_PERIODIC_CFG16 0x234e
2239 #define MT6358_AFE_VOW_PERIODIC_CFG17 0x2350
2240 #define MT6358_AFE_VOW_PERIODIC_CFG18 0x2352
2241 #define MT6358_AFE_VOW_PERIODIC_CFG19 0x2354
2242 #define MT6358_AFE_VOW_PERIODIC_CFG20 0x2356
2243 #define MT6358_AFE_VOW_PERIODIC_CFG21 0x2358
2244 #define MT6358_AFE_VOW_PERIODIC_CFG22 0x235a
2245 #define MT6358_AFE_VOW_PERIODIC_CFG23 0x235c
2246 #define MT6358_AFE_VOW_PERIODIC_MON0 0x235e
2247 #define MT6358_AFE_VOW_PERIODIC_MON1 0x2360
2248 #define MT6358_AUDENC_DSN_ID 0x2380
2249 #define MT6358_AUDENC_DSN_REV0 0x2382
2250 #define MT6358_AUDENC_DSN_DBI 0x2384
2251 #define MT6358_AUDENC_DSN_FPI 0x2386
2252 #define MT6358_AUDENC_ANA_CON0 0x2388
2253 #define MT6358_AUDENC_ANA_CON1 0x238a
2254 #define MT6358_AUDENC_ANA_CON2 0x238c
2255 #define MT6358_AUDENC_ANA_CON3 0x238e
2256 #define MT6358_AUDENC_ANA_CON4 0x2390
2257 #define MT6358_AUDENC_ANA_CON5 0x2392
2258 #define MT6358_AUDENC_ANA_CON6 0x2394
2259 #define MT6358_AUDENC_ANA_CON7 0x2396
2260 #define MT6358_AUDENC_ANA_CON8 0x2398
2261 #define MT6358_AUDENC_ANA_CON9 0x239a
2262 #define MT6358_AUDENC_ANA_CON10 0x239c
2263 #define MT6358_AUDENC_ANA_CON11 0x239e
2264 #define MT6358_AUDENC_ANA_CON12 0x23a0
2265 #define MT6358_AUDDEC_DSN_ID 0x2400
2266 #define MT6358_AUDDEC_DSN_REV0 0x2402
2267 #define MT6358_AUDDEC_DSN_DBI 0x2404
2268 #define MT6358_AUDDEC_DSN_FPI 0x2406
2269 #define MT6358_AUDDEC_ANA_CON0 0x2408
2270 #define MT6358_AUDDEC_ANA_CON1 0x240a
2271 #define MT6358_AUDDEC_ANA_CON2 0x240c
2272 #define MT6358_AUDDEC_ANA_CON3 0x240e
2273 #define MT6358_AUDDEC_ANA_CON4 0x2410
2274 #define MT6358_AUDDEC_ANA_CON5 0x2412
2275 #define MT6358_AUDDEC_ANA_CON6 0x2414
2276 #define MT6358_AUDDEC_ANA_CON7 0x2416
2277 #define MT6358_AUDDEC_ANA_CON8 0x2418
2278 #define MT6358_AUDDEC_ANA_CON9 0x241a
2279 #define MT6358_AUDDEC_ANA_CON10 0x241c
2280 #define MT6358_AUDDEC_ANA_CON11 0x241e
2281 #define MT6358_AUDDEC_ANA_CON12 0x2420
2282 #define MT6358_AUDDEC_ANA_CON13 0x2422
2283 #define MT6358_AUDDEC_ANA_CON14 0x2424
2284 #define MT6358_AUDDEC_ANA_CON15 0x2426
2285 #define MT6358_AUDDEC_ELR_NUM 0x2428
2286 #define MT6358_AUDDEC_ELR_0 0x242a
2287 #define MT6358_AUDZCD_DSN_ID 0x2480
2288 #define MT6358_AUDZCD_DSN_REV0 0x2482
2289 #define MT6358_AUDZCD_DSN_DBI 0x2484
2290 #define MT6358_AUDZCD_DSN_FPI 0x2486
2291 #define MT6358_ZCD_CON0 0x2488
2292 #define MT6358_ZCD_CON1 0x248a
2293 #define MT6358_ZCD_CON2 0x248c
2294 #define MT6358_ZCD_CON3 0x248e
2295 #define MT6358_ZCD_CON4 0x2490
2296 #define MT6358_ZCD_CON5 0x2492
2297 #define MT6358_ACCDET_CON13 0x2522
2302 MT6358_MTKAIF_PROTOCOL_1 = 0,