Lines Matching +full:static +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0
3 // mt6358.c -- mt6358 ALSA SoC audio codec driver
107 priv->mtkaif_protocol = mtkaif_protocol; in mt6358_set_mtkaif_protocol()
111 static void playback_gpio_set(struct mt6358_priv *priv) in playback_gpio_set()
114 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR, in playback_gpio_set()
116 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_SET, in playback_gpio_set()
118 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2, in playback_gpio_set()
122 static void playback_gpio_reset(struct mt6358_priv *priv) in playback_gpio_reset()
129 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR, in playback_gpio_reset()
131 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2, in playback_gpio_reset()
133 regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0, in playback_gpio_reset()
137 static void capture_gpio_set(struct mt6358_priv *priv) in capture_gpio_set()
140 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR, in capture_gpio_set()
142 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_SET, in capture_gpio_set()
144 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, in capture_gpio_set()
148 static void capture_gpio_reset(struct mt6358_priv *priv) in capture_gpio_reset()
156 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR, in capture_gpio_reset()
158 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, in capture_gpio_reset()
160 regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0, in capture_gpio_reset()
165 static int mt6358_set_dcxo(struct mt6358_priv *priv, bool enable) in mt6358_set_dcxo() argument
167 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, in mt6358_set_dcxo()
169 (enable ? 1 : 0) << RG_XO_AUDIO_EN_M_SFT); in mt6358_set_dcxo()
174 static int mt6358_set_clksq(struct mt6358_priv *priv, bool enable) in mt6358_set_clksq() argument
177 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6, in mt6358_set_clksq()
181 /* Enable/disable CLKSQ 26MHz */ in mt6358_set_clksq()
182 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6, in mt6358_set_clksq()
184 (enable ? 1 : 0) << RG_CLKSQ_EN_SFT); in mt6358_set_clksq()
189 static int mt6358_set_aud_global_bias(struct mt6358_priv *priv, bool enable) in mt6358_set_aud_global_bias() argument
191 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, in mt6358_set_aud_global_bias()
193 (enable ? 0 : 1) << RG_AUDGLB_PWRDN_VA28_SFT); in mt6358_set_aud_global_bias()
198 static int mt6358_set_topck(struct mt6358_priv *priv, bool enable) in mt6358_set_topck() argument
200 regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0, in mt6358_set_topck()
201 0x0066, enable ? 0x0 : 0x66); in mt6358_set_topck()
205 static int mt6358_mtkaif_tx_enable(struct mt6358_priv *priv) in mt6358_mtkaif_tx_enable()
207 switch (priv->mtkaif_protocol) { in mt6358_mtkaif_tx_enable()
210 regmap_update_bits(priv->regmap, in mt6358_mtkaif_tx_enable()
213 /* enable aud_pad TX fifos */ in mt6358_mtkaif_tx_enable()
214 regmap_update_bits(priv->regmap, in mt6358_mtkaif_tx_enable()
217 regmap_update_bits(priv->regmap, in mt6358_mtkaif_tx_enable()
223 regmap_update_bits(priv->regmap, in mt6358_mtkaif_tx_enable()
226 /* enable aud_pad TX fifos */ in mt6358_mtkaif_tx_enable()
227 regmap_update_bits(priv->regmap, in mt6358_mtkaif_tx_enable()
234 regmap_update_bits(priv->regmap, in mt6358_mtkaif_tx_enable()
237 /* enable aud_pad TX fifos */ in mt6358_mtkaif_tx_enable()
238 regmap_update_bits(priv->regmap, in mt6358_mtkaif_tx_enable()
246 static int mt6358_mtkaif_tx_disable(struct mt6358_priv *priv) in mt6358_mtkaif_tx_disable()
249 regmap_update_bits(priv->regmap, MT6358_AFE_AUD_PAD_TOP, in mt6358_mtkaif_tx_disable()
268 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG, in mt6358_mtkaif_calibration_enable()
271 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG, in mt6358_mtkaif_calibration_enable()
282 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG, in mt6358_mtkaif_calibration_disable()
285 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG, in mt6358_mtkaif_calibration_disable()
305 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG, in mt6358_set_mtkaif_calibration_phase()
308 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG, in mt6358_set_mtkaif_calibration_phase()
327 static void hp_zcd_disable(struct mt6358_priv *priv) in hp_zcd_disable()
329 regmap_write(priv->regmap, MT6358_ZCD_CON0, 0x0000); in hp_zcd_disable()
332 static void hp_main_output_ramp(struct mt6358_priv *priv, bool up) in hp_main_output_ramp()
337 /* Enable/Reduce HPL/R main output stage step by step */ in hp_main_output_ramp()
339 stage = up ? i : target - i; in hp_main_output_ramp()
340 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, in hp_main_output_ramp()
342 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, in hp_main_output_ramp()
348 static void hp_aux_feedback_loop_gain_ramp(struct mt6358_priv *priv, bool up) in hp_aux_feedback_loop_gain_ramp()
354 stage = up ? i : 0xf - i; in hp_aux_feedback_loop_gain_ramp()
355 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, in hp_aux_feedback_loop_gain_ramp()
361 static void hp_pull_down(struct mt6358_priv *priv, bool enable) in hp_pull_down() argument
365 if (enable) { in hp_pull_down()
367 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, in hp_pull_down()
372 for (i = 0x6; i >= 0x1; i--) { in hp_pull_down()
373 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, in hp_pull_down()
380 static bool is_valid_hp_pga_idx(int reg_idx) in is_valid_hp_pga_idx()
386 static void headset_volume_ramp(struct mt6358_priv *priv, int from, int to) in headset_volume_ramp()
391 dev_warn(priv->dev, "%s(), volume index is not valid, from %d, to %d\n", in headset_volume_ramp()
394 dev_info(priv->dev, "%s(), from %d, to %d\n", in headset_volume_ramp()
398 offset = to - from; in headset_volume_ramp()
400 offset = from - to; in headset_volume_ramp()
406 reg_idx = from - count; in headset_volume_ramp()
409 regmap_update_bits(priv->regmap, in headset_volume_ramp()
415 offset--; in headset_volume_ramp()
420 static int mt6358_put_volsw(struct snd_kcontrol *kcontrol, in mt6358_put_volsw()
427 (struct soc_mixer_control *)kcontrol->private_value; in mt6358_put_volsw()
435 switch (mc->reg) { in mt6358_put_volsw()
437 regmap_read(priv->regmap, MT6358_ZCD_CON2, ®); in mt6358_put_volsw()
438 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] = in mt6358_put_volsw()
440 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] = in mt6358_put_volsw()
444 regmap_read(priv->regmap, MT6358_ZCD_CON1, ®); in mt6358_put_volsw()
445 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] = in mt6358_put_volsw()
447 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] = in mt6358_put_volsw()
451 regmap_read(priv->regmap, MT6358_ZCD_CON3, ®); in mt6358_put_volsw()
452 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL] = in mt6358_put_volsw()
454 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTR] = in mt6358_put_volsw()
459 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON0, ®); in mt6358_put_volsw()
460 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1] = in mt6358_put_volsw()
462 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON1, ®); in mt6358_put_volsw()
463 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2] = in mt6358_put_volsw()
471 static void mt6358_restore_pga(struct mt6358_priv *priv);
473 static int mt6358_enable_wov_phase2(struct mt6358_priv *priv) in mt6358_enable_wov_phase2()
476 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, in mt6358_enable_wov_phase2()
478 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5); in mt6358_enable_wov_phase2()
479 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_enable_wov_phase2()
483 regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9929); in mt6358_enable_wov_phase2()
484 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, in mt6358_enable_wov_phase2()
486 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON8, in mt6358_enable_wov_phase2()
490 regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0, in mt6358_enable_wov_phase2()
492 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x0120); in mt6358_enable_wov_phase2()
493 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0xffff); in mt6358_enable_wov_phase2()
494 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0200); in mt6358_enable_wov_phase2()
495 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2424); in mt6358_enable_wov_phase2()
496 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xdbac); in mt6358_enable_wov_phase2()
497 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x029e); in mt6358_enable_wov_phase2()
498 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0000); in mt6358_enable_wov_phase2()
499 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_POSDIV_CFG0, in mt6358_enable_wov_phase2()
501 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_HPF_CFG0, in mt6358_enable_wov_phase2()
503 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0x68d1); in mt6358_enable_wov_phase2()
508 static int mt6358_disable_wov_phase2(struct mt6358_priv *priv) in mt6358_disable_wov_phase2()
511 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0xc000); in mt6358_disable_wov_phase2()
512 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_HPF_CFG0, in mt6358_disable_wov_phase2()
514 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_POSDIV_CFG0, in mt6358_disable_wov_phase2()
516 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0100); in mt6358_disable_wov_phase2()
517 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x006c); in mt6358_disable_wov_phase2()
518 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xa879); in mt6358_disable_wov_phase2()
519 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2323); in mt6358_disable_wov_phase2()
520 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0400); in mt6358_disable_wov_phase2()
521 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0x0000); in mt6358_disable_wov_phase2()
522 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x02d8); in mt6358_disable_wov_phase2()
523 regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0, in mt6358_disable_wov_phase2()
527 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON8, in mt6358_disable_wov_phase2()
529 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, in mt6358_disable_wov_phase2()
531 regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9829); in mt6358_disable_wov_phase2()
532 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_disable_wov_phase2()
535 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5); in mt6358_disable_wov_phase2()
536 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, in mt6358_disable_wov_phase2()
542 static int mt6358_get_wov(struct snd_kcontrol *kcontrol, in mt6358_get_wov()
548 ucontrol->value.integer.value[0] = priv->wov_enabled; in mt6358_get_wov()
552 static int mt6358_put_wov(struct snd_kcontrol *kcontrol, in mt6358_put_wov()
557 int enabled = ucontrol->value.integer.value[0]; in mt6358_put_wov()
559 if (priv->wov_enabled != enabled) { in mt6358_put_wov()
565 priv->wov_enabled = enabled; in mt6358_put_wov()
571 static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
572 static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0);
574 static const struct snd_kcontrol_new mt6358_snd_controls[] = {
591 SOC_SINGLE_BOOL_EXT("Wake-on-Voice Phase2 Switch", 0,
597 static const char * const lo_in_mux_map[] = {
601 static int lo_in_mux_map_value[] = {
605 static SOC_VALUE_ENUM_SINGLE_DECL(lo_in_mux_map_enum,
612 static const struct snd_kcontrol_new lo_in_mux_control =
625 static const char * const hp_in_mux_map[] = {
636 static int hp_in_mux_map_value[] = {
647 static SOC_VALUE_ENUM_SINGLE_DECL(hpl_in_mux_map_enum,
654 static const struct snd_kcontrol_new hpl_in_mux_control =
657 static SOC_VALUE_ENUM_SINGLE_DECL(hpr_in_mux_map_enum,
664 static const struct snd_kcontrol_new hpr_in_mux_control =
676 static const char * const rcv_in_mux_map[] = {
680 static int rcv_in_mux_map_value[] = {
687 static SOC_VALUE_ENUM_SINGLE_DECL(rcv_in_mux_map_enum,
694 static const struct snd_kcontrol_new rcv_in_mux_control =
698 static const char * const dac_in_mux_map[] = {
702 static int dac_in_mux_map_value[] = {
706 static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum,
713 static const struct snd_kcontrol_new dac_in_mux_control =
717 static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum,
724 static const struct snd_kcontrol_new aif_out_mux_control =
742 static const char * const mic_type_mux_map[] = {
751 static int mic_type_mux_map_value[] = {
760 static SOC_VALUE_ENUM_SINGLE_DECL(mic_type_mux_map_enum,
767 static const struct snd_kcontrol_new mic_type_mux_control =
779 static const char * const adc_left_mux_map[] = {
783 static int adc_mux_map_value[] = {
790 static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum,
797 static const struct snd_kcontrol_new adc_left_mux_control =
801 static const char * const adc_right_mux_map[] = {
805 static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum,
812 static const struct snd_kcontrol_new adc_right_mux_control =
824 static const char * const pga_mux_map[] = {
828 static int pga_mux_map_value[] = {
835 static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum,
842 static const struct snd_kcontrol_new pga_left_mux_control =
846 static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum,
853 static const struct snd_kcontrol_new pga_right_mux_control =
856 static int mt_clksq_event(struct snd_soc_dapm_widget *w, in mt_clksq_event()
860 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); in mt_clksq_event()
863 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); in mt_clksq_event()
868 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6, in mt_clksq_event()
879 static int mt_sgen_event(struct snd_soc_dapm_widget *w, in mt_sgen_event()
883 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); in mt_sgen_event()
886 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); in mt_sgen_event()
891 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006); in mt_sgen_event()
892 /* scrambler clock on enable */ in mt_sgen_event()
893 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1); in mt_sgen_event()
895 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003); in mt_sgen_event()
896 /* sdm fifo enable */ in mt_sgen_event()
897 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B); in mt_sgen_event()
899 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG0, in mt_sgen_event()
902 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG1, in mt_sgen_event()
908 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000); in mt_sgen_event()
909 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0); in mt_sgen_event()
918 static int mt_aif_in_event(struct snd_soc_dapm_widget *w, in mt_aif_in_event()
922 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); in mt_aif_in_event()
925 dev_info(priv->dev, "%s(), event 0x%x, rate %d\n", in mt_aif_in_event()
926 __func__, event, priv->dl_rate); in mt_aif_in_event()
933 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006); in mt_aif_in_event()
934 /* scrambler clock on enable */ in mt_aif_in_event()
935 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1); in mt_aif_in_event()
937 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003); in mt_aif_in_event()
938 /* sdm fifo enable */ in mt_aif_in_event()
939 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B); in mt_aif_in_event()
943 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000); in mt_aif_in_event()
944 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0); in mt_aif_in_event()
955 static int mtk_hp_enable(struct mt6358_priv *priv) in mtk_hp_enable()
957 /* Pull-down HPL/R to AVSS28_AUD */ in mtk_hp_enable()
960 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, in mtk_hp_enable()
964 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); in mtk_hp_enable()
966 /* Set HPR/HPL gain as minimum (~ -40dB) */ in mtk_hp_enable()
967 regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_40DB_REG); in mtk_hp_enable()
970 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); in mtk_hp_enable()
972 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); in mtk_hp_enable()
974 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); in mtk_hp_enable()
976 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); in mtk_hp_enable()
977 /* Enable NCP */ in mtk_hp_enable()
978 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); in mtk_hp_enable()
981 /* Enable cap-less LDOs (1.5V) */ in mtk_hp_enable()
982 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, in mtk_hp_enable()
984 /* Enable NV regulator (-1.2V) */ in mtk_hp_enable()
985 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); in mtk_hp_enable()
991 /* Disable headphone short-circuit protection */ in mtk_hp_enable()
992 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000); in mtk_hp_enable()
994 /* Enable IBIST */ in mtk_hp_enable()
995 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mtk_hp_enable()
998 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); in mtk_hp_enable()
1001 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mtk_hp_enable()
1003 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033); in mtk_hp_enable()
1005 /* Enable HP aux output stage */ in mtk_hp_enable()
1006 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x000c); in mtk_hp_enable()
1007 /* Enable HP aux feedback loop */ in mtk_hp_enable()
1008 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x003c); in mtk_hp_enable()
1009 /* Enable HP aux CMFB loop */ in mtk_hp_enable()
1010 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00); in mtk_hp_enable()
1011 /* Enable HP driver bias circuits */ in mtk_hp_enable()
1012 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0); in mtk_hp_enable()
1013 /* Enable HP driver core circuits */ in mtk_hp_enable()
1014 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0); in mtk_hp_enable()
1016 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00fc); in mtk_hp_enable()
1018 /* Enable HP main CMFB loop */ in mtk_hp_enable()
1019 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00); in mtk_hp_enable()
1021 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200); in mtk_hp_enable()
1025 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); in mtk_hp_enable()
1027 /* Enable HP main output stage */ in mtk_hp_enable()
1028 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00ff); in mtk_hp_enable()
1029 /* Enable HPR/L main output stage step by step */ in mtk_hp_enable()
1035 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); in mtk_hp_enable()
1040 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]); in mtk_hp_enable()
1043 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); in mtk_hp_enable()
1045 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3f03); in mtk_hp_enable()
1048 /* Enable AUD_CLK */ in mtk_hp_enable()
1049 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1); in mtk_hp_enable()
1050 /* Enable Audio DAC */ in mtk_hp_enable()
1051 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30ff); in mtk_hp_enable()
1052 /* Enable low-noise mode of DAC */ in mtk_hp_enable()
1053 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0xf201); in mtk_hp_enable()
1057 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x32ff); in mtk_hp_enable()
1059 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3aff); in mtk_hp_enable()
1061 /* Disable Pull-down HPL/R to AVSS28_AUD */ in mtk_hp_enable()
1067 static int mtk_hp_disable(struct mt6358_priv *priv) in mtk_hp_disable()
1069 /* Pull-down HPL/R to AVSS28_AUD */ in mtk_hp_disable()
1073 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, in mtk_hp_disable()
1076 /* Disable low-noise mode of DAC */ in mtk_hp_disable()
1077 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, in mtk_hp_disable()
1081 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, in mtk_hp_disable()
1085 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0); in mtk_hp_disable()
1088 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); in mtk_hp_disable()
1089 /* Enable HP aux output stage */ in mtk_hp_disable()
1090 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); in mtk_hp_disable()
1094 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL], in mtk_hp_disable()
1097 /* Enable HP aux feedback loop */ in mtk_hp_disable()
1098 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff); in mtk_hp_disable()
1107 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0); in mtk_hp_disable()
1109 /* Enable HP aux CMFB loop */ in mtk_hp_disable()
1110 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00); in mtk_hp_disable()
1113 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00); in mtk_hp_disable()
1116 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, in mtk_hp_disable()
1120 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, in mtk_hp_disable()
1124 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, in mtk_hp_disable()
1128 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000); in mtk_hp_disable()
1131 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, in mtk_hp_disable()
1135 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, in mtk_hp_disable()
1139 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12, in mtk_hp_disable()
1142 /* Disable NV regulator (-1.2V) */ in mtk_hp_disable()
1143 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0); in mtk_hp_disable()
1144 /* Disable cap-less LDOs (1.5V) */ in mtk_hp_disable()
1145 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, in mtk_hp_disable()
1148 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, in mtk_hp_disable()
1152 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON2, in mtk_hp_disable()
1156 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, in mtk_hp_disable()
1158 /* disable Pull-down HPL/R to AVSS28_AUD */ in mtk_hp_disable()
1164 static int mtk_hp_spk_enable(struct mt6358_priv *priv) in mtk_hp_spk_enable()
1166 /* Pull-down HPL/R to AVSS28_AUD */ in mtk_hp_spk_enable()
1169 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, in mtk_hp_spk_enable()
1173 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); in mtk_hp_spk_enable()
1175 /* Set HPR/HPL gain to -10dB */ in mtk_hp_spk_enable()
1176 regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_10DB_REG); in mtk_hp_spk_enable()
1179 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); in mtk_hp_spk_enable()
1181 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); in mtk_hp_spk_enable()
1183 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); in mtk_hp_spk_enable()
1185 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); in mtk_hp_spk_enable()
1186 /* Enable NCP */ in mtk_hp_spk_enable()
1187 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); in mtk_hp_spk_enable()
1190 /* Enable cap-less LDOs (1.5V) */ in mtk_hp_spk_enable()
1191 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, in mtk_hp_spk_enable()
1193 /* Enable NV regulator (-1.2V) */ in mtk_hp_spk_enable()
1194 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); in mtk_hp_spk_enable()
1200 /* Disable headphone short-circuit protection */ in mtk_hp_spk_enable()
1201 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000); in mtk_hp_spk_enable()
1203 /* Enable IBIST */ in mtk_hp_spk_enable()
1204 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mtk_hp_spk_enable()
1207 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); in mtk_hp_spk_enable()
1210 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mtk_hp_spk_enable()
1212 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033); in mtk_hp_spk_enable()
1214 /* Disable Pull-down HPL/R to AVSS28_AUD */ in mtk_hp_spk_enable()
1217 /* Enable HP driver bias circuits */ in mtk_hp_spk_enable()
1218 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0); in mtk_hp_spk_enable()
1219 /* Enable HP driver core circuits */ in mtk_hp_spk_enable()
1220 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0); in mtk_hp_spk_enable()
1221 /* Enable HP main CMFB loop */ in mtk_hp_spk_enable()
1222 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200); in mtk_hp_spk_enable()
1226 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); in mtk_hp_spk_enable()
1228 /* Enable HP main output stage */ in mtk_hp_spk_enable()
1229 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x0003); in mtk_hp_spk_enable()
1230 /* Enable HPR/L main output stage step by step */ in mtk_hp_spk_enable()
1233 /* Set LO gain as minimum (~ -40dB) */ in mtk_hp_spk_enable()
1234 regmap_write(priv->regmap, MT6358_ZCD_CON1, DL_GAIN_N_40DB_REG); in mtk_hp_spk_enable()
1238 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]); in mtk_hp_spk_enable()
1241 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0110); in mtk_hp_spk_enable()
1242 /* Enable LO driver bias circuits */ in mtk_hp_spk_enable()
1243 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0112); in mtk_hp_spk_enable()
1244 /* Enable LO driver core circuits */ in mtk_hp_spk_enable()
1245 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0113); in mtk_hp_spk_enable()
1248 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1, in mtk_hp_spk_enable()
1250 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] << in mtk_hp_spk_enable()
1252 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1, in mtk_hp_spk_enable()
1254 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] << in mtk_hp_spk_enable()
1257 /* Enable AUD_CLK */ in mtk_hp_spk_enable()
1258 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1); in mtk_hp_spk_enable()
1259 /* Enable Audio DAC */ in mtk_hp_spk_enable()
1260 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f9); in mtk_hp_spk_enable()
1261 /* Enable low-noise mode of DAC */ in mtk_hp_spk_enable()
1262 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0201); in mtk_hp_spk_enable()
1264 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x011b); in mtk_hp_spk_enable()
1265 /* Switch HPL/R MUX to Line-out */ in mtk_hp_spk_enable()
1266 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x35f9); in mtk_hp_spk_enable()
1271 static int mtk_hp_spk_disable(struct mt6358_priv *priv) in mtk_hp_spk_disable()
1274 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, in mtk_hp_spk_disable()
1277 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, in mtk_hp_spk_disable()
1281 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, in mtk_hp_spk_disable()
1285 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0); in mtk_hp_spk_disable()
1289 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL], in mtk_hp_spk_disable()
1293 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1, in mtk_hp_spk_disable()
1300 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0); in mtk_hp_spk_disable()
1303 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); in mtk_hp_spk_disable()
1304 /* Enable HP aux output stage */ in mtk_hp_spk_disable()
1305 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); in mtk_hp_spk_disable()
1307 /* Enable HP aux feedback loop */ in mtk_hp_spk_disable()
1308 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff); in mtk_hp_spk_disable()
1314 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, in mtk_hp_spk_disable()
1317 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, in mtk_hp_spk_disable()
1321 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, in mtk_hp_spk_disable()
1324 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, in mtk_hp_spk_disable()
1328 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, in mtk_hp_spk_disable()
1332 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12, in mtk_hp_spk_disable()
1334 /* Disable NV regulator (-1.2V) */ in mtk_hp_spk_disable()
1335 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0); in mtk_hp_spk_disable()
1336 /* Disable cap-less LDOs (1.5V) */ in mtk_hp_spk_disable()
1337 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 0x1055, 0x0); in mtk_hp_spk_disable()
1339 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x1, 0x1); in mtk_hp_spk_disable()
1342 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, in mtk_hp_spk_disable()
1344 /* disable Pull-down HPL/R to AVSS28_AUD */ in mtk_hp_spk_disable()
1350 static int mt_hp_event(struct snd_soc_dapm_widget *w, in mt_hp_event()
1354 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); in mt_hp_event()
1356 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_hp_event()
1359 dev_info(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n", in mt_hp_event()
1362 priv->dev_counter[device], in mt_hp_event()
1367 priv->dev_counter[device]++; in mt_hp_event()
1368 if (priv->dev_counter[device] > 1) in mt_hp_event()
1370 else if (priv->dev_counter[device] <= 0) in mt_hp_event()
1371 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d <= 0\n", in mt_hp_event()
1373 priv->dev_counter[device]); in mt_hp_event()
1375 priv->mux_select[MUX_HP_L] = mux; in mt_hp_event()
1383 priv->dev_counter[device]--; in mt_hp_event()
1384 if (priv->dev_counter[device] > 0) { in mt_hp_event()
1386 } else if (priv->dev_counter[device] < 0) { in mt_hp_event()
1387 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d < 0\n", in mt_hp_event()
1389 priv->dev_counter[device]); in mt_hp_event()
1390 priv->dev_counter[device] = 0; in mt_hp_event()
1394 if (priv->mux_select[MUX_HP_L] == HP_MUX_HP) in mt_hp_event()
1396 else if (priv->mux_select[MUX_HP_L] == HP_MUX_HPSPK) in mt_hp_event()
1399 priv->mux_select[MUX_HP_L] = mux; in mt_hp_event()
1408 static int mt_rcv_event(struct snd_soc_dapm_widget *w, in mt_rcv_event()
1412 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); in mt_rcv_event()
1415 dev_info(priv->dev, "%s(), event 0x%x, mux %u\n", in mt_rcv_event()
1418 dapm_kcontrol_get_value(w->kcontrols[0])); in mt_rcv_event()
1423 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); in mt_rcv_event()
1426 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); in mt_rcv_event()
1428 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); in mt_rcv_event()
1430 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); in mt_rcv_event()
1432 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); in mt_rcv_event()
1433 /* Enable NCP */ in mt_rcv_event()
1434 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); in mt_rcv_event()
1437 /* Enable cap-less LDOs (1.5V) */ in mt_rcv_event()
1438 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, in mt_rcv_event()
1440 /* Enable NV regulator (-1.2V) */ in mt_rcv_event()
1441 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); in mt_rcv_event()
1447 /* Disable handset short-circuit protection */ in mt_rcv_event()
1448 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0010); in mt_rcv_event()
1450 /* Enable IBIST */ in mt_rcv_event()
1451 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mt_rcv_event()
1453 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); in mt_rcv_event()
1456 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mt_rcv_event()
1458 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0090); in mt_rcv_event()
1461 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000); in mt_rcv_event()
1464 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); in mt_rcv_event()
1466 /* Enable HS driver bias circuits */ in mt_rcv_event()
1467 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0092); in mt_rcv_event()
1468 /* Enable HS driver core circuits */ in mt_rcv_event()
1469 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0093); in mt_rcv_event()
1471 /* Enable AUD_CLK */ in mt_rcv_event()
1472 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, in mt_rcv_event()
1475 /* Enable Audio DAC */ in mt_rcv_event()
1476 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x0009); in mt_rcv_event()
1477 /* Enable low-noise mode of DAC */ in mt_rcv_event()
1478 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0001); in mt_rcv_event()
1480 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x009b); in mt_rcv_event()
1484 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, in mt_rcv_event()
1489 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, in mt_rcv_event()
1493 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, in mt_rcv_event()
1497 regmap_write(priv->regmap, MT6358_ZCD_CON3, DL_GAIN_N_40DB); in mt_rcv_event()
1500 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, in mt_rcv_event()
1504 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, in mt_rcv_event()
1508 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, in mt_rcv_event()
1511 /* Enable HP main CMFB Switch */ in mt_rcv_event()
1512 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, in mt_rcv_event()
1516 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12, in mt_rcv_event()
1519 /* Disable NV regulator (-1.2V) */ in mt_rcv_event()
1520 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, in mt_rcv_event()
1522 /* Disable cap-less LDOs (1.5V) */ in mt_rcv_event()
1523 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, in mt_rcv_event()
1526 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, in mt_rcv_event()
1536 static int mt_aif_out_event(struct snd_soc_dapm_widget *w, in mt_aif_out_event()
1540 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); in mt_aif_out_event()
1543 dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n", in mt_aif_out_event()
1544 __func__, event, priv->ul_rate); in mt_aif_out_event()
1560 static int mt_adc_supply_event(struct snd_soc_dapm_widget *w, in mt_adc_supply_event()
1564 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); in mt_adc_supply_event()
1567 dev_dbg(priv->dev, "%s(), event 0x%x\n", in mt_adc_supply_event()
1572 /* Enable audio ADC CLKGEN */ in mt_adc_supply_event()
1573 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, in mt_adc_supply_event()
1576 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3, in mt_adc_supply_event()
1578 /* Enable LCLDO_ENC 1P8V */ in mt_adc_supply_event()
1579 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, in mt_adc_supply_event()
1582 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, in mt_adc_supply_event()
1587 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, in mt_adc_supply_event()
1590 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, in mt_adc_supply_event()
1594 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3, 0x0000); in mt_adc_supply_event()
1596 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, in mt_adc_supply_event()
1606 static int mt6358_amic_enable(struct mt6358_priv *priv) in mt6358_amic_enable()
1608 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE]; in mt6358_amic_enable()
1609 unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L]; in mt6358_amic_enable()
1610 unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R]; in mt6358_amic_enable()
1612 dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n", in mt6358_amic_enable()
1617 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); in mt6358_amic_enable()
1618 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); in mt6358_amic_enable()
1619 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060); in mt6358_amic_enable()
1620 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2061); in mt6358_amic_enable()
1621 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG1, 0x0100); in mt6358_amic_enable()
1629 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, in mt6358_amic_enable()
1633 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, in mt6358_amic_enable()
1637 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, in mt6358_amic_enable()
1641 /* Enable MICBIAS0, MISBIAS0 = 1P9V */ in mt6358_amic_enable()
1642 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, in mt6358_amic_enable()
1648 /* Enable MICBIAS1, MISBIAS1 = 2P6V */ in mt6358_amic_enable()
1650 regmap_write(priv->regmap, in mt6358_amic_enable()
1653 regmap_write(priv->regmap, in mt6358_amic_enable()
1659 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, in mt6358_amic_enable()
1661 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_amic_enable()
1665 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, in mt6358_amic_enable()
1667 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_amic_enable()
1673 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, in mt6358_amic_enable()
1677 /* L preamplifier enable */ in mt6358_amic_enable()
1678 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, in mt6358_amic_enable()
1684 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, in mt6358_amic_enable()
1689 /* L ADC input sel : L PGA. Enable audio L ADC */ in mt6358_amic_enable()
1690 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, in mt6358_amic_enable()
1694 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, in mt6358_amic_enable()
1701 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_amic_enable()
1705 /* R preamplifier enable */ in mt6358_amic_enable()
1706 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_amic_enable()
1712 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_amic_enable()
1717 /* R ADC input sel : R PGA. Enable audio R ADC */ in mt6358_amic_enable()
1718 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_amic_enable()
1722 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_amic_enable()
1730 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, in mt6358_amic_enable()
1733 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_amic_enable()
1737 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON3, in mt6358_amic_enable()
1745 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0000); in mt6358_amic_enable()
1748 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0001); in mt6358_amic_enable()
1753 static void mt6358_amic_disable(struct mt6358_priv *priv) in mt6358_amic_disable()
1755 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE]; in mt6358_amic_disable()
1756 unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L]; in mt6358_amic_disable()
1757 unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R]; in mt6358_amic_disable()
1759 dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n", in mt6358_amic_disable()
1763 regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, in mt6358_amic_disable()
1770 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, in mt6358_amic_disable()
1773 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, in mt6358_amic_disable()
1776 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, in mt6358_amic_disable()
1780 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, in mt6358_amic_disable()
1784 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_amic_disable()
1787 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_amic_disable()
1790 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_amic_disable()
1794 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_amic_disable()
1799 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000); in mt6358_amic_disable()
1802 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10, in mt6358_amic_disable()
1807 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060); in mt6358_amic_disable()
1809 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); in mt6358_amic_disable()
1811 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); in mt6358_amic_disable()
1813 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); in mt6358_amic_disable()
1817 static int mt6358_dmic_enable(struct mt6358_priv *priv) in mt6358_dmic_enable()
1819 dev_info(priv->dev, "%s()\n", __func__); in mt6358_dmic_enable()
1822 /* Enable MICBIAS0, MISBIAS0 = 1P9V */ in mt6358_dmic_enable()
1823 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0021); in mt6358_dmic_enable()
1826 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10, in mt6358_dmic_enable()
1829 /* DMIC enable */ in mt6358_dmic_enable()
1830 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0005); in mt6358_dmic_enable()
1836 if (priv->dmic_one_wire_mode) in mt6358_dmic_enable()
1837 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0400); in mt6358_dmic_enable()
1839 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0080); in mt6358_dmic_enable()
1842 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0003); in mt6358_dmic_enable()
1850 static void mt6358_dmic_disable(struct mt6358_priv *priv) in mt6358_dmic_disable()
1852 dev_info(priv->dev, "%s()\n", __func__); in mt6358_dmic_disable()
1855 regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, in mt6358_dmic_disable()
1862 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0000); in mt6358_dmic_disable()
1866 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0001); in mt6358_dmic_disable()
1869 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10, in mt6358_dmic_disable()
1873 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000); in mt6358_dmic_disable()
1876 static void mt6358_restore_pga(struct mt6358_priv *priv) in mt6358_restore_pga()
1880 gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1]; in mt6358_restore_pga()
1881 gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2]; in mt6358_restore_pga()
1883 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, in mt6358_restore_pga()
1886 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_restore_pga()
1891 static int mt_mic_type_event(struct snd_soc_dapm_widget *w, in mt_mic_type_event()
1895 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); in mt_mic_type_event()
1897 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_mic_type_event()
1899 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n", in mt_mic_type_event()
1904 priv->mux_select[MUX_MIC_TYPE] = mux; in mt_mic_type_event()
1919 switch (priv->mux_select[MUX_MIC_TYPE]) { in mt_mic_type_event()
1928 priv->mux_select[MUX_MIC_TYPE] = mux; in mt_mic_type_event()
1937 static int mt_adc_l_event(struct snd_soc_dapm_widget *w, in mt_adc_l_event()
1941 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); in mt_adc_l_event()
1943 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_adc_l_event()
1945 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", in mt_adc_l_event()
1948 priv->mux_select[MUX_ADC_L] = mux; in mt_adc_l_event()
1953 static int mt_adc_r_event(struct snd_soc_dapm_widget *w, in mt_adc_r_event()
1957 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); in mt_adc_r_event()
1959 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_adc_r_event()
1961 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", in mt_adc_r_event()
1964 priv->mux_select[MUX_ADC_R] = mux; in mt_adc_r_event()
1969 static int mt_pga_left_event(struct snd_soc_dapm_widget *w, in mt_pga_left_event()
1973 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); in mt_pga_left_event()
1975 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_pga_left_event()
1977 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", in mt_pga_left_event()
1980 priv->mux_select[MUX_PGA_L] = mux; in mt_pga_left_event()
1985 static int mt_pga_right_event(struct snd_soc_dapm_widget *w, in mt_pga_right_event()
1989 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); in mt_pga_right_event()
1991 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_pga_right_event()
1993 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", in mt_pga_right_event()
1996 priv->mux_select[MUX_PGA_R] = mux; in mt_pga_right_event()
2001 static int mt_delay_250_event(struct snd_soc_dapm_widget *w, in mt_delay_250_event()
2020 static const struct snd_soc_dapm_widget mt6358_dapm_widgets[] = {
2138 SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6358_AFE_SGEN_CFG0,
2200 static const struct snd_soc_dapm_route mt6358_dapm_routes[] = {
2276 {"SGEN DL", NULL, "SGEN DL Enable"},
2313 static int mt6358_codec_dai_hw_params(struct snd_pcm_substream *substream, in mt6358_codec_dai_hw_params()
2317 struct snd_soc_component *cmpnt = dai->component; in mt6358_codec_dai_hw_params()
2321 dev_info(priv->dev, "%s(), substream->stream %d, rate %d, number %d\n", in mt6358_codec_dai_hw_params()
2323 substream->stream, in mt6358_codec_dai_hw_params()
2325 substream->number); in mt6358_codec_dai_hw_params()
2327 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in mt6358_codec_dai_hw_params()
2328 priv->dl_rate = rate; in mt6358_codec_dai_hw_params()
2329 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) in mt6358_codec_dai_hw_params()
2330 priv->ul_rate = rate; in mt6358_codec_dai_hw_params()
2335 static const struct snd_soc_dai_ops mt6358_codec_dai_ops = {
2346 static struct snd_soc_dai_driver mt6358_dai_driver[] = {
2348 .name = "mt6358-snd-codec-aif1",
2372 static void mt6358_codec_init_reg(struct mt6358_priv *priv) in mt6358_codec_init_reg()
2375 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, in mt6358_codec_init_reg()
2378 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, in mt6358_codec_init_reg()
2382 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, in mt6358_codec_init_reg()
2386 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, in mt6358_codec_init_reg()
2390 /* accdet s/w enable */ in mt6358_codec_init_reg()
2391 regmap_update_bits(priv->regmap, MT6358_ACCDET_CON13, in mt6358_codec_init_reg()
2395 regmap_write(priv->regmap, MT6358_DRV_CON3, 0x8888); in mt6358_codec_init_reg()
2402 static int mt6358_codec_probe(struct snd_soc_component *cmpnt) in mt6358_codec_probe()
2407 snd_soc_component_init_regmap(cmpnt, priv->regmap); in mt6358_codec_probe()
2411 priv->avdd_reg = devm_regulator_get(priv->dev, "Avdd"); in mt6358_codec_probe()
2412 if (IS_ERR(priv->avdd_reg)) { in mt6358_codec_probe()
2413 dev_err(priv->dev, "%s() have no Avdd supply", __func__); in mt6358_codec_probe()
2414 return PTR_ERR(priv->avdd_reg); in mt6358_codec_probe()
2417 ret = regulator_enable(priv->avdd_reg); in mt6358_codec_probe()
2424 static const struct snd_soc_component_driver mt6358_soc_component_driver = {
2434 static void mt6358_parse_dt(struct mt6358_priv *priv) in mt6358_parse_dt()
2437 struct device *dev = priv->dev; in mt6358_parse_dt()
2439 ret = of_property_read_u32(dev->of_node, "mediatek,dmic-mode", in mt6358_parse_dt()
2440 &priv->dmic_one_wire_mode); in mt6358_parse_dt()
2442 dev_warn(priv->dev, "%s() failed to read dmic-mode\n", in mt6358_parse_dt()
2444 priv->dmic_one_wire_mode = 0; in mt6358_parse_dt()
2448 static int mt6358_platform_driver_probe(struct platform_device *pdev) in mt6358_platform_driver_probe()
2451 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent); in mt6358_platform_driver_probe()
2453 priv = devm_kzalloc(&pdev->dev, in mt6358_platform_driver_probe()
2457 return -ENOMEM; in mt6358_platform_driver_probe()
2459 dev_set_drvdata(&pdev->dev, priv); in mt6358_platform_driver_probe()
2461 priv->dev = &pdev->dev; in mt6358_platform_driver_probe()
2463 priv->regmap = mt6397->regmap; in mt6358_platform_driver_probe()
2464 if (IS_ERR(priv->regmap)) in mt6358_platform_driver_probe()
2465 return PTR_ERR(priv->regmap); in mt6358_platform_driver_probe()
2469 dev_info(priv->dev, "%s(), dev name %s\n", in mt6358_platform_driver_probe()
2470 __func__, dev_name(&pdev->dev)); in mt6358_platform_driver_probe()
2472 return devm_snd_soc_register_component(&pdev->dev, in mt6358_platform_driver_probe()
2478 static const struct of_device_id mt6358_of_match[] = {
2479 {.compatible = "mediatek,mt6358-sound",},
2484 static struct platform_driver mt6358_platform_driver = {
2486 .name = "mt6358-sound",