Lines Matching +full:0 +full:x07
10 #define MAX98926_CHIP_VERSION 0x40
11 #define MAX98926_CHIP_VERSION1 0x50
13 #define MAX98926_VBAT_DATA 0x00
14 #define MAX98926_VBST_DATA 0x01
15 #define MAX98926_LIVE_STATUS0 0x02
16 #define MAX98926_LIVE_STATUS1 0x03
17 #define MAX98926_LIVE_STATUS2 0x04
18 #define MAX98926_STATE0 0x05
19 #define MAX98926_STATE1 0x06
20 #define MAX98926_STATE2 0x07
21 #define MAX98926_FLAG0 0x08
22 #define MAX98926_FLAG1 0x09
23 #define MAX98926_FLAG2 0x0A
24 #define MAX98926_IRQ_ENABLE0 0x0B
25 #define MAX98926_IRQ_ENABLE1 0x0C
26 #define MAX98926_IRQ_ENABLE2 0x0D
27 #define MAX98926_IRQ_CLEAR0 0x0E
28 #define MAX98926_IRQ_CLEAR1 0x0F
29 #define MAX98926_IRQ_CLEAR2 0x10
30 #define MAX98926_MAP0 0x11
31 #define MAX98926_MAP1 0x12
32 #define MAX98926_MAP2 0x13
33 #define MAX98926_MAP3 0x14
34 #define MAX98926_MAP4 0x15
35 #define MAX98926_MAP5 0x16
36 #define MAX98926_MAP6 0x17
37 #define MAX98926_MAP7 0x18
38 #define MAX98926_MAP8 0x19
39 #define MAX98926_DAI_CLK_MODE1 0x1A
40 #define MAX98926_DAI_CLK_MODE2 0x1B
41 #define MAX98926_DAI_CLK_DIV_M_MSBS 0x1C
42 #define MAX98926_DAI_CLK_DIV_M_LSBS 0x1D
43 #define MAX98926_DAI_CLK_DIV_N_MSBS 0x1E
44 #define MAX98926_DAI_CLK_DIV_N_LSBS 0x1F
45 #define MAX98926_FORMAT 0x20
46 #define MAX98926_TDM_SLOT_SELECT 0x21
47 #define MAX98926_DOUT_CFG_VMON 0x22
48 #define MAX98926_DOUT_CFG_IMON 0x23
49 #define MAX98926_DOUT_CFG_VBAT 0x24
50 #define MAX98926_DOUT_CFG_VBST 0x25
51 #define MAX98926_DOUT_CFG_FLAG 0x26
52 #define MAX98926_DOUT_HIZ_CFG1 0x27
53 #define MAX98926_DOUT_HIZ_CFG2 0x28
54 #define MAX98926_DOUT_HIZ_CFG3 0x29
55 #define MAX98926_DOUT_HIZ_CFG4 0x2A
56 #define MAX98926_DOUT_DRV_STRENGTH 0x2B
57 #define MAX98926_FILTERS 0x2C
58 #define MAX98926_GAIN 0x2D
59 #define MAX98926_GAIN_RAMPING 0x2E
60 #define MAX98926_SPK_AMP 0x2F
61 #define MAX98926_THRESHOLD 0x30
62 #define MAX98926_ALC_ATTACK 0x31
63 #define MAX98926_ALC_ATTEN_RLS 0x32
64 #define MAX98926_ALC_HOLD_RLS 0x33
65 #define MAX98926_ALC_CONFIGURATION 0x34
66 #define MAX98926_BOOST_CONVERTER 0x35
67 #define MAX98926_BLOCK_ENABLE 0x36
68 #define MAX98926_CONFIGURATION 0x37
69 #define MAX98926_GLOBAL_ENABLE 0x38
70 #define MAX98926_BOOST_LIMITER 0x3A
71 #define MAX98926_VERSION 0xFF
85 #define MAX98926_PDM_SOURCE_0_SHIFT 0
86 #define MAX98926_PDM_SOURCE_0_MASK (1<<0)
116 #define MAX98926_ACLP_STATUS_MASK (1<<0)
117 #define MAX98926_ACLP_STATUS_SHIFT 0
139 #define MAX98926_VMONOVFL_STATUS_MASK (1<<0)
140 #define MAX98926_VMONOVFL_STATUS_SHIFT 0
153 #define MAX98926_THERMSHDN_BGN_STATE_MASK (1<<0)
154 #define MAX98926_THERMSHDN_BGN_STATE_SHIFT 0
173 #define MAX98926_ALCP_STATE_MASK (1<<0)
174 #define MAX98926_ALCP_STATE_SHIFT 0
196 #define MAX98926_VMONOVFL_STATE_MASK (1<<0)
197 #define MAX98926_VMONOVFL_STATE_SHIFT 0
210 #define MAX98926_THERMSHDN_BGN_FLAG_MASK (1<<0)
211 #define MAX98926_THERMSHDN_BGN_FLAG_SHIFT 0
230 #define MAX98926_ALCP_FLAG_MASK (1<<0)
231 #define MAX98926_ALCP_FLAG_SHIFT 0
253 #define MAX98926_VMONOVFL_FLAG_MASK (1<<0)
254 #define MAX98926_VMONOVFL_FLAG_SHIFT 0
267 #define MAX98926_THERMSHDN_BGN_EN_MASK (1<<0)
268 #define MAX98926_THERMSHDN_BGN_EN_SHIFT 0
287 #define MAX98926_ALCP_EN_MASK (1<<0)
288 #define MAX98926_ALCP_EN_SHIFT 0
310 #define MAX98926_VMONOVFL_EN_MASK (1<<0)
311 #define MAX98926_VMONOVFL_EN_SHIFT 0
324 #define MAX98926_THERMSHDN_BGN_CLR_MASK (1<<0)
325 #define MAX98926_THERMSHDN_BGN_CLR_SHIFT 0
344 #define MAX98926_ALCP_CLR_MASK (1<<0)
345 #define MAX98926_ALCP_CLR_SHIFT 0
367 #define MAX98926_VMONOVFL_CLR_MASK (1<<0)
368 #define MAX98926_VMONOVFL_CLR_SHIFT 0
375 #define MAX98926_ER_THERMWARN_MAP_MASK (0x07<<4)
383 #define MAX98926_ER_ALCMUT_MAP_MASK (0x07<<4)
389 #define MAX98926_ER_ALCP_MAP_MASK (0x07<<0)
390 #define MAX98926_ER_ALCP_MAP_SHIFT 0
397 #define MAX98926_ER_ALCINFH_MAP_MASK (0x07<<4)
403 #define MAX98926_ER_ALCACT_MAP_MASK (0x07<<0)
404 #define MAX98926_ER_ALCACT_MAP_SHIFT 0
411 #define MAX98926_ER_SPKCURNT_MAP_MASK (0x07<<4)
422 #define MAX98926_ER_IMONOVFL_MAP_MASK (0x07<<4)
428 #define MAX98926_ER_VMONOVFL_MAP_MASK (0x07<<0)
429 #define MAX98926_ER_VMONOVFL_MAP_SHIFT 0
436 #define MAX98926_ER_VBSTOVFL_MAP_MASK (0x07<<4)
442 #define MAX98926_ER_VBATOVFL_MAP_MASK (0x07<<0)
443 #define MAX98926_ER_VBATOVFL_MAP_SHIFT 0
450 #define MAX98926_ER_INVALSLOT_MAP_MASK (0x07<<4)
456 #define MAX98926_ER_SLOTCNFLT_MAP_MASK (0x07<<0)
457 #define MAX98926_ER_SLOTCNFLT_MAP_SHIFT 0
464 #define MAX98926_ER_SLOTOVRN_MAP_MASK (0x07<<0)
465 #define MAX98926_ER_SLOTOVRN_MAP_SHIFT 0
472 #define MAX98926_MDLL_MULT_MASK (0x0F<<0)
473 #define MAX98926_MDLL_MULT_SHIFT 0
480 #define MAX98926_DAI_SR_MASK (0x0F<<4)
486 #define MAX98926_DAI_BSEL_MASK (0x07<<0)
487 #define MAX98926_DAI_BSEL_SHIFT 0
490 #define MAX98926_DAI_BSEL_32 (0 << MAX98926_DAI_BSEL_SHIFT)
496 #define MAX98926_DAI_M_MSBS_MASK (0xFF<<0)
497 #define MAX98926_DAI_M_MSBS_SHIFT 0
501 #define MAX98926_DAI_M_LSBS_MASK (0xFF<<0)
502 #define MAX98926_DAI_M_LSBS_SHIFT 0
506 #define MAX98926_DAI_N_MSBS_MASK (0x7F<<0)
507 #define MAX98926_DAI_N_MSBS_SHIFT 0
511 #define MAX98926_DAI_N_LSBS_MASK (0xFF<<0)
512 #define MAX98926_DAI_N_LSBS_SHIFT 0
516 #define MAX98926_DAI_CHANSZ_MASK (0x03<<6)
534 #define MAX98926_DAI_TDM_MASK (1<<0)
535 #define MAX98926_DAI_TDM_SHIFT 0
549 #define MAX98926_DAI_INR_SOURCE_MASK (0x07<<3)
552 #define MAX98926_DAI_INL_SOURCE_MASK (0x07<<0)
553 #define MAX98926_DAI_INL_SOURCE_SHIFT 0
560 #define MAX98926_DAI_VMON_SLOT_MASK (0x1F<<0)
561 #define MAX98926_DAI_VMON_SLOT_SHIFT 0
564 #define MAX98926_DAI_VMON_SLOT_00_01 (0 << MAX98926_DAI_VMON_SLOT_SHIFT)
600 #define MAX98926_DAI_IMON_SLOT_MASK (0x1F<<0)
601 #define MAX98926_DAI_IMON_SLOT_SHIFT 0
604 #define MAX98926_DAI_IMON_SLOT_00_01 (0 << MAX98926_DAI_IMON_SLOT_SHIFT)
637 #define MAX98926_DAI_INTERLEAVE_SLOT_MASK (0x1F<<0)
638 #define MAX98926_DAI_INTERLEAVE_SLOT_SHIFT 0
645 #define MAX98926_DAI_VBST_SLOT_MASK (0x1F<<0)
646 #define MAX98926_DAI_VBST_SLOT_SHIFT 0
653 #define MAX98926_DAI_FLAG_SLOT_MASK (0x1F<<0)
654 #define MAX98926_DAI_FLAG_SLOT_SHIFT 0
658 #define MAX98926_DAI_SLOT_HIZ_CFG1_MASK (0xFF<<0)
659 #define MAX98926_DAI_SLOT_HIZ_CFG1_SHIFT 0
663 #define MAX98926_DAI_SLOT_HIZ_CFG2_MASK (0xFF<<0)
664 #define MAX98926_DAI_SLOT_HIZ_CFG2_SHIFT 0
668 #define MAX98926_DAI_SLOT_HIZ_CFG3_MASK (0xFF<<0)
669 #define MAX98926_DAI_SLOT_HIZ_CFG3_SHIFT 0
673 #define MAX98926_DAI_SLOT_HIZ_CFG4_MASK (0xFF<<0)
674 #define MAX98926_DAI_SLOT_HIZ_CFG4_SHIFT 0
678 #define MAX98926_DAI_OUT_DRIVE_MASK (0x03<<0)
679 #define MAX98926_DAI_OUT_DRIVE_SHIFT 0
695 #define MAX98926_DAC_HPF_MASK (0x07<<0)
696 #define MAX98926_DAC_HPF_SHIFT 0
698 #define MAX98926_DAC_HPF_DISABLE (0 << MAX98926_DAC_HPF_SHIFT)
706 #define MAX98926_DAC_IN_SEL_MASK (0x03<<5)
709 #define MAX98926_SPK_GAIN_MASK (0x1F<<0)
710 #define MAX98926_SPK_GAIN_SHIFT 0
713 #define MAX98926_DAC_IN_SEL_LEFT_DAI (0 << MAX98926_DAC_IN_SEL_SHIFT)
722 #define MAX98926_SPK_ZCD_EN_MASK (1<<0)
723 #define MAX98926_SPK_ZCD_EN_SHIFT 0
727 #define MAX98926_SPK_MODE_MASK (1<<0)
728 #define MAX98926_SPK_MODE_SHIFT 0
738 #define MAX98926_ALC_TH_MASK (0x1F<<0)
739 #define MAX98926_ALC_TH_SHIFT 0
743 #define MAX98926_ALC_ATK_STEP_MASK (0x0F<<4)
746 #define MAX98926_ALC_ATK_RATE_MASK (0x7<<0)
747 #define MAX98926_ALC_ATK_RATE_SHIFT 0
751 #define MAX98926_ALC_MAX_ATTEN_MASK (0x0F<<4)
754 #define MAX98926_ALC_RLS_RATE_MASK (0x7<<0)
755 #define MAX98926_ALC_RLS_RATE_SHIFT 0
759 #define MAX98926_ALC_RLS_TGR_MASK (1<<0)
760 #define MAX98926_ALC_RLS_TGR_SHIFT 0
767 #define MAX98926_ALC_MUTE_DLY_MASK (0x07<<4)
770 #define MAX98926_ALC_RLS_DBT_MASK (0x07<<0)
771 #define MAX98926_ALC_RLS_DBT_SHIFT 0
778 #define MAX98926_BST_PHASE_MASK (0x03<<4)
781 #define MAX98926_BST_SKIP_MODE_MASK (0x03<<0)
782 #define MAX98926_BST_SKIP_MODE_SHIFT 0
807 #define MAX98926_ADC_VMON_EN_MASK (1<<0)
808 #define MAX98926_ADC_VMON_EN_SHIFT 0
812 #define MAX98926_BST_VOUT_MASK (0x0F<<4)
815 #define MAX98926_THERMWARN_LEVEL_MASK (0x03<<2)
818 #define MAX98926_WATCH_TIME_MASK (0x03<<0)
819 #define MAX98926_WATCH_TIME_SHIFT 0
828 #define MAX98926_BST_ILIM_MASK (0xF<<4)
833 #define MAX98926_REV_ID_MASK (0xFF<<0)
834 #define MAX98926_REV_ID_SHIFT 0