Lines Matching +full:0 +full:x07
11 #define MAX98925_VERSION 0x51
12 #define MAX98925_VERSION1 0x80
13 #define MAX98925_VBAT_DATA 0x00
14 #define MAX98925_VBST_DATA 0x01
15 #define MAX98925_LIVE_STATUS0 0x02
16 #define MAX98925_LIVE_STATUS1 0x03
17 #define MAX98925_LIVE_STATUS2 0x04
18 #define MAX98925_STATE0 0x05
19 #define MAX98925_STATE1 0x06
20 #define MAX98925_STATE2 0x07
21 #define MAX98925_FLAG0 0x08
22 #define MAX98925_FLAG1 0x09
23 #define MAX98925_FLAG2 0x0A
24 #define MAX98925_IRQ_ENABLE0 0x0B
25 #define MAX98925_IRQ_ENABLE1 0x0C
26 #define MAX98925_IRQ_ENABLE2 0x0D
27 #define MAX98925_IRQ_CLEAR0 0x0E
28 #define MAX98925_IRQ_CLEAR1 0x0F
29 #define MAX98925_IRQ_CLEAR2 0x10
30 #define MAX98925_MAP0 0x11
31 #define MAX98925_MAP1 0x12
32 #define MAX98925_MAP2 0x13
33 #define MAX98925_MAP3 0x14
34 #define MAX98925_MAP4 0x15
35 #define MAX98925_MAP5 0x16
36 #define MAX98925_MAP6 0x17
37 #define MAX98925_MAP7 0x18
38 #define MAX98925_MAP8 0x19
39 #define MAX98925_DAI_CLK_MODE1 0x1A
40 #define MAX98925_DAI_CLK_MODE2 0x1B
41 #define MAX98925_DAI_CLK_DIV_M_MSBS 0x1C
42 #define MAX98925_DAI_CLK_DIV_M_LSBS 0x1D
43 #define MAX98925_DAI_CLK_DIV_N_MSBS 0x1E
44 #define MAX98925_DAI_CLK_DIV_N_LSBS 0x1F
45 #define MAX98925_FORMAT 0x20
46 #define MAX98925_TDM_SLOT_SELECT 0x21
47 #define MAX98925_DOUT_CFG_VMON 0x22
48 #define MAX98925_DOUT_CFG_IMON 0x23
49 #define MAX98925_DOUT_CFG_VBAT 0x24
50 #define MAX98925_DOUT_CFG_VBST 0x25
51 #define MAX98925_DOUT_CFG_FLAG 0x26
52 #define MAX98925_DOUT_HIZ_CFG1 0x27
53 #define MAX98925_DOUT_HIZ_CFG2 0x28
54 #define MAX98925_DOUT_HIZ_CFG3 0x29
55 #define MAX98925_DOUT_HIZ_CFG4 0x2A
56 #define MAX98925_DOUT_DRV_STRENGTH 0x2B
57 #define MAX98925_FILTERS 0x2C
58 #define MAX98925_GAIN 0x2D
59 #define MAX98925_GAIN_RAMPING 0x2E
60 #define MAX98925_SPK_AMP 0x2F
61 #define MAX98925_THRESHOLD 0x30
62 #define MAX98925_ALC_ATTACK 0x31
63 #define MAX98925_ALC_ATTEN_RLS 0x32
64 #define MAX98925_ALC_HOLD_RLS 0x33
65 #define MAX98925_ALC_CONFIGURATION 0x34
66 #define MAX98925_BOOST_CONVERTER 0x35
67 #define MAX98925_BLOCK_ENABLE 0x36
68 #define MAX98925_CONFIGURATION 0x37
69 #define MAX98925_GLOBAL_ENABLE 0x38
70 #define MAX98925_BOOST_LIMITER 0x3A
71 #define MAX98925_REV_VERSION 0xFF
101 #define M98925_ACLP_STATUS_MASK (1<<0)
102 #define M98925_ACLP_STATUS_SHIFT 0
124 #define M98925_VMONOVFL_STATUS_MASK (1<<0)
125 #define M98925_VMONOVFL_STATUS_SHIFT 0
138 #define M98925_THERMSHDN_BGN_STATE_MASK (1<<0)
139 #define M98925_THERMSHDN_BGN_STATE_SHIFT 0
158 #define M98925_ALCP_STATE_MASK (1<<0)
159 #define M98925_ALCP_STATE_SHIFT 0
181 #define M98925_VMONOVFL_STATE_MASK (1<<0)
182 #define M98925_VMONOVFL_STATE_SHIFT 0
195 #define M98925_THERMSHDN_BGN_FLAG_MASK (1<<0)
196 #define M98925_THERMSHDN_BGN_FLAG_SHIFT 0
215 #define M98925_ALCP_FLAG_MASK (1<<0)
216 #define M98925_ALCP_FLAG_SHIFT 0
238 #define M98925_VMONOVFL_FLAG_MASK (1<<0)
239 #define M98925_VMONOVFL_FLAG_SHIFT 0
252 #define M98925_THERMSHDN_BGN_EN_MASK (1<<0)
253 #define M98925_THERMSHDN_BGN_EN_SHIFT 0
272 #define M98925_ALCP_EN_MASK (1<<0)
273 #define M98925_ALCP_EN_SHIFT 0
295 #define M98925_VMONOVFL_EN_MASK (1<<0)
296 #define M98925_VMONOVFL_EN_SHIFT 0
309 #define M98925_THERMSHDN_BGN_CLR_MASK (1<<0)
310 #define M98925_THERMSHDN_BGN_CLR_SHIFT 0
329 #define M98925_ALCP_CLR_MASK (1<<0)
330 #define M98925_ALCP_CLR_SHIFT 0
352 #define M98925_VMONOVFL_CLR_MASK (1<<0)
353 #define M98925_VMONOVFL_CLR_SHIFT 0
360 #define M98925_ER_THERMWARN_MAP_MASK (0x07<<4)
368 #define M98925_ER_ALCMUT_MAP_MASK (0x07<<4)
374 #define M98925_ER_ALCP_MAP_MASK (0x07<<0)
375 #define M98925_ER_ALCP_MAP_SHIFT 0
382 #define M98925_ER_ALCINFH_MAP_MASK (0x07<<4)
388 #define M98925_ER_ALCACT_MAP_MASK (0x07<<0)
389 #define M98925_ER_ALCACT_MAP_SHIFT 0
396 #define M98925_ER_SPKCURNT_MAP_MASK (0x07<<4)
407 #define M98925_ER_IMONOVFL_MAP_MASK (0x07<<4)
413 #define M98925_ER_VMONOVFL_MAP_MASK (0x07<<0)
414 #define M98925_ER_VMONOVFL_MAP_SHIFT 0
421 #define M98925_ER_VBSTOVFL_MAP_MASK (0x07<<4)
427 #define M98925_ER_VBATOVFL_MAP_MASK (0x07<<0)
428 #define M98925_ER_VBATOVFL_MAP_SHIFT 0
435 #define M98925_ER_INVALSLOT_MAP_MASK (0x07<<4)
441 #define M98925_ER_SLOTCNFLT_MAP_MASK (0x07<<0)
442 #define M98925_ER_SLOTCNFLT_MAP_SHIFT 0
449 #define M98925_ER_SLOTOVRN_MAP_MASK (0x07<<0)
450 #define M98925_ER_SLOTOVRN_MAP_SHIFT 0
457 #define M98925_MDLL_MULT_MASK (0x0F<<0)
458 #define M98925_MDLL_MULT_SHIFT 0
465 #define M98925_DAI_SR_MASK (0x0F<<4)
471 #define M98925_DAI_BSEL_MASK (0x07<<0)
472 #define M98925_DAI_BSEL_SHIFT 0
475 #define M98925_DAI_BSEL_32 (0 << M98925_DAI_BSEL_SHIFT)
481 #define M98925_DAI_M_MSBS_MASK (0xFF<<0)
482 #define M98925_DAI_M_MSBS_SHIFT 0
486 #define M98925_DAI_M_LSBS_MASK (0xFF<<0)
487 #define M98925_DAI_M_LSBS_SHIFT 0
491 #define M98925_DAI_N_MSBS_MASK (0x7F<<0)
492 #define M98925_DAI_N_MSBS_SHIFT 0
496 #define M98925_DAI_N_LSBS_MASK (0xFF<<0)
497 #define M98925_DAI_N_LSBS_SHIFT 0
501 #define M98925_DAI_CHANSZ_MASK (0x03<<6)
516 #define M98925_DAI_TDM_MASK (1<<0)
517 #define M98925_DAI_TDM_SHIFT 0
531 #define M98925_DAI_INR_SOURCE_MASK (0x07<<3)
534 #define M98925_DAI_INL_SOURCE_MASK (0x07<<0)
535 #define M98925_DAI_INL_SOURCE_SHIFT 0
542 #define M98925_DAI_VMON_SLOT_MASK (0x1F<<0)
543 #define M98925_DAI_VMON_SLOT_SHIFT 0
546 #define M98925_DAI_VMON_SLOT_00_01 (0 << M98925_DAI_VMON_SLOT_SHIFT)
582 #define M98925_DAI_IMON_SLOT_MASK (0x1F<<0)
583 #define M98925_DAI_IMON_SLOT_SHIFT 0
586 #define M98925_DAI_IMON_SLOT_00_01 (0 << M98925_DAI_IMON_SLOT_SHIFT)
622 #define M98925_DAI_VBAT_SLOT_MASK (0x1F<<0)
623 #define M98925_DAI_VBAT_SLOT_SHIFT 0
630 #define M98925_DAI_VBST_SLOT_MASK (0x1F<<0)
631 #define M98925_DAI_VBST_SLOT_SHIFT 0
638 #define M98925_DAI_FLAG_SLOT_MASK (0x1F<<0)
639 #define M98925_DAI_FLAG_SLOT_SHIFT 0
643 #define M98925_DAI_SLOT_HIZ_CFG1_MASK (0xFF<<0)
644 #define M98925_DAI_SLOT_HIZ_CFG1_SHIFT 0
648 #define M98925_DAI_SLOT_HIZ_CFG2_MASK (0xFF<<0)
649 #define M98925_DAI_SLOT_HIZ_CFG2_SHIFT 0
653 #define M98925_DAI_SLOT_HIZ_CFG3_MASK (0xFF<<0)
654 #define M98925_DAI_SLOT_HIZ_CFG3_SHIFT 0
658 #define M98925_DAI_SLOT_HIZ_CFG4_MASK (0xFF<<0)
659 #define M98925_DAI_SLOT_HIZ_CFG4_SHIFT 0
663 #define M98925_DAI_OUT_DRIVE_MASK (0x03<<0)
664 #define M98925_DAI_OUT_DRIVE_SHIFT 0
680 #define M98925_DAC_HPF_MASK (0x07<<0)
681 #define M98925_DAC_HPF_SHIFT 0
683 #define M98925_DAC_HPF_DISABLE (0 << M98925_DAC_HPF_SHIFT)
691 #define M98925_DAC_IN_SEL_MASK (0x03<<5)
694 #define M98925_SPK_GAIN_MASK (0x1F<<0)
695 #define M98925_SPK_GAIN_SHIFT 0
698 #define M98925_DAC_IN_SEL_LEFT_DAI (0 << M98925_DAC_IN_SEL_SHIFT)
707 #define M98925_SPK_ZCD_EN_MASK (1<<0)
708 #define M98925_SPK_ZCD_EN_SHIFT 0
712 #define M98925_SPK_MODE_MASK (1<<0)
713 #define M98925_SPK_MODE_SHIFT 0
720 #define M98925_ALC_TH_MASK (0x1F<<0)
721 #define M98925_ALC_TH_SHIFT 0
725 #define M98925_ALC_ATK_STEP_MASK (0x0F<<4)
728 #define M98925_ALC_ATK_RATE_MASK (0x7<<0)
729 #define M98925_ALC_ATK_RATE_SHIFT 0
733 #define M98925_ALC_MAX_ATTEN_MASK (0x0F<<4)
736 #define M98925_ALC_RLS_RATE_MASK (0x7<<0)
737 #define M98925_ALC_RLS_RATE_SHIFT 0
741 #define M98925_ALC_RLS_TGR_MASK (1<<0)
742 #define M98925_ALC_RLS_TGR_SHIFT 0
749 #define M98925_ALC_MUTE_DLY_MASK (0x07<<4)
752 #define M98925_ALC_RLS_DBT_MASK (0x07<<0)
753 #define M98925_ALC_RLS_DBT_SHIFT 0
760 #define M98925_BST_PHASE_MASK (0x03<<4)
763 #define M98925_BST_SKIP_MODE_MASK (0x03<<0)
764 #define M98925_BST_SKIP_MODE_SHIFT 0
789 #define M98925_ADC_VMON_EN_MASK (1<<0)
790 #define M98925_ADC_VMON_EN_SHIFT 0
794 #define M98925_BST_VOUT_MASK (0x0F<<4)
797 #define M98925_THERMWARN_LEVEL_MASK (0x03<<2)
800 #define M98925_WATCH_TIME_MASK (0x03<<0)
801 #define M98925_WATCH_TIME_SHIFT 0
810 #define M98925_BST_ILIM_MASK (0x1F<<3)
815 #define M98925_REV_ID_MASK (0xFF<<0)
816 #define M98925_REV_ID_SHIFT 0