Lines Matching +full:invert +full:- +full:enable
53 /* -127.5dB to 0dB with step of 0.5dB */
54 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
55 /* -64dB to 24dB with step of 0.5dB */
56 static const DECLARE_TLV_DB_SCALE(adc_tlv, -6400, 50, 0);
58 static const char *const cs42xx8_adc_single[] = { "Differential", "Single-Ended" };
83 CS42XX8_VOLAIN2, 0, -0x80, 0x30, 7, 0, adc_tlv),
85 CS42XX8_VOLAIN4, 0, -0x80, 0x30, 7, 0, adc_tlv),
86 SOC_DOUBLE("DAC1 Invert Switch", CS42XX8_DACINV, 0, 1, 1, 0),
87 SOC_DOUBLE("DAC2 Invert Switch", CS42XX8_DACINV, 2, 3, 1, 0),
88 SOC_DOUBLE("DAC3 Invert Switch", CS42XX8_DACINV, 4, 5, 1, 0),
89 SOC_DOUBLE("DAC4 Invert Switch", CS42XX8_DACINV, 6, 7, 1, 0),
90 SOC_DOUBLE("ADC1 Invert Switch", CS42XX8_ADCINV, 0, 1, 1, 0),
91 SOC_DOUBLE("ADC2 Invert Switch", CS42XX8_ADCINV, 2, 3, 1, 0),
92 SOC_SINGLE("ADC High-Pass Filter Switch", CS42XX8_ADCCTL, 7, 1, 1),
93 SOC_SINGLE("DAC De-emphasis Switch", CS42XX8_ADCCTL, 5, 1, 0),
106 CS42XX8_VOLAIN6, 0, -0x80, 0x30, 7, 0, adc_tlv),
107 SOC_DOUBLE("ADC3 Invert Switch", CS42XX8_ADCINV, 4, 5, 1, 0),
206 struct snd_soc_component *component = codec_dai->component; in cs42xx8_set_dai_sysclk()
209 cs42xx8->sysclk = freq; in cs42xx8_set_dai_sysclk()
217 struct snd_soc_component *component = codec_dai->component; in cs42xx8_set_dai_fmt()
236 dev_err(component->dev, "unsupported dai format\n"); in cs42xx8_set_dai_fmt()
237 return -EINVAL; in cs42xx8_set_dai_fmt()
240 regmap_update_bits(cs42xx8->regmap, CS42XX8_INTF, in cs42xx8_set_dai_fmt()
247 cs42xx8->slave_mode = true; in cs42xx8_set_dai_fmt()
250 cs42xx8->slave_mode = false; in cs42xx8_set_dai_fmt()
253 dev_err(component->dev, "unsupported master/slave mode\n"); in cs42xx8_set_dai_fmt()
254 return -EINVAL; in cs42xx8_set_dai_fmt()
264 struct snd_soc_component *component = dai->component; in cs42xx8_hw_params()
266 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in cs42xx8_hw_params()
274 cs42xx8->tx_channels = params_channels(params); in cs42xx8_hw_params()
277 rate[!tx] = cs42xx8->rate[!tx]; in cs42xx8_hw_params()
279 ratio[tx] = rate[tx] > 0 ? cs42xx8->sysclk / rate[tx] : 0; in cs42xx8_hw_params()
280 ratio[!tx] = rate[!tx] > 0 ? cs42xx8->sysclk / rate[!tx] : 0; in cs42xx8_hw_params()
284 if (cs42xx8->slave_mode) { in cs42xx8_hw_params()
294 dev_err(component->dev, in cs42xx8_hw_params()
296 return -EINVAL; in cs42xx8_hw_params()
308 cs42xx8->sysclk >= cs42xx8_ratios[i].min_mclk && in cs42xx8_hw_params()
309 cs42xx8->sysclk <= cs42xx8_ratios[i].max_mclk; in cs42xx8_hw_params()
333 dev_err(component->dev, "unsupported sysclk ratio\n"); in cs42xx8_hw_params()
334 return -EINVAL; in cs42xx8_hw_params()
337 cs42xx8->rate[tx] = params_rate(params); in cs42xx8_hw_params()
342 regmap_update_bits(cs42xx8->regmap, CS42XX8_FUNCMOD, in cs42xx8_hw_params()
352 struct snd_soc_component *component = dai->component; in cs42xx8_hw_free()
354 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in cs42xx8_hw_free()
357 cs42xx8->rate[tx] = 0; in cs42xx8_hw_free()
359 regmap_update_bits(cs42xx8->regmap, CS42XX8_FUNCMOD, in cs42xx8_hw_free()
367 struct snd_soc_component *component = dai->component; in cs42xx8_mute()
369 u8 dac_unmute = cs42xx8->tx_channels ? in cs42xx8_mute()
370 ~((0x1 << cs42xx8->tx_channels) - 1) : 0; in cs42xx8_mute()
372 regmap_write(cs42xx8->regmap, CS42XX8_DACMUTE, in cs42xx8_mute()
408 { 0x05, 0x00 }, /* ADC Control & DAC De-Emphasis */
419 { 0x10, 0x00 }, /* DAC Channel Invert */
426 { 0x17, 0x00 }, /* ADC Channel Invert */
471 switch (cs42xx8->drvdata->num_adcs) { in cs42xx8_component_probe()
485 regmap_write(cs42xx8->regmap, CS42XX8_DACMUTE, CS42XX8_DACMUTE_ALL); in cs42xx8_component_probe()
537 return -ENOMEM; in cs42xx8_probe()
539 cs42xx8->regmap = regmap; in cs42xx8_probe()
544 cs42xx8->drvdata = of_id->data; in cs42xx8_probe()
546 if (!cs42xx8->drvdata) { in cs42xx8_probe()
548 return -EINVAL; in cs42xx8_probe()
551 cs42xx8->gpiod_reset = devm_gpiod_get_optional(dev, "reset", in cs42xx8_probe()
553 if (IS_ERR(cs42xx8->gpiod_reset)) in cs42xx8_probe()
554 return PTR_ERR(cs42xx8->gpiod_reset); in cs42xx8_probe()
556 gpiod_set_value_cansleep(cs42xx8->gpiod_reset, 0); in cs42xx8_probe()
558 cs42xx8->clk = devm_clk_get(dev, "mclk"); in cs42xx8_probe()
559 if (IS_ERR(cs42xx8->clk)) { in cs42xx8_probe()
561 PTR_ERR(cs42xx8->clk)); in cs42xx8_probe()
562 return -EINVAL; in cs42xx8_probe()
565 cs42xx8->sysclk = clk_get_rate(cs42xx8->clk); in cs42xx8_probe()
567 for (i = 0; i < ARRAY_SIZE(cs42xx8->supplies); i++) in cs42xx8_probe()
568 cs42xx8->supplies[i].supply = cs42xx8_supply_names[i]; in cs42xx8_probe()
571 ARRAY_SIZE(cs42xx8->supplies), cs42xx8->supplies); in cs42xx8_probe()
577 ret = regulator_bulk_enable(ARRAY_SIZE(cs42xx8->supplies), in cs42xx8_probe()
578 cs42xx8->supplies); in cs42xx8_probe()
580 dev_err(dev, "failed to enable supplies: %d\n", ret); in cs42xx8_probe()
588 ret = regmap_read(cs42xx8->regmap, CS42XX8_CHIPID, &val); in cs42xx8_probe()
598 ret = -EINVAL; in cs42xx8_probe()
605 cs42xx8_dai.name = cs42xx8->drvdata->name; in cs42xx8_probe()
608 cs42xx8_dai.capture.channels_max = cs42xx8->drvdata->num_adcs * 2; in cs42xx8_probe()
616 regcache_cache_only(cs42xx8->regmap, true); in cs42xx8_probe()
619 regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies), in cs42xx8_probe()
620 cs42xx8->supplies); in cs42xx8_probe()
632 ret = clk_prepare_enable(cs42xx8->clk); in cs42xx8_runtime_resume()
634 dev_err(dev, "failed to enable mclk: %d\n", ret); in cs42xx8_runtime_resume()
638 gpiod_set_value_cansleep(cs42xx8->gpiod_reset, 0); in cs42xx8_runtime_resume()
640 ret = regulator_bulk_enable(ARRAY_SIZE(cs42xx8->supplies), in cs42xx8_runtime_resume()
641 cs42xx8->supplies); in cs42xx8_runtime_resume()
643 dev_err(dev, "failed to enable supplies: %d\n", ret); in cs42xx8_runtime_resume()
650 regcache_cache_only(cs42xx8->regmap, false); in cs42xx8_runtime_resume()
651 regcache_mark_dirty(cs42xx8->regmap); in cs42xx8_runtime_resume()
653 ret = regcache_sync(cs42xx8->regmap); in cs42xx8_runtime_resume()
662 regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies), in cs42xx8_runtime_resume()
663 cs42xx8->supplies); in cs42xx8_runtime_resume()
665 clk_disable_unprepare(cs42xx8->clk); in cs42xx8_runtime_resume()
674 regcache_cache_only(cs42xx8->regmap, true); in cs42xx8_runtime_suspend()
676 regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies), in cs42xx8_runtime_suspend()
677 cs42xx8->supplies); in cs42xx8_runtime_suspend()
679 gpiod_set_value_cansleep(cs42xx8->gpiod_reset, 1); in cs42xx8_runtime_suspend()
681 clk_disable_unprepare(cs42xx8->clk); in cs42xx8_runtime_suspend()