76 		rv_writel(BIT(BT_TX_THRESHOLD), rv_i2s_data->acp3x_base +  in i2s_irq_handler()
83 		rv_writel(BIT(I2S_TX_THRESHOLD),  in i2s_irq_handler()
90 		rv_writel(BIT(BT_RX_THRESHOLD), rv_i2s_data->acp3x_base +  in i2s_irq_handler()
97 		rv_writel(BIT(I2S_RX_THRESHOLD),  in i2s_irq_handler()
138 	rv_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp3x_base +  in config_acp3x_dma()
140 	rv_writel(PAGE_SIZE_4K_ENABLE, rtd->acp3x_base +  in config_acp3x_dma()
148 		rv_writel(low, rtd->acp3x_base + mmACP_SCRATCH_REG_0 + val);  in config_acp3x_dma()
150 		rv_writel(high, rtd->acp3x_base + mmACP_SCRATCH_REG_0 + val  in config_acp3x_dma()
165 			rv_writel(I2S_BT_TX_MEM_WINDOW_START,  in config_acp3x_dma()
176 			rv_writel(I2S_SP_TX_MEM_WINDOW_START,  in config_acp3x_dma()
187 			rv_writel(I2S_BT_RX_MEM_WINDOW_START,  in config_acp3x_dma()
198 			rv_writel(I2S_SP_RX_MEM_WINDOW_START,  in config_acp3x_dma()
202 	rv_writel(DMA_SIZE, rtd->acp3x_base + reg_dma_size);  in config_acp3x_dma()
203 	rv_writel(acp_fifo_addr, rtd->acp3x_base + reg_fifo_addr);  in config_acp3x_dma()
204 	rv_writel(FIFO_SIZE, rtd->acp3x_base + reg_fifo_size);  in config_acp3x_dma()
205 	rv_writel(BIT(I2S_RX_THRESHOLD) | BIT(BT_RX_THRESHOLD)  in config_acp3x_dma()
242 		rv_writel(1, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);  in acp3x_dma_open()
375 		rv_writel(0, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);  in acp3x_dma_close()
476 		rv_writel((rtd->xfer_resolution  << 3),  in acp3x_resume()
493 		rv_writel((rtd->xfer_resolution  << 3),  in acp3x_resume()
497 		rv_writel(adata->tdm_fmt, adata->acp3x_base + frmt_val);  in acp3x_resume()
499 		rv_writel(val | 0x2, adata->acp3x_base + reg_val);  in acp3x_resume()
501 	rv_writel(1, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);  in acp3x_resume()
512 	rv_writel(0, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);  in acp3x_pcm_runtime_suspend()
523 	rv_writel(1, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);  in acp3x_pcm_runtime_resume()