Lines Matching +full:0 +full:- +full:127
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
20 #define SNDRV_TRIDENT_VOICE_TYPE_PCM 0
24 #define SNDRV_TRIDENT_VFLG_RUNNING (1<<0)
29 #define SNDRV_TRIDENT_PAGE_MASK ((1<<SNDRV_TRIDENT_PAGE_SHIFT)-1)
36 #define TRID_REG(trident, x) ((trident)->port + (x))
38 #define ID_4DWAVE_DX 0x2000
39 #define ID_4DWAVE_NX 0x2001
43 #define T4D_BANK_A 0
52 CHANNEL_IDX = 0x0000003f,
53 OVERRUN_IE = 0x00000400, /* interrupt enable: capture overrun */
54 UNDERRUN_IE = 0x00000800, /* interrupt enable: playback underrun */
55 ENDLP_IE = 0x00001000, /* interrupt enable: end of buffer */
56 MIDLP_IE = 0x00002000, /* interrupt enable: middle buffer */
57 ETOG_IE = 0x00004000, /* interrupt enable: envelope toggling */
58 EDROP_IE = 0x00008000, /* interrupt enable: envelope drop */
59 BANK_B_EN = 0x00010000, /* SiS: enable bank B (64 channels) */
60 PCMIN_B_MIX = 0x00020000, /* SiS: PCM IN B mixing enable */
61 I2S_OUT_ASSIGN = 0x00040000, /* SiS: I2S Out contains surround PCM */
62 SPDIF_OUT_ASSIGN= 0x00080000, /* SiS: 0=S/PDIF L/R | 1=PCM Out FIFO */
63 MAIN_OUT_ASSIGN = 0x00100000, /* SiS: 0=PCM Out FIFO | 1=MMC Out buffer */
67 PB_UNDERRUN_IRQ = 0x00000001, REC_OVERRUN_IRQ = 0x00000002,
68 SB_IRQ = 0x00000004, MPU401_IRQ = 0x00000008,
69 OPL3_IRQ = 0x00000010, ADDRESS_IRQ = 0x00000020,
70 ENVELOPE_IRQ = 0x00000040, PB_UNDERRUN = 0x00000100,
71 REC_OVERRUN = 0x00000200, MIXER_UNDERFLOW = 0x00000400,
72 MIXER_OVERFLOW = 0x00000800, NX_SB_IRQ_DISABLE = 0x00001000,
73 ST_TARGET_REACHED = 0x00008000,
74 PB_24K_MODE = 0x00010000, ST_IRQ_EN = 0x00800000,
75 ACGPIO_IRQ = 0x01000000
79 #define LEGACY_DMAR0 0x00 // ADR0
80 #define LEGACY_DMAR4 0x04 // CNT0
81 #define LEGACY_DMAR6 0x06 // CNT0 - High bits
82 #define LEGACY_DMAR11 0x0b // MOD
83 #define LEGACY_DMAR15 0x0f // MMR
85 #define T4D_START_A 0x80
86 #define T4D_STOP_A 0x84
87 #define T4D_DLY_A 0x88
88 #define T4D_SIGN_CSO_A 0x8c
89 #define T4D_CSPF_A 0x90
90 #define T4D_CSPF_B 0xbc
91 #define T4D_CEBC_A 0x94
92 #define T4D_AINT_A 0x98
93 #define T4D_AINTEN_A 0x9c
94 #define T4D_LFO_GC_CIR 0xa0
95 #define T4D_MUSICVOL_WAVEVOL 0xa8
96 #define T4D_SBDELTA_DELTA_R 0xac
97 #define T4D_MISCINT 0xb0
98 #define T4D_START_B 0xb4
99 #define T4D_STOP_B 0xb8
100 #define T4D_SBBL_SBCL 0xc0
101 #define T4D_SBCTRL_SBE2R_SBDD 0xc4
102 #define T4D_STIMER 0xc8
103 #define T4D_AINT_B 0xd8
104 #define T4D_AINTEN_B 0xdc
105 #define T4D_RCI 0x70
107 /* MPU-401 UART */
108 #define T4D_MPU401_BASE 0x20
109 #define T4D_MPUR0 0x20
110 #define T4D_MPUR1 0x21
111 #define T4D_MPUR2 0x22
112 #define T4D_MPUR3 0x23
115 #define NX_SPCTRL_SPCSO 0x24
116 #define NX_SPLBA 0x28
117 #define NX_SPESO 0x2c
118 #define NX_SPCSTATUS 0x64
121 #define GAMEPORT_GCR 0x30
122 #define GAMEPORT_MODE_ADC 0x80
123 #define GAMEPORT_LEGACY 0x31
124 #define GAMEPORT_AXES 0x34
127 #define NX_TLBC 0x6c
131 #define CH_START 0xe0
133 #define CH_DX_CSO_ALPHA_FMS 0xe0
134 #define CH_DX_ESO_DELTA 0xe8
135 #define CH_DX_FMC_RVOL_CVOL 0xec
137 #define CH_NX_DELTA_CSO 0xe0
138 #define CH_NX_DELTA_ESO 0xe8
139 #define CH_NX_ALPHA_FMS_FMC_RVOL_CVOL 0xec
141 #define CH_LBA 0xe4
142 #define CH_GVSEL_PAN_VOL_CTRL_EC 0xf0
143 #define CH_EBUF1 0xf4
144 #define CH_EBUF2 0xf8
146 /* AC-97 Registers */
148 #define DX_ACR0_AC97_W 0x40
149 #define DX_ACR1_AC97_R 0x44
150 #define DX_ACR2_AC97_COM_STAT 0x48
152 #define NX_ACR0_AC97_COM_STAT 0x40
153 #define NX_ACR1_AC97_W 0x44
154 #define NX_ACR2_AC97_R_PRIMARY 0x48
155 #define NX_ACR3_AC97_R_SECONDARY 0x4c
157 #define SI_AC97_WRITE 0x40
158 #define SI_AC97_READ 0x44
159 #define SI_SERIAL_INTF_CTRL 0x48
160 #define SI_AC97_GPIO 0x4c
161 #define SI_ASR0 0x50
162 #define SI_SPDIF_CS 0x70
163 #define SI_GPIO 0x7c
166 /* ACR1-3 */
167 NX_AC97_BUSY_WRITE = 0x0800,
168 NX_AC97_BUSY_READ = 0x0800,
169 NX_AC97_BUSY_DATA = 0x0400,
170 NX_AC97_WRITE_SECONDARY = 0x0100,
172 NX_AC97_SECONDARY_READY = 0x0040,
173 NX_AC97_SECONDARY_RECORD = 0x0020,
174 NX_AC97_SURROUND_OUTPUT = 0x0010,
175 NX_AC97_PRIMARY_READY = 0x0008,
176 NX_AC97_PRIMARY_RECORD = 0x0004,
177 NX_AC97_PCM_OUTPUT = 0x0002,
178 NX_AC97_WARM_RESET = 0x0001
182 DX_AC97_BUSY_WRITE = 0x8000,
183 DX_AC97_BUSY_READ = 0x8000,
184 DX_AC97_READY = 0x0010,
185 DX_AC97_RECORD = 0x0008,
186 DX_AC97_PLAYBACK = 0x0002
190 SI_AC97_BUSY_WRITE = 0x00008000,
191 SI_AC97_AUDIO_BUSY = 0x00004000,
192 SI_AC97_MODEM_BUSY = 0x00002000,
193 SI_AC97_BUSY_READ = 0x00008000,
194 SI_AC97_SECONDARY = 0x00000080,
198 WARM_RESET = 0x00000001,
199 COLD_RESET = 0x00000002,
200 I2S_CLOCK = 0x00000004,
201 PCM_SEC_AC97 = 0x00000008,
202 AC97_DBL_RATE = 0x00000010,
203 SPDIF_EN = 0x00000020,
204 I2S_OUTPUT_EN = 0x00000040,
205 I2S_INPUT_EN = 0x00000080,
206 PCMIN = 0x00000100,
207 LINE1IN = 0x00000200,
208 MICIN = 0x00000400,
209 LINE2IN = 0x00000800,
210 HEAD_SET_IN = 0x00001000,
211 GPIOIN = 0x00002000,
213 SECONDARY_ID= 0x00004000, */
214 SECONDARY_ID = 0x00004000,
215 PCMOUT = 0x00010000,
216 SURROUT = 0x00020000,
217 CENTEROUT = 0x00040000,
218 LFEOUT = 0x00080000,
219 LINE1OUT = 0x00100000,
220 LINE2OUT = 0x00200000,
221 GPIOOUT = 0x00400000,
222 SI_AC97_PRIMARY_READY = 0x01000000,
223 SI_AC97_SECONDARY_READY = 0x02000000,
224 SI_AC97_POWERDOWN = 0x04000000,
229 #define T4D_DEFAULT_PCM_VOL 10 /* 0 - 255 */
230 #define T4D_DEFAULT_PCM_PAN 0 /* 0 - 127 */
231 #define T4D_DEFAULT_PCM_RVOL 127 /* 0 - 127 */
232 #define T4D_DEFAULT_PCM_CVOL 127 /* 0 - 127 */
252 __le32 *entries; /* 16k-aligned TLB table */
253 dma_addr_t entries_dmaaddr; /* 16k-aligned PCI address to TLB table */
280 unsigned short Attribute; /* 16 bits - SiS 7018 */
291 unsigned int negCSO; /* nonzero - use negative CSO */
314 /* --- */