117 	u32 control_reg;  in load_asic()  local
150 		control_reg = GML_CONVERTER_ENABLE | GML_48KHZ;  in load_asic()
151 		err = write_control_reg(chip, control_reg, true);  in load_asic()
198 	u32 control_reg, clock;  in set_sample_rate()  local
244 	control_reg = le32_to_cpu(chip->comm_page->control_register);  in set_sample_rate()
245 	control_reg &= GML_CLOCK_CLEAR_MASK;  in set_sample_rate()
246 	control_reg &= GML_SPDIF_RATE_CLEAR_MASK;  in set_sample_rate()
261 		if (control_reg & GML_SPDIF_PRO_MODE)  in set_sample_rate()
286 	control_reg |= clock;  in set_sample_rate()
293 	return write_control_reg(chip, control_reg, force_write);  in set_sample_rate()
300 	u32 control_reg, clocks_from_dsp;  in set_input_clock()  local
304 	control_reg = le32_to_cpu(chip->comm_page->control_register) &  in set_input_clock()
321 		control_reg |= GML_SPDIF_CLOCK;  in set_input_clock()
323 			control_reg |= GML_DOUBLE_SPEED_MODE;  in set_input_clock()
325 			control_reg &= ~GML_DOUBLE_SPEED_MODE;  in set_input_clock()
334 		control_reg |= GML_WORD_CLOCK;  in set_input_clock()
336 			control_reg |= GML_DOUBLE_SPEED_MODE;  in set_input_clock()
338 			control_reg &= ~GML_DOUBLE_SPEED_MODE;  in set_input_clock()
344 		control_reg |= GML_ADAT_CLOCK;  in set_input_clock()
345 		control_reg &= ~GML_DOUBLE_SPEED_MODE;  in set_input_clock()
354 	return write_control_reg(chip, control_reg, true);  in set_input_clock()
361 	u32 control_reg;  in dsp_set_digital_mode()  local
390 	control_reg = le32_to_cpu(chip->comm_page->control_register);  in dsp_set_digital_mode()
391 	control_reg &= GML_DIGITAL_MODE_CLEAR_MASK;  in dsp_set_digital_mode()
396 		control_reg |= GML_SPDIF_OPTICAL_MODE;  in dsp_set_digital_mode()
408 		control_reg |= GML_ADAT_MODE;  in dsp_set_digital_mode()
409 		control_reg &= ~GML_DOUBLE_SPEED_MODE;  in dsp_set_digital_mode()
413 	err = write_control_reg(chip, control_reg, false);  in dsp_set_digital_mode()