159 	u32 control_reg, clock, base_rate;  in set_sample_rate()  local
176 	control_reg = le32_to_cpu(chip->comm_page->control_register);  in set_sample_rate()
177 	control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK;  in set_sample_rate()
194 		if (control_reg & GML_SPDIF_PRO_MODE)  in set_sample_rate()
219 			control_reg |= GML_DOUBLE_SPEED_MODE;  in set_sample_rate()
237 	control_reg |= clock;  in set_sample_rate()
242 		"set_sample_rate: %d clock %d\n", rate, control_reg);  in set_sample_rate()
244 	return write_control_reg(chip, control_reg, false);  in set_sample_rate()
251 	u32 control_reg, clocks_from_dsp;  in set_input_clock()  local
254 	control_reg = le32_to_cpu(chip->comm_page->control_register) &  in set_input_clock()
266 		control_reg |= GML_SPDIF_CLOCK;  in set_input_clock()
268 		control_reg &= ~GML_DOUBLE_SPEED_MODE;  in set_input_clock()
271 		control_reg |= GML_WORD_CLOCK;  in set_input_clock()
273 			control_reg |= GML_DOUBLE_SPEED_MODE;  in set_input_clock()
275 			control_reg &= ~GML_DOUBLE_SPEED_MODE;  in set_input_clock()
280 		control_reg |= GML_ADAT_CLOCK;  in set_input_clock()
281 		control_reg &= ~GML_DOUBLE_SPEED_MODE;  in set_input_clock()
290 	return write_control_reg(chip, control_reg, true);  in set_input_clock()
332 	u32 control_reg;  in dsp_set_digital_mode()  local
370 	control_reg = le32_to_cpu(chip->comm_page->control_register);  in dsp_set_digital_mode()
371 	control_reg &= GML_DIGITAL_MODE_CLEAR_MASK;  in dsp_set_digital_mode()
375 		control_reg |= GML_SPDIF_OPTICAL_MODE;  in dsp_set_digital_mode()
381 		control_reg |= GML_ADAT_MODE;  in dsp_set_digital_mode()
382 		control_reg &= ~GML_DOUBLE_SPEED_MODE;  in dsp_set_digital_mode()
386 	err = write_control_reg(chip, control_reg, true);  in dsp_set_digital_mode()