124 	u32 control_reg;  in load_asic()  local
154 		control_reg = GML_CONVERTER_ENABLE | GML_48KHZ;  in load_asic()
155 		err = write_control_reg(chip, control_reg, true);  in load_asic()
164 	u32 control_reg, clock;  in set_sample_rate()  local
182 	control_reg = le32_to_cpu(chip->comm_page->control_register);  in set_sample_rate()
183 	control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK;  in set_sample_rate()
198 		if (control_reg & GML_SPDIF_PRO_MODE)  in set_sample_rate()
223 	control_reg |= clock;  in set_sample_rate()
229 	return write_control_reg(chip, control_reg, false);  in set_sample_rate()
236 	u32 control_reg, clocks_from_dsp;  in set_input_clock()  local
240 	control_reg = le32_to_cpu(chip->comm_page->control_register) &  in set_input_clock()
251 		control_reg |= GML_SPDIF_CLOCK;  in set_input_clock()
253 			control_reg |= GML_DOUBLE_SPEED_MODE;  in set_input_clock()
255 			control_reg &= ~GML_DOUBLE_SPEED_MODE;  in set_input_clock()
260 		control_reg |= GML_ADAT_CLOCK;  in set_input_clock()
261 		control_reg &= ~GML_DOUBLE_SPEED_MODE;  in set_input_clock()
264 		control_reg |= GML_ESYNC_CLOCK;  in set_input_clock()
265 		control_reg &= ~GML_DOUBLE_SPEED_MODE;  in set_input_clock()
268 		control_reg |= GML_ESYNC_CLOCK | GML_DOUBLE_SPEED_MODE;  in set_input_clock()
277 	return write_control_reg(chip, control_reg, true);  in set_input_clock()
284 	u32 control_reg;  in dsp_set_digital_mode()  local
314 	control_reg = le32_to_cpu(chip->comm_page->control_register);  in dsp_set_digital_mode()
315 	control_reg &= GML_DIGITAL_MODE_CLEAR_MASK;  in dsp_set_digital_mode()
320 		control_reg |= GML_SPDIF_OPTICAL_MODE;  in dsp_set_digital_mode()
325 			control_reg |= GML_SPDIF_CDROM_MODE;  in dsp_set_digital_mode()
331 		control_reg |= GML_ADAT_MODE;  in dsp_set_digital_mode()
332 		control_reg &= ~GML_DOUBLE_SPEED_MODE;  in dsp_set_digital_mode()
336 	err = write_control_reg(chip, control_reg, true);  in dsp_set_digital_mode()