145 static u32 set_spdif_bits(struct echoaudio *chip, u32 control_reg, u32 rate)  in set_spdif_bits()  argument
147 	control_reg &= E3G_SPDIF_FORMAT_CLEAR_MASK;  in set_spdif_bits()
151 		control_reg |= E3G_SPDIF_SAMPLE_RATE0 | E3G_SPDIF_SAMPLE_RATE1;  in set_spdif_bits()
155 			control_reg |= E3G_SPDIF_SAMPLE_RATE0;  in set_spdif_bits()
158 		control_reg |= E3G_SPDIF_SAMPLE_RATE1;  in set_spdif_bits()
163 		control_reg |= E3G_SPDIF_PRO_MODE;  in set_spdif_bits()
166 		control_reg |= E3G_SPDIF_NOT_AUDIO;  in set_spdif_bits()
168 	control_reg |= E3G_SPDIF_24_BIT | E3G_SPDIF_TWO_CHANNEL |  in set_spdif_bits()
171 	return control_reg;  in set_spdif_bits()
179 	u32 control_reg;  in set_professional_spdif()  local
181 	control_reg = le32_to_cpu(chip->comm_page->control_register);  in set_professional_spdif()
183 	control_reg = set_spdif_bits(chip, control_reg, chip->sample_rate);  in set_professional_spdif()
184 	return write_control_reg(chip, control_reg, get_frq_reg(chip), 0);  in set_professional_spdif()
260 	u32 control_reg, clock, base_rate, frq_reg;  in set_sample_rate()  local
278 	control_reg = le32_to_cpu(chip->comm_page->control_register);  in set_sample_rate()
279 	control_reg &= E3G_CLOCK_CLEAR_MASK;  in set_sample_rate()
304 	control_reg |= clock;  in set_sample_rate()
305 	control_reg = set_spdif_bits(chip, control_reg, rate);  in set_sample_rate()
320 		"SetSampleRate: %d clock %x\n", rate, control_reg);  in set_sample_rate()
323 	return write_control_reg(chip, control_reg, frq_reg, 0);  in set_sample_rate()
331 	u32 control_reg, clocks_from_dsp;  in set_input_clock()  local
335 	control_reg = le32_to_cpu(chip->comm_page->control_register) &  in set_input_clock()
346 		control_reg |= E3G_SPDIF_CLOCK;  in set_input_clock()
348 			control_reg |= E3G_DOUBLE_SPEED_MODE;  in set_input_clock()
350 			control_reg &= ~E3G_DOUBLE_SPEED_MODE;  in set_input_clock()
355 		control_reg |= E3G_ADAT_CLOCK;  in set_input_clock()
356 		control_reg &= ~E3G_DOUBLE_SPEED_MODE;  in set_input_clock()
359 		control_reg |= E3G_WORD_CLOCK;  in set_input_clock()
361 			control_reg |= E3G_DOUBLE_SPEED_MODE;  in set_input_clock()
363 			control_reg &= ~E3G_DOUBLE_SPEED_MODE;  in set_input_clock()
372 	return write_control_reg(chip, control_reg, get_frq_reg(chip), 1);  in set_input_clock()
379 	u32 control_reg;  in dsp_set_digital_mode()  local
408 	control_reg = le32_to_cpu(chip->comm_page->control_register);  in dsp_set_digital_mode()
409 	control_reg &= E3G_DIGITAL_MODE_CLEAR_MASK;  in dsp_set_digital_mode()
414 		control_reg |= E3G_SPDIF_OPTICAL_MODE;  in dsp_set_digital_mode()
420 		control_reg |= E3G_ADAT_MODE;  in dsp_set_digital_mode()
421 		control_reg &= ~E3G_DOUBLE_SPEED_MODE;	/* @@ useless */  in dsp_set_digital_mode()
425 	err = write_control_reg(chip, control_reg, get_frq_reg(chip), 1);  in dsp_set_digital_mode()