Lines Matching +full:rx +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
19 #define AACI_RXCR 0x000 /* 29 bits Control Rx FIFO */
23 #define AACI_IE 0x010 /* 7 bits Int Enable */
36 #define AACI_SLIEN 0x070 /* slot interrupt enable */
49 * TX/RX fifo control register (CR). P48
51 #define CR_FEN (1 << 16) /* fifo enable */
69 #define CR_EN (1 << 0) /* transmit enable */
74 #define SR_RXTOFE (1 << 11) /* rx timeout fifo empty */
75 #define SR_TXTO (1 << 10) /* rx timeout fifo nonempty */
77 #define SR_RXO (1 << 8) /* rx overrun */
79 #define SR_RXB (1 << 6) /* rx busy */
81 #define SR_RXFF (1 << 4) /* rx fifo full */
83 #define SR_RXHF (1 << 2) /* rx fifo half full */
85 #define SR_RXFE (1 << 0) /* rx fifo empty */
90 #define ISR_RXTOFEINTR (1 << 6) /* rx fifo empty */
92 #define ISR_ORINTR (1 << 4) /* rx overflow */
93 #define ISR_RXINTR (1 << 3) /* rx fifo */
99 * interrupt enable register bits.
112 #define ISR_RXTOFE (1 << 6) /* rx timeout fifo empty */
114 #define ISR_OR (1 << 4) /* rx fifo overrun */
115 #define ISR_RX (1 << 3) /* rx interrupt status */
117 #define ISR_RXTO (1 << 1) /* rx timeout */
121 * interrupt enable. P52
123 #define IE_RXTOFE (1 << 6) /* rx timeout fifo empty */
125 #define IE_OR (1 << 4) /* rx fifo overrun */
126 #define IE_RX (1 << 3) /* rx interrupt status */
128 #define IE_RXTO (1 << 1) /* rx timeout */
134 #define SLFR_RWIS (1 << 13) /* raw wake-up interrupt status */
137 #define SLFR_12RXV (1 << 10) /* slot 12 rx valid */
139 #define SLFR_2RXV (1 << 8) /* slot 2 rx valid */
141 #define SLFR_1RXV (1 << 6) /* slot 1 rx valid */
143 #define SLFR_12RXB (1 << 4) /* slot 12 rx busy */
145 #define SLFR_2RXB (1 << 2) /* slot 2 rx busy */
147 #define SLFR_1RXB (1 << 0) /* slot 1 rx busy */
170 #define MAINCR_DMAEN (1 << 9) /* dma enable */
171 #define MAINCR_SL12TXEN (1 << 8) /* slot 12 transmit enable */
172 #define MAINCR_SL12RXEN (1 << 7) /* slot 12 receive enable */
173 #define MAINCR_SL2TXEN (1 << 6) /* slot 2 transmit enable */
174 #define MAINCR_SL2RXEN (1 << 5) /* slot 2 receive enable */
175 #define MAINCR_SL1TXEN (1 << 4) /* slot 1 transmit enable */
176 #define MAINCR_SL1RXEN (1 << 3) /* slot 1 receive enable */
179 #define MAINCR_IE (1 << 0) /* aaci interface enable */