Lines Matching +full:rx +full:- +full:tx +full:- +full:swap
1 /* SPDX-License-Identifier: GPL-1.0+ WITH Linux-syscall-note */
44 #define UART_IIR_RX_TIMEOUT 0x0c /* OMAP RX Timeout interrupt */
55 * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11
125 #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
135 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
193 #define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx
215 #define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */
216 #define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */
217 #define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */
218 #define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */
219 #define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */
220 #define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */
228 #define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */
232 * The Intel XScale on-chip UARTs define these bits
268 #define UART_NMR 0x0D /* Nine-bit Mode Register */
284 * These definitions are for the RSA-DV II/S card, from
286 * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
289 #define UART_RSA_BASE (-8)
293 #define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */
300 #define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */
301 #define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */
302 #define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */
308 #define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */
309 #define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */
310 #define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */
311 #define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */
312 #define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */
313 #define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */
336 #define UART_DA830_PWREMU_MGMT_FREE (1 << 0) /* Free-running mode */
356 #define UART_OMAP_WER 0x17 /* Wake-up enable register */
357 #define UART_OMAP_TX_LVL 0x1a /* TX FIFO level register */
364 #define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02 /* UART 16x auto-baud */
376 #define UART_ALTR_EN_TXFIFO_LW 0x01 /* Enable the TX FIFO Low Watermark */
377 #define UART_ALTR_TX_LOW 0x41 /* Tx FIFO Low Watermark */