Lines Matching +full:cts +full:- +full:rts +full:- +full:swap
1 /* SPDX-License-Identifier: GPL-1.0+ WITH Linux-syscall-note */
46 #define UART_IIR_CTS_RTS_DSR 0x20 /* OMAP CTS/RTS/DSR Change */
125 #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
129 #define UART_MCR_RTS 0x02 /* RTS complement */
135 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
151 #define UART_MSR_DCTS 0x01 /* Delta CTS */
168 #define UART_EFR_CTS 0x80 /* CTS flow control */
169 #define UART_EFR_RTS 0x40 /* RTS flow control */
210 #define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */
220 #define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */
232 * The Intel XScale on-chip UARTs define these bits
268 #define UART_NMR 0x0D /* Nine-bit Mode Register */
284 * These definitions are for the RSA-DV II/S card, from
286 * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
289 #define UART_RSA_BASE (-8)
293 #define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */
295 #define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */
336 #define UART_DA830_PWREMU_MGMT_FREE (1 << 0) /* Free-running mode */
356 #define UART_OMAP_WER 0x17 /* Wake-up enable register */
364 #define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02 /* UART 16x auto-baud */