Lines Matching +full:mode +full:- +full:capable
1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
5 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
25 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
26 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
50 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
59 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
87 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
123 /* 0x35-0x3b are reserved */
129 /* Header type 1 (PCI-to-PCI bridges) */
157 /* 0x35-0x3b is reserved */
159 /* 0x3c-0x3d are same as for htype 0 */
163 #define PCI_BRIDGE_CTL_ISA 0x04 /* Enable ISA mode */
190 /* 0x3c-0x3d are same as for htype 0 */
198 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
204 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
205 /* 0x48-0x7f reserved */
216 #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
218 #define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */
221 #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
223 #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
226 #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
255 #define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
271 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
273 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
282 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
294 #define PCI_VPD_DATA 4 /* 32-bits of data returned here */
310 #define PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */
311 #define PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking capable */
315 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
316 #define PCI_MSI_MASK_32 12 /* Mask bits register for 32-bit devices */
317 #define PCI_MSI_PENDING_32 16 /* Pending intrs for 32-bit devices */
318 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
319 #define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */
320 #define PCI_MSI_PENDING_64 20 /* Pending intrs for 64-bit devices */
322 /* MSI-X registers (in MSI-X capability) */
326 #define PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */
336 /* MSI-X Table entry format (in memory mapped by a BAR) */
352 #define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
353 #define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
381 /* 0-5 map to BARs 0-5 respectively */
387 /* 9-14 map to VF BARs 0-5 respectively */
390 #define PCI_EA_BEI_RESERVED 15 /* Reserved - Treat like ENI */
393 #define PCI_EA_P_MEM 0x00 /* Non-Prefetch Memory */
397 #define PCI_EA_P_VF_MEM 0x04 /* VF Non-Prefetch Memory */
398 #define PCI_EA_P_BRIDGE_MEM 0x05 /* Bridge Non-Prefetch Memory */
401 /* 0x08-0xfc reserved */
410 #define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */
413 /* PCI-X registers (Type 0 (non-bridge) devices) */
434 #define PCI_X_STATUS 4 /* PCI-X capabilities */
437 #define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
438 #define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
446 #define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
447 #define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
453 /* PCI-X registers (Type 1 (bridge) devices) */
457 #define PCI_X_SSTATUS_133MHZ 0x0002 /* 133 MHz capable */
458 #define PCI_X_SSTATUS_FREQ 0x03c0 /* Secondary Bus Mode and Frequency */
459 #define PCI_X_SSTATUS_VERS 0x3000 /* PCI-X Capability Version */
460 #define PCI_X_SSTATUS_V1 0x1000 /* Mode 2, not Mode 1 */
461 #define PCI_X_SSTATUS_V2 0x2000 /* Mode 1 or Modes 1 and 2 */
462 #define PCI_X_SSTATUS_266MHZ 0x4000 /* 266 MHz capable */
463 #define PCI_X_SSTATUS_533MHZ 0x8000 /* 533 MHz capable */
481 #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */
482 #define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */
496 #define PCI_EXP_DEVCAP_RBER 0x00008000 /* Role-Based Error Reporting */
502 #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
521 #define PCI_EXP_DEVSTA_NFED 0x0002 /* Non-Fatal Error Detected */
541 #define PCI_EXP_LNKCAP_SDERC 0x00080000 /* Surprise Down Error Reporting Capable */
542 #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
583 #define PCI_EXP_SLTCAP_HPS 0x00000020 /* Hot-Plug Surprise */
584 #define PCI_EXP_SLTCAP_HPC 0x00000040 /* Hot-Plug Capable */
596 #define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
611 #define PCI_EXP_SLTCTL_IBPD_DISABLE 0x4000 /* In-band PD disable */
624 #define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */
643 #define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */
651 #define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */
652 #define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 /* End-End TLP Prefix */
656 #define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */
687 #define PCI_EXP_SLTCAP2_IBPD 0x00000001 /* In-band PD Disable Supported */
691 /* Extended Capabilities (PCI-X 2.0 and Express) */
703 #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */
706 #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */
707 #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */
762 #define PCI_ERR_COR_ADV_NFAT 0x00002000 /* Advisory Non-Fatal */
769 #define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */
771 #define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
776 #define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Err Reporting Enable */
784 #define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */
834 /* Vendor-Specific (VSEC, PCI_EXT_CAP_ID_VNDR) */
835 #define PCI_VNDR_HEADER 4 /* Vendor-Specific Header */
874 /* Alternative Routing-ID Interpretation */
912 #define PCI_PASID_CAP_PRIV 0x04 /* Privilege Mode Supported */
916 #define PCI_PASID_CTRL_PRIV 0x04 /* Privilege Mode Enable */
920 #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
921 #define PCI_SRIOV_CAP_VFM 0x00000001 /* VF Migration Capable */
923 #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
928 #define PCI_SRIOV_CTRL_ARI 0x0010 /* ARI Capable Hierarchy */
929 #define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */
971 #define PCI_VSEC_HDR 4 /* extended cap - vendor-specific */
976 #define PCI_SATA_REGS_MASK 0xF /* location - BAR#/inline */
993 #define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */
1001 #define PCI_TPH_LOC_MSIX 0x400 /* in MSI-X */
1040 #define PCI_PTM_CAP_REQ 0x00000001 /* Requester capable */
1041 #define PCI_PTM_CAP_ROOT 0x00000004 /* Root capable */
1049 #define PCI_L1SS_CAP_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Supported */
1050 #define PCI_L1SS_CAP_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Supported */
1058 #define PCI_L1SS_CTL1_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Enable */
1059 #define PCI_L1SS_CTL1_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Enable */