Lines Matching +full:rx +full:- +full:tx +full:- +full:swap
1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
57 /* Media-dependent registers. */
58 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
59 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
60 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
61 * Lanes B-D are numbered 134-136. */
62 #define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */
63 #define MDIO_PCS_10GBX_STAT1 24 /* 10GBASE-X PCS status 1 */
64 #define MDIO_PCS_10GBRT_STAT1 32 /* 10GBASE-R/-T PCS status 1 */
65 #define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */
66 #define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */
67 #define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */
97 /* 10PASS-TS/2BASE-TL */
105 #define MDIO_STAT1_LPOWERABLE 0x0002 /* Low-power ability */
117 #define MDIO_PMA_SPEED_2B 0x0002 /* 2BASE-TL capable */
118 #define MDIO_PMA_SPEED_10P 0x0004 /* 10PASS-TS capable */
122 #define MDIO_PCS_SPEED_10P2B 0x0002 /* 10PASS-TS/2BASE-TL capable */
140 #define MDIO_PMA_CTRL2_10GBCX4 0x0000 /* 10GBASE-CX4 type */
141 #define MDIO_PMA_CTRL2_10GBEW 0x0001 /* 10GBASE-EW type */
142 #define MDIO_PMA_CTRL2_10GBLW 0x0002 /* 10GBASE-LW type */
143 #define MDIO_PMA_CTRL2_10GBSW 0x0003 /* 10GBASE-SW type */
144 #define MDIO_PMA_CTRL2_10GBLX4 0x0004 /* 10GBASE-LX4 type */
145 #define MDIO_PMA_CTRL2_10GBER 0x0005 /* 10GBASE-ER type */
146 #define MDIO_PMA_CTRL2_10GBLR 0x0006 /* 10GBASE-LR type */
147 #define MDIO_PMA_CTRL2_10GBSR 0x0007 /* 10GBASE-SR type */
148 #define MDIO_PMA_CTRL2_10GBLRM 0x0008 /* 10GBASE-LRM type */
149 #define MDIO_PMA_CTRL2_10GBT 0x0009 /* 10GBASE-T type */
150 #define MDIO_PMA_CTRL2_10GBKX4 0x000a /* 10GBASE-KX4 type */
151 #define MDIO_PMA_CTRL2_10GBKR 0x000b /* 10GBASE-KR type */
152 #define MDIO_PMA_CTRL2_1000BT 0x000c /* 1000BASE-T type */
153 #define MDIO_PMA_CTRL2_1000BKX 0x000d /* 1000BASE-KX type */
154 #define MDIO_PMA_CTRL2_100BTX 0x000e /* 100BASE-TX type */
155 #define MDIO_PMA_CTRL2_10BT 0x000f /* 10BASE-T type */
159 #define MDIO_PCS_CTRL2_10GBR 0x0000 /* 10GBASE-R type */
160 #define MDIO_PCS_CTRL2_10GBX 0x0001 /* 10GBASE-X type */
161 #define MDIO_PCS_CTRL2_10GBW 0x0002 /* 10GBASE-W type */
162 #define MDIO_PCS_CTRL2_10GBT 0x0003 /* 10GBASE-T type */
170 #define MDIO_PMA_STAT2_10GBEW 0x0002 /* 10GBASE-EW ability */
171 #define MDIO_PMA_STAT2_10GBLW 0x0004 /* 10GBASE-LW ability */
172 #define MDIO_PMA_STAT2_10GBSW 0x0008 /* 10GBASE-SW ability */
173 #define MDIO_PMA_STAT2_10GBLX4 0x0010 /* 10GBASE-LX4 ability */
174 #define MDIO_PMA_STAT2_10GBER 0x0020 /* 10GBASE-ER ability */
175 #define MDIO_PMA_STAT2_10GBLR 0x0040 /* 10GBASE-LR ability */
176 #define MDIO_PMA_STAT2_10GBSR 0x0080 /* 10GBASE-SR ability */
177 #define MDIO_PMD_STAT2_TXDISAB 0x0100 /* PMD TX disable ability */
181 #define MDIO_PCS_STAT2_10GBR 0x0001 /* 10GBASE-R capable */
182 #define MDIO_PCS_STAT2_10GBX 0x0002 /* 10GBASE-X capable */
183 #define MDIO_PCS_STAT2_10GBW 0x0004 /* 10GBASE-W capable */
188 #define MDIO_PMD_TXDIS_GLOBAL 0x0001 /* Global PMD TX disable */
189 #define MDIO_PMD_TXDIS_0 0x0002 /* PMD TX disable 0 */
190 #define MDIO_PMD_TXDIS_1 0x0004 /* PMD TX disable 1 */
191 #define MDIO_PMD_TXDIS_2 0x0008 /* PMD TX disable 2 */
192 #define MDIO_PMD_TXDIS_3 0x0010 /* PMD TX disable 3 */
195 #define MDIO_PMD_RXDET_GLOBAL 0x0001 /* Global PMD RX signal detect */
196 #define MDIO_PMD_RXDET_0 0x0002 /* PMD RX signal detect 0 */
197 #define MDIO_PMD_RXDET_1 0x0004 /* PMD RX signal detect 1 */
198 #define MDIO_PMD_RXDET_2 0x0008 /* PMD RX signal detect 2 */
199 #define MDIO_PMD_RXDET_3 0x0010 /* PMD RX signal detect 3 */
202 #define MDIO_PMA_EXTABLE_10GCX4 0x0001 /* 10GBASE-CX4 ability */
203 #define MDIO_PMA_EXTABLE_10GBLRM 0x0002 /* 10GBASE-LRM ability */
204 #define MDIO_PMA_EXTABLE_10GBT 0x0004 /* 10GBASE-T ability */
205 #define MDIO_PMA_EXTABLE_10GBKX4 0x0008 /* 10GBASE-KX4 ability */
206 #define MDIO_PMA_EXTABLE_10GBKR 0x0010 /* 10GBASE-KR ability */
207 #define MDIO_PMA_EXTABLE_1000BT 0x0020 /* 1000BASE-T ability */
208 #define MDIO_PMA_EXTABLE_1000BKX 0x0040 /* 1000BASE-KX ability */
209 #define MDIO_PMA_EXTABLE_100BTX 0x0080 /* 100BASE-TX ability */
210 #define MDIO_PMA_EXTABLE_10BT 0x0100 /* 10BASE-T ability */
211 #define MDIO_PMA_EXTABLE_NBT 0x4000 /* 2.5/5GBASE-T ability */
220 /* PMA 10GBASE-T pair swap & polarity */
228 /* PMA 10GBASE-T TX power register. */
229 #define MDIO_PMA_10GBT_TXPWR_SHORT 0x0001 /* Short-reach mode */
231 /* PMA 10GBASE-T SNR registers. */
232 /* Value is SNR margin in dB, clamped to range [-127, 127], plus 0x8000. */
236 /* PMA 10GBASE-R FEC ability register. */
240 /* PCS 10GBASE-R/-T status register 1. */
243 /* PCS 10GBASE-R/-T status register 2. */
247 /* AN 10GBASE-T control register. */
248 #define MDIO_AN_10GBT_CTRL_ADV2_5G 0x0080 /* Advertise 2.5GBASE-T */
249 #define MDIO_AN_10GBT_CTRL_ADV5G 0x0100 /* Advertise 5GBASE-T */
250 #define MDIO_AN_10GBT_CTRL_ADV10G 0x1000 /* Advertise 10GBASE-T */
252 /* AN 10GBASE-T status register. */
269 #define MDIO_AN_EEE_ADV_100TX 0x0002 /* Advertise 100TX EEE cap */
271 /* Note: the two defines above can be potentially used by the user-land
276 #define MDIO_EEE_100TX MDIO_AN_EEE_ADV_100TX /* 100TX EEE cap */
295 #define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001 /* PHY XS RX local fault */
296 #define MDIO_PMA_LASI_RX_PCSLFLT 0x0008 /* PCS RX local fault */
297 #define MDIO_PMA_LASI_RX_PMALFLT 0x0010 /* PMA/PMD RX local fault */
298 #define MDIO_PMA_LASI_RX_OPTICPOWERFLT 0x0020 /* RX optical power fault */
302 #define MDIO_PMA_LASI_TX_PHYXSLFLT 0x0001 /* PHY XS TX local fault */
303 #define MDIO_PMA_LASI_TX_PCSLFLT 0x0008 /* PCS TX local fault */
304 #define MDIO_PMA_LASI_TX_PMALFLT 0x0010 /* PMA/PMD TX local fault */
327 /* UsxgmiiChannelInfo[15:0] for USXGMII in-band auto-negotiation.*/
334 #define MDIO_USXGMII_10HALF 0x0000 /* 10Mbps half-duplex */
335 #define MDIO_USXGMII_10FULL 0x1000 /* 10Mbps full-duplex */
337 #define MDIO_USXGMII_100HALF 0x0200 /* 100Mbps half-duplex */
338 #define MDIO_USXGMII_100FULL 0x1200 /* 100Mbps full-duplex */
340 #define MDIO_USXGMII_1000HALF 0x0400 /* 1000Mbps half-duplex */
341 #define MDIO_USXGMII_1000FULL 0x1400 /* 1000Mbps full-duplex */
343 #define MDIO_USXGMII_10GHALF 0x0600 /* 10Gbps half-duplex */
344 #define MDIO_USXGMII_10GFULL 0x1600 /* 10Gbps full-duplex */
346 #define MDIO_USXGMII_2500HALF 0x0800 /* 2500Mbps half-duplex */
347 #define MDIO_USXGMII_2500FULL 0x1800 /* 2500Mbps full-duplex */
349 #define MDIO_USXGMII_5000HALF 0x0a00 /* 5000Mbps half-duplex */
350 #define MDIO_USXGMII_5000FULL 0x1a00 /* 5000Mbps full-duplex */
351 #define MDIO_USXGMII_LINK 0x8000 /* PHY link with copper-side partner */