Lines Matching +full:per +full:- +full:board
1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
57 *fold in changes for Cyclom-Z -- including structures for
58 *communicating with board as well modest changes to original
63 *to support use of this file in non-kernel applications
117 /*************** CYCLOM-Z ADDITIONS ***************/
156 * CUSTOM_REG - Cyclom-Z/PCI Custom Registers Set. The driver
176 __u32 ram_wait_state; /* RAM wait-state Register */
177 __u32 uart_wait_state; /* UART wait-state Register */
178 __u32 timer_wait_state; /* timer wait-state Register */
183 * RUNTIME_9060 - PLX PCI9060ES local configuration and shared runtime
189 __u32 loc_addr_range; /* 00h - Local Address Range */
190 __u32 loc_addr_base; /* 04h - Local Address Base */
191 __u32 loc_arbitr; /* 08h - Local Arbitration */
192 __u32 endian_descr; /* 0Ch - Big/Little Endian Descriptor */
193 __u32 loc_rom_range; /* 10h - Local ROM Range */
194 __u32 loc_rom_base; /* 14h - Local ROM Base */
195 __u32 loc_bus_descr; /* 18h - Local Bus descriptor */
196 __u32 loc_range_mst; /* 1Ch - Local Range for Master to PCI */
197 __u32 loc_base_mst; /* 20h - Local Base for Master PCI */
198 __u32 loc_range_io; /* 24h - Local Range for Master IO */
199 __u32 pci_base_mst; /* 28h - PCI Base for Master PCI */
200 __u32 pci_conf_io; /* 2Ch - PCI configuration for Master IO */
205 __u32 mail_box_0; /* 40h - Mail Box 0 */
206 __u32 mail_box_1; /* 44h - Mail Box 1 */
207 __u32 mail_box_2; /* 48h - Mail Box 2 */
208 __u32 mail_box_3; /* 4Ch - Mail Box 3 */
213 __u32 pci_doorbell; /* 60h - PCI to Local Doorbell */
214 __u32 loc_doorbell; /* 64h - Local to PCI Doorbell */
215 __u32 intr_ctrl_stat; /* 68h - Interrupt Control/Status */
216 __u32 init_ctrl; /* 6Ch - EEPROM control, Init Control, etc */
219 /* Values for the Local Base Address re-map register */
239 * Cyclom-Z ZFIRM Firmware.
244 #define MAX_CHAN 64 /* max number of channels per board */
274 /* comm_parity - parity */
286 /* comm_data_l - data length and stop bits */
331 /* rs_control/rs_status RS-232 signals */
342 /* commands Host <-> Board */
345 #define C_CM_IOCTL 0x02 /* re-read CH_CTRL */
346 #define C_CM_IOCTLW 0x03 /* re-read CH_CTRL, intr when done */
347 #define C_CM_IOCTLM 0x04 /* RS-232 outputs change */
387 #define C_CM_HW_RESET 0x92 /* reset board */
390 * CH_CTRL - This per port structure contains all parameters
392 * configuration registers of a "super-serial-controller".
400 __u32 comm_baud; /* baud rate - numerically specified */
405 __u32 rs_control; /* RS-232 outputs */
406 __u32 rs_status; /* RS-232 inputs */
418 * BUF_CTRL - This per channel structure contains
438 * BOARD_CTRL - This per board structure contains all global
439 * control fields related to the board.
444 /* static info provided by the on-board CPU */
452 /* board control area */
481 * ZFW_CTRL - This is the data structure that includes all other