Lines Matching full:layout
46 * format and data layout of the buffer, and should be the only way to describe
49 * Having multiple fourcc:modifier pairs which describe the same layout should
206 * then V), but the exact Linear layout is undefined.
346 * When adding a new token please document the layout with a code comment,
362 * In future cases where a generic layout is identified before merging with a
386 * Linear Layout
388 * Just plain linear layout. Note that this is different from no specifying any
398 * Intel X-tiling layout
400 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
401 * in row-major layout. Within the tile bytes are laid out row-major, with
405 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
408 * identify the layout in a simple way for i915-specific userspace, which
415 * Intel Y-tiling layout
417 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
418 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
423 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
426 * identify the layout in a simple way for i915-specific userspace, which
433 * Intel Yf-tiling layout
435 * This is a tiled layout using 4Kb tiles in row-major layout.
437 * are arranged in four groups (two wide, two high) with column-major layout.
509 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
510 * layout. For YCbCr formats Cb/Cr components are taken in such a way that
531 * Vivante 4x4 tiling layout
533 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
534 * layout.
539 * Vivante 64x64 super-tiling layout
541 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
543 * major layout.
551 * Vivante 4x4 tiling layout for dual-pipe
553 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
555 * compared to the non-split tiled layout.
560 * Vivante 64x64 super-tiling layout for dual-pipe
562 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
564 * therefore halved compared to the non-split super-tiled layout.
571 * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
578 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80,
581 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies
598 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
615 * tables of all GPUs >= NV50. It affects the exact layout of bits
623 * since the modifier should define the layout of the associated
629 * kind and bit layout has changed at various points.
636 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
638 * page kind and block linear swizzles. This causes the layout of
642 * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
643 * 1 = Desktop GPU and Tegra Xavier+ Layout
648 * 1 = ROP/3D, layout 1, exact compression format implied by Page
650 * 2 = ROP/3D, layout 2, exact compression format implied by Page
668 /* To grandfather in prior block linear format modifiers to the above layout,
684 * 16Bx2 Block Linear layout, used by Tegra K1 and later
740 * This is the primary layout that the V3D GPU can texture from (it
888 * AFBC sparse layout
909 * AFBC tiled layout
911 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
915 * When the tiled layout is used, the buffer size (in pixels) must be aligned
931 * Indicates that the buffer is allocated in a layout safe for front-buffer
948 * The buffer layout is the same as for AFBC buffers without USM set, this only
994 * The first 8 bits of the mode defines the layout, then the following 8 bits
995 * defines the options changing the layout.
998 * combinations of layout and options.
1013 * Amlogic FBC Basic Layout
1015 * The basic layout is composed of:
1020 * This layout is transferrable between Amlogic SoCs supporting this modifier.
1025 * Amlogic FBC Scatter Memory layout
1028 * frames content to optimize memory access and layout.
1035 * Due to the nature of the layout, these buffers are not expected to
1044 /* Amlogic FBC Layout Options Bit Mask */
1053 * This mode reduces body layout to 3072 bytes per 64x32 superblock with
1054 * the basic layout and 3200 bytes per 64x32 superblock combined with
1055 * the scatter layout.