Lines Matching +full:6 +full:- +full:bit
1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define ANA_ANAGEFIL_B_DOM_EN BIT(22)
12 #define ANA_ANAGEFIL_B_DOM_VAL BIT(21)
13 #define ANA_ANAGEFIL_AGE_LOCKED BIT(20)
14 #define ANA_ANAGEFIL_PID_EN BIT(19)
18 #define ANA_ANAGEFIL_VID_EN BIT(13)
24 #define ANA_STORMLIMIT_CFG_STORM_RATE(x) (((x) << 3) & GENMASK(6, 3))
25 #define ANA_STORMLIMIT_CFG_STORM_RATE_M GENMASK(6, 3)
26 #define ANA_STORMLIMIT_CFG_STORM_RATE_X(x) (((x) & GENMASK(6, 3)) >> 3)
27 #define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2)
31 #define ANA_AUTOAGE_AGE_FAST BIT(21)
35 #define ANA_AUTOAGE_AUTOAGE_LOCKED BIT(0)
37 #define ANA_MACTOPTIONS_REDUCED_TABLE BIT(1)
38 #define ANA_MACTOPTIONS_SHADOW BIT(0)
43 #define ANA_AGENCTRL_IGNORE_DMAC_FLAGS BIT(11)
44 #define ANA_AGENCTRL_IGNORE_SMAC_FLAGS BIT(10)
45 #define ANA_AGENCTRL_FLOOD_SPECIAL BIT(9)
46 #define ANA_AGENCTRL_FLOOD_IGNORE_VLAN BIT(8)
47 #define ANA_AGENCTRL_MIRROR_CPU BIT(7)
48 #define ANA_AGENCTRL_LEARN_CPU_COPY BIT(6)
49 #define ANA_AGENCTRL_LEARN_FWD_KILL BIT(5)
50 #define ANA_AGENCTRL_LEARN_IGNORE_VLAN BIT(4)
51 #define ANA_AGENCTRL_CPU_CPU_KILL_ENA BIT(3)
52 #define ANA_AGENCTRL_GREEN_COUNT_MODE BIT(2)
53 #define ANA_AGENCTRL_YELLOW_COUNT_MODE BIT(1)
54 #define ANA_AGENCTRL_RED_COUNT_MODE BIT(0)
61 #define ANA_FLOODING_FLD_BROADCAST(x) (((x) << 6) & GENMASK(11, 6))
62 #define ANA_FLOODING_FLD_BROADCAST_M GENMASK(11, 6)
63 #define ANA_FLOODING_FLD_BROADCAST_X(x) (((x) & GENMASK(11, 6)) >> 6)
73 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL(x) (((x) << 6) & GENMASK(11, 6))
74 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_M GENMASK(11, 6)
75 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_X(x) (((x) & GENMASK(11, 6)) >> 6)
84 #define ANA_SFLOW_CFG_SF_SAMPLE_RX BIT(1)
85 #define ANA_SFLOW_CFG_SF_SAMPLE_TX BIT(0)
89 #define ANA_PORT_MODE_REDTAG_PARSE_CFG BIT(3)
93 #define ANA_PORT_MODE_L3_PARSE_CFG BIT(0)
111 #define ANA_TABLES_STREAMDATA_SSID_VALID BIT(16)
115 #define ANA_TABLES_STREAMDATA_SFID_VALID BIT(8)
119 #define ANA_TABLES_MACACCESS_MAC_CPU_COPY BIT(15)
120 #define ANA_TABLES_MACACCESS_SRC_KILL BIT(14)
121 #define ANA_TABLES_MACACCESS_IGNORE_VLAN BIT(13)
122 #define ANA_TABLES_MACACCESS_AGED_FLAG BIT(12)
123 #define ANA_TABLES_MACACCESS_VALID BIT(11)
138 #define MACACCESS_CMD_READ 6
150 #define ANA_TABLES_VLANTIDX_VLAN_SEC_FWD_ENA BIT(17)
151 #define ANA_TABLES_VLANTIDX_VLAN_FLOOD_DIS BIT(16)
152 #define ANA_TABLES_VLANTIDX_VLAN_PRIV_VLAN BIT(15)
153 #define ANA_TABLES_VLANTIDX_VLAN_LEARN_DISABLED BIT(14)
154 #define ANA_TABLES_VLANTIDX_VLAN_MIRROR BIT(13)
155 #define ANA_TABLES_VLANTIDX_VLAN_SRC_CHK BIT(12)
171 #define ANA_TABLES_ISDXTIDX_ISDX_ES0_KEY_ENA BIT(14)
172 #define ANA_TABLES_ISDXTIDX_ISDX_FORCE_ENA BIT(10)
187 #define ANA_TABLES_STREAMACCESS_SEQ_GEN_REC_ENA BIT(3)
188 #define ANA_TABLES_STREAMACCESS_GEN_REC_TYPE BIT(2)
198 #define ANA_TABLES_STREAMTIDX_FORCE_SF_BEHAVIOUR BIT(14)
202 #define ANA_TABLES_STREAMTIDX_RESET_ON_ROGUE BIT(7)
203 #define ANA_TABLES_STREAMTIDX_REDTAG_POP BIT(6)
204 #define ANA_TABLES_STREAMTIDX_STREAM_SPLIT BIT(5)
211 #define ANA_TABLES_SEQ_MASK_INPUT_PORT_MASK(x) ((x) & GENMASK(6, 0))
212 #define ANA_TABLES_SEQ_MASK_INPUT_PORT_MASK_M GENMASK(6, 0)
217 #define ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA BIT(0)
219 #define ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA BIT(22)
223 #define ANA_TABLES_SFIDACCESS_FORCE_BLOCK BIT(18)
230 #define ANA_TABLES_SFIDTIDX_SGID_VALID BIT(26)
234 #define ANA_TABLES_SFIDTIDX_POL_ENA BIT(17)
247 #define ANA_SG_ACCESS_CTRL_CONFIG_CHANGE BIT(28)
254 #define ANA_SG_CONFIG_REG_3_GATE_ENABLE BIT(20)
258 #define ANA_SG_CONFIG_REG_3_INIT_GATE_STATE BIT(25)
264 #define ANA_SG_GCL_GS_CONFIG_GATE_STATE BIT(4)
270 #define ANA_SG_STATUS_REG_3_GATE_STATE BIT(16)
274 #define ANA_SG_STATUS_REG_3_CONFIG_PENDING BIT(24)
278 #define ANA_PORT_VLAN_CFG_VLAN_VID_AS_ISDX BIT(21)
279 #define ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA BIT(20)
283 #define ANA_PORT_VLAN_CFG_VLAN_INNER_TAG_ENA BIT(17)
284 #define ANA_PORT_VLAN_CFG_VLAN_TAG_TYPE BIT(16)
285 #define ANA_PORT_VLAN_CFG_VLAN_DEI BIT(15)
294 #define ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA BIT(6)
295 #define ANA_PORT_DROP_CFG_DROP_S_TAGGED_ENA BIT(5)
296 #define ANA_PORT_DROP_CFG_DROP_C_TAGGED_ENA BIT(4)
297 #define ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA BIT(3)
298 #define ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA BIT(2)
299 #define ANA_PORT_DROP_CFG_DROP_NULL_MAC_ENA BIT(1)
300 #define ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA BIT(0)
304 #define ANA_PORT_QOS_CFG_DP_DEFAULT_VAL BIT(8)
308 #define ANA_PORT_QOS_CFG_QOS_DSCP_ENA BIT(4)
309 #define ANA_PORT_QOS_CFG_QOS_PCP_ENA BIT(3)
310 #define ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA BIT(2)
316 #define ANA_PORT_VCAP_CFG_S1_ENA BIT(14)
329 #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG(x) (((x) << 4) & GENMASK(6, 4))
330 #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG_M GENMASK(6, 4)
331 #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG_X(x) (((x) & GENMASK(6, 4)) >> 4)
346 #define ANA_PORT_VCAP_S2_CFG_S2_ENA BIT(14)
356 #define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS(x) (((x) << 6) & GENMASK(7, 6))
357 #define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_M GENMASK(7, 6)
358 #define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_X(x) (((x) & GENMASK(7, 6)) >> 6)
368 #define ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL BIT(3)
374 #define ANA_PORT_CPU_FWD_CFG_CPU_VRAP_REDIR_ENA BIT(7)
375 #define ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA BIT(6)
376 #define ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA BIT(5)
377 #define ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA BIT(4)
378 #define ANA_PORT_CPU_FWD_CFG_CPU_SRC_COPY_ENA BIT(3)
379 #define ANA_PORT_CPU_FWD_CFG_CPU_ALLBRIDGE_DROP_ENA BIT(2)
380 #define ANA_PORT_CPU_FWD_CFG_CPU_ALLBRIDGE_REDIR_ENA BIT(1)
381 #define ANA_PORT_CPU_FWD_CFG_CPU_OAM_ENA BIT(0)
409 #define ANA_PORT_PORT_CFG_SRC_MIRROR_ENA BIT(15)
410 #define ANA_PORT_PORT_CFG_LIMIT_DROP BIT(14)
411 #define ANA_PORT_PORT_CFG_LIMIT_CPU BIT(13)
412 #define ANA_PORT_PORT_CFG_LOCKED_PORTMOVE_DROP BIT(12)
413 #define ANA_PORT_PORT_CFG_LOCKED_PORTMOVE_CPU BIT(11)
414 #define ANA_PORT_PORT_CFG_LEARNDROP BIT(10)
415 #define ANA_PORT_PORT_CFG_LEARNCPU BIT(9)
416 #define ANA_PORT_PORT_CFG_LEARNAUTO BIT(8)
417 #define ANA_PORT_PORT_CFG_LEARN_ENA BIT(7)
418 #define ANA_PORT_PORT_CFG_RECV_ENA BIT(6)
422 #define ANA_PORT_PORT_CFG_USE_B_DOM_TBL BIT(1)
423 #define ANA_PORT_PORT_CFG_LSR_MODE BIT(0)
427 #define ANA_PORT_POL_CFG_POL_CPU_REDIR_8021 BIT(19)
428 #define ANA_PORT_POL_CFG_POL_CPU_REDIR_IP BIT(18)
429 #define ANA_PORT_POL_CFG_PORT_POL_ENA BIT(17)
438 #define ANA_PORT_PTP_CFG_PTP_BACKPLANE_MODE BIT(0)
447 #define ANA_PORT_SFID_CFG_SFID_VALID BIT(8)
464 #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P(x) (((x) << 6) & GENMASK(10, 6))
465 #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P_M GENMASK(10, 6)
466 #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P_X(x) (((x) & GENMASK(10, 6)) >> 6)
470 #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_ENA BIT(0)
480 #define ANA_IPT_IPT_PPT_IDX(x) ((x) & GENMASK(6, 0))
481 #define ANA_IPT_IPT_PPT_IDX_M GENMASK(6, 0)
487 #define ANA_FID_MAP_FID_MAP_FID_C_VAL(x) (((x) << 6) & GENMASK(11, 6))
488 #define ANA_FID_MAP_FID_MAP_FID_C_VAL_M GENMASK(11, 6)
489 #define ANA_FID_MAP_FID_MAP_FID_C_VAL_X(x) (((x) & GENMASK(11, 6)) >> 6)
493 #define ANA_AGGR_CFG_AC_RND_ENA BIT(7)
494 #define ANA_AGGR_CFG_AC_DMAC_ENA BIT(6)
495 #define ANA_AGGR_CFG_AC_SMAC_ENA BIT(5)
496 #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA BIT(4)
497 #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA BIT(3)
498 #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA BIT(2)
499 #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA BIT(1)
500 #define ANA_AGGR_CFG_AC_ISDX_ENA BIT(0)
523 #define ANA_CPUQ_CFG_CPUQ_LRN(x) (((x) << 6) & GENMASK(8, 6))
524 #define ANA_CPUQ_CFG_CPUQ_LRN_M GENMASK(8, 6)
525 #define ANA_CPUQ_CFG_CPUQ_LRN_X(x) (((x) & GENMASK(8, 6)) >> 6)
534 #define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(x) (((x) << 6) & GENMASK(8, 6))
535 #define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL_M GENMASK(8, 6)
536 #define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL_X(x) (((x) & GENMASK(8, 6)) >> 6)
545 #define ANA_DSCP_CFG_DP_DSCP_VAL BIT(11)
552 #define ANA_DSCP_CFG_DSCP_TRUST_ENA BIT(1)
553 #define ANA_DSCP_CFG_DSCP_REWR_ENA BIT(0)
567 #define ANA_VRAP_CFG_VRAP_VLAN_AWARE_ENA BIT(12)
571 #define ANA_DISCARD_CFG_DROP_TAGGING_ISDX0 BIT(3)
572 #define ANA_DISCARD_CFG_DROP_CTRLPROT_ISDX0 BIT(2)
573 #define ANA_DISCARD_CFG_DROP_TAGGING_S2_ENA BIT(1)
574 #define ANA_DISCARD_CFG_DROP_CTRLPROT_S2_ENA BIT(0)
576 #define ANA_FID_CFG_VID_MC_ENA BIT(0)
580 #define ANA_POL_PIR_CFG_PIR_RATE(x) (((x) << 6) & GENMASK(20, 6))
581 #define ANA_POL_PIR_CFG_PIR_RATE_M GENMASK(20, 6)
582 #define ANA_POL_PIR_CFG_PIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6)
588 #define ANA_POL_CIR_CFG_CIR_RATE(x) (((x) << 6) & GENMASK(20, 6))
589 #define ANA_POL_CIR_CFG_CIR_RATE_M GENMASK(20, 6)
590 #define ANA_POL_CIR_CFG_CIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6)
602 #define ANA_POL_MODE_CFG_DLB_COUPLED BIT(2)
603 #define ANA_POL_MODE_CFG_CIR_ENA BIT(1)
604 #define ANA_POL_MODE_CFG_OVERSHOOT_ENA BIT(0)
614 #define ANA_POL_FLOWC_POL_FLOWC BIT(0)
622 #define ANA_POL_MISC_CFG_POL_CLOSE_ALL BIT(1)
623 #define ANA_POL_MISC_CFG_POL_LEAK_DIS BIT(0)