Lines Matching +full:pwm +full:- +full:channels +full:- +full:mask

17  * Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
18  * three general-purpose 16-bit timers.  These timers share one register bank.
23  * clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
37  * struct atmel_tcb_config - SoC data for a Timer/Counter Block
50  * struct atmel_tc - information about a Timer/Counter Block
55  * @irq: irq for each of the three channels
56  * @clk: internal clock source for each of the three channels
61  * while on others, all TC channels share the same clock and IRQ.
83 /* platform-specific ATMEL_TC_TIMER_CLOCKx divisors (0 means 32KiHz) */
88  * Two registers have block-wide controls.  These are: configuring the three
89  * "external" clocks (or event sources) used by the timer channels; and
119  * Each TC block has three "channels", each with one counter and controls.
122  * when it's not "external") is silicon-specific.  AT91 platforms use one
123  * set of definitions; AVR32 platforms use a different set.  Don't hard-wire
129  * generation mode (including PWM) or "capture" mode (to time events).  In
133  * PWM output, and TIOB as either another PWM or as a trigger.  Capture mode
250 #define ATMEL_TC_SR	0x20		/* status (read-only) */
251 /* Status-only flags */
256 #define ATMEL_TC_IER	0x24		/* interrupt enable (write-only) */
257 #define ATMEL_TC_IDR	0x28		/* interrupt disable (write-only) */
258 #define ATMEL_TC_IMR	0x2c		/* interrupt mask (read-only) */