Lines Matching refs:V4L2_HEVC_DPB_ENTRIES_NUM_MAX
127 #define V4L2_HEVC_DPB_ENTRIES_NUM_MAX 16 macro
138 __s8 delta_luma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
139 __s8 luma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
140 __s8 delta_chroma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
141 __s8 chroma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
143 __s8 delta_luma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
144 __s8 luma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
145 __s8 delta_chroma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
146 __s8 chroma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
194 __u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
195 __u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
204 struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];