Lines Matching +full:0 +full:xc00000
24 #define SSB_EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
25 #define SSB_EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
26 #define SSB_EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
27 #define SSB_EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
47 #define SSB_EXTIF_CTL 0x0000
48 #define SSB_EXTIF_CTL_UARTEN (1 << 0) /* UART enable */
49 #define SSB_EXTIF_EXTSTAT 0x0004
50 #define SSB_EXTIF_EXTSTAT_EMODE (1 << 0) /* Endian mode (ro) */
53 #define SSB_EXTIF_PCMCIA_CFG 0x0010
54 #define SSB_EXTIF_PCMCIA_MEMWAIT 0x0014
55 #define SSB_EXTIF_PCMCIA_ATTRWAIT 0x0018
56 #define SSB_EXTIF_PCMCIA_IOWAIT 0x001C
57 #define SSB_EXTIF_PROG_CFG 0x0020
58 #define SSB_EXTIF_PROG_WAITCNT 0x0024
59 #define SSB_EXTIF_FLASH_CFG 0x0028
60 #define SSB_EXTIF_FLASH_WAITCNT 0x002C
61 #define SSB_EXTIF_WATCHDOG 0x0040
62 #define SSB_EXTIF_CLOCK_N 0x0044
63 #define SSB_EXTIF_CLOCK_SB 0x0048
64 #define SSB_EXTIF_CLOCK_PCI 0x004C
65 #define SSB_EXTIF_CLOCK_MII 0x0050
66 #define SSB_EXTIF_GPIO_IN 0x0060
67 #define SSB_EXTIF_GPIO_OUT_BASE 0x0064
68 #define SSB_EXTIF_GPIO_OUTEN_BASE 0x0068
69 #define SSB_EXTIF_EJTAG_OUTEN 0x0090
70 #define SSB_EXTIF_GPIO_INTPOL 0x0094
71 #define SSB_EXTIF_GPIO_INTMASK 0x0098
72 #define SSB_EXTIF_UART_DATA 0x0300
73 #define SSB_EXTIF_UART_TIMER 0x0310
74 #define SSB_EXTIF_UART_FCR 0x0320
75 #define SSB_EXTIF_UART_LCR 0x0330
76 #define SSB_EXTIF_UART_MCR 0x0340
77 #define SSB_EXTIF_UART_LSR 0x0350
78 #define SSB_EXTIF_UART_MSR 0x0360
79 #define SSB_EXTIF_UART_SCRATCH 0x0370
85 #define SSB_EXTCFG_EN (1 << 0) /* enable */
86 #define SSB_EXTCFG_MODE 0xE /* mode */
88 #define SSB_EXTCFG_MODE_FLASH 0x0 /* flash/asynchronous mode */
89 #define SSB_EXTCFG_MODE_SYNC 0x2 /* synchronous mode */
90 #define SSB_EXTCFG_MODE_PCMCIA 0x4 /* pcmcia mode */
91 #define SSB_EXTCFG_DS16 (1 << 4) /* destsize: 0=8bit, 1=16bit */
93 #define SSB_EXTCFG_CLKDIV 0xC0 /* clock divider */
95 #define SSB_EXTCFG_CLKDIV_2 0x0 /* backplane/2 */
96 #define SSB_EXTCFG_CLKDIV_3 0x40 /* backplane/3 */
97 #define SSB_EXTCFG_CLKDIV_4 0x80 /* backplane/4 */
102 #define SSB_PCMCIA_MEMW_0 0x0000003F /* waitcount0 */
103 #define SSB_PCMCIA_MEMW_1 0x00001F00 /* waitcount1 */
105 #define SSB_PCMCIA_MEMW_2 0x001F0000 /* waitcount2 */
107 #define SSB_PCMCIA_MEMW_3 0x1F000000 /* waitcount3 */
111 #define SSB_PCMCIA_ATTW_0 0x0000003F /* waitcount0 */
112 #define SSB_PCMCIA_ATTW_1 0x00001F00 /* waitcount1 */
114 #define SSB_PCMCIA_ATTW_2 0x001F0000 /* waitcount2 */
116 #define SSB_PCMCIA_ATTW_3 0x1F000000 /* waitcount3 */
120 #define SSB_PCMCIA_IOW_0 0x0000003F /* waitcount0 */
121 #define SSB_PCMCIA_IOW_1 0x00001F00 /* waitcount1 */
123 #define SSB_PCMCIA_IOW_2 0x001F0000 /* waitcount2 */
125 #define SSB_PCMCIA_IOW_3 0x1F000000 /* waitcount3 */
129 #define SSB_PROG_WCNT_0 0x0000001F /* waitcount0 */
130 #define SSB_PROG_WCNT_1 0x00001F00 /* waitcount1 */
132 #define SSB_PROG_WCNT_2 0x001F0000 /* waitcount2 */
134 #define SSB_PROG_WCNT_3 0x1F000000 /* waitcount3 */
137 #define SSB_PROG_W0 0x0000000C
138 #define SSB_PROG_W1 0x00000A00
139 #define SSB_PROG_W2 0x00020000
140 #define SSB_PROG_W3 0x01000000
143 #define SSB_FLASH_WCNT_0 0x0000001F /* waitcount0 */
144 #define SSB_FLASH_WCNT_1 0x00001F00 /* waitcount1 */
146 #define SSB_FLASH_WCNT_2 0x001F0000 /* waitcount2 */
148 #define SSB_FLASH_WCNT_3 0x1F000000 /* waitcount3 */
200 return 0; in ssb_extif_available()
217 return 0; in ssb_extif_watchdog_timer_set()
222 return 0; in ssb_extif_gpio_in()
228 return 0; in ssb_extif_gpio_out()
234 return 0; in ssb_extif_gpio_outen()
240 return 0; in ssb_extif_gpio_polarity()
246 return 0; in ssb_extif_gpio_intmask()
253 return 0; in ssb_extif_serial_init()