Lines Matching +full:switch +full:- +full:frequency +full:- +full:hz
1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
71 * enum sdw_slave_status - Slave status
89 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare
90 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare
100 * enum sdw_command_response - Command response as defined by SDW spec
180 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a
191 * enum sdw_dpn_type - Data port types
206 * enum sdw_clk_stop_mode - Clock Stop modes
209 * @SDW_CLK_STOP_MODE1: Slave may have entered a deeper power-saving mode,
218 * struct sdw_dp0_prop - DP0 properties
229 * implementation-defined interrupts
246 * struct sdw_dpn_audio_mode - Audio mode properties for DPn
247 * @bus_min_freq: Minimum bus frequency, in Hz
248 * @bus_max_freq: Maximum bus frequency, in Hz
250 * @bus_freq: Discrete bus frequencies, in Hz
251 * @min_freq: Minimum sampling frequency, in Hz
252 * @max_freq: Maximum sampling bus frequency, in Hz
253 * @num_freq: Number of discrete sampling frequency supported
254 * @freq: Discrete sampling frequencies, in Hz
259 * changed to a frequency supported by this mode or compatible modes
278 * struct sdw_dpn_prop - Data Port DPn properties
291 * @ch_prep_timeout: Port-specific timeout value, in milliseconds
293 * implementation-defined interrupts
334 * struct sdw_slave_prop - SoundWire Slave properties
336 * @wake_capable: Wake-up events are supported
338 * @clk_stop_mode1: Clock-Stop Mode 1 is supported
340 * @clk_stop_timeout: Worst-case latency of the Clock Stop Prepare State
342 * @ch_prep_timeout: Worst-case latency of the Channel Prepare State Machine
345 * state machine (P=1 SCSP_SM) after exit from clock-stop mode1
390 * struct sdw_master_prop - Master properties
392 * @clk_stop_modes: Bitmap, bit N set when clock-stop-modeN supported
393 * @max_clk_freq: Maximum Bus clock frequency, in Hz
396 * @num_clk_freq: Number of clock frequencies supported, in Hz
397 * @clk_freq: Clock frequencies supported, in Hz
398 * @default_frame_rate: Controller default Frame rate, in Hz
404 * @mclk_freq: clock reference passed to SoundWire Master, in Hz.
405 * @hw_disabled: if true, the Master is not functional, typically due to pin-mux
434 * struct sdw_slave_id - Slave ID
452 * Helper macros to extract the MIPI-defined IDs
481 * struct sdw_slave_intr_status - Slave interrupt status
491 * sdw_reg_bank - SoundWire register banks
503 * @clk_freq: Clock frequency, in Hz
516 * struct sdw_prepare_ch: Prepare/De-prepare Data Port channel
520 * @prepare: Prepare (true) /de-prepare (false) channel
552 * @max_dr_freq: Maximum double rate clock frequency supported, in Hz
553 * @curr_dr_freq: Current double rate clock frequency, in Hz
603 * struct sdw_slave - SoundWire Slave
614 * @dev_num_sticky: one-time static Device Number assigned by Bus
618 * Slave state changes/implementation-defined interrupts
624 * @unattach_request: mask field to keep track why the Slave re-attached and
625 * was re-initialized. This is useful to deal with potential race conditions
658 * struct sdw_master_device - SoundWire 'Master Device' representation
734 * during a bank switch without any artifacts in audio stream.
789 * struct sdw_defer - SDW deffered message
801 * struct sdw_master_ops - Master driver ops
807 * @pre_bank_switch: Callback for pre bank switch
808 * @post_bank_switch: Callback for post bank switch
828 * struct sdw_bus - SoundWire bus
829 * @dev: Shortcut to &bus->md->dev to avoid changing the entire code.
832 * @id: bus system-wide unique id
849 * @bank_switch_timeout: Bank switch timeout computed
854 * hardware-based synchronization is required. This value is only
855 * meaningful if multi_link is set. If set to 1, hardware-based
902 * @frame_rate: Audio frame rate of the stream, in Hz
924 * @SDW_STREAM_DEPREPARED: Stream de-prepared
940 * @rate: Sampling frequency, in Hz