Lines Matching +full:0 +full:xf003
25 #define SDLA_CONTROL_WND 0xE000
27 #define SDLA_502_CMD_BUF 0xEF60
28 #define SDLA_502_RCV_BUF 0xA900
29 #define SDLA_502_TXN_AVAIL 0xFFF1
30 #define SDLA_502_RCV_AVAIL 0xFFF2
31 #define SDLA_502_EVENT_FLAGS 0xFFF3
32 #define SDLA_502_MDM_STATUS 0xFFF4
33 #define SDLA_502_IRQ_INTERFACE 0xFFFD
34 #define SDLA_502_IRQ_PERMISSION 0xFFFE
35 #define SDLA_502_DATA_OFS 0x0010
37 #define SDLA_508_CMD_BUF 0xE000
38 #define SDLA_508_TXBUF_INFO 0xF100
39 #define SDLA_508_RXBUF_INFO 0xF120
40 #define SDLA_508_EVENT_FLAGS 0xF003
41 #define SDLA_508_MDM_STATUS 0xF004
42 #define SDLA_508_IRQ_INTERFACE 0xF010
43 #define SDLA_508_IRQ_PERMISSION 0xF011
44 #define SDLA_508_TSE_OFFSET 0xF012
47 #define SDLA_EVENT_STATUS 0x01
48 #define SDLA_EVENT_DLCI_STATUS 0x02
49 #define SDLA_EVENT_BAD_DLCI 0x04
50 #define SDLA_EVENT_LINK_DOWN 0x40
53 #define SDLA_INTR_RX 0x01
54 #define SDLA_INTR_TX 0x02
55 #define SDLA_INTR_MODEM 0x04
56 #define SDLA_INTR_COMPLETE 0x08
57 #define SDLA_INTR_STATUS 0x10
58 #define SDLA_INTR_TIMER 0x20
61 #define SDLA_DLCI_DELETED 0x01
62 #define SDLA_DLCI_ACTIVE 0x02
63 #define SDLA_DLCI_WAITING 0x04
64 #define SDLA_DLCI_NEW 0x08
65 #define SDLA_DLCI_INCLUDED 0x40
68 #define SDLA_INFORMATION_WRITE 0x01
69 #define SDLA_INFORMATION_READ 0x02
70 #define SDLA_ISSUE_IN_CHANNEL_SIGNAL 0x03
71 #define SDLA_SET_DLCI_CONFIGURATION 0x10
72 #define SDLA_READ_DLCI_CONFIGURATION 0x11
73 #define SDLA_DISABLE_COMMUNICATIONS 0x12
74 #define SDLA_ENABLE_COMMUNICATIONS 0x13
75 #define SDLA_READ_DLC_STATUS 0x14
76 #define SDLA_READ_DLC_STATISTICS 0x15
77 #define SDLA_FLUSH_DLC_STATISTICS 0x16
78 #define SDLA_LIST_ACTIVE_DLCI 0x17
79 #define SDLA_FLUSH_INFORMATION_BUFFERS 0x18
80 #define SDLA_ADD_DLCI 0x20
81 #define SDLA_DELETE_DLCI 0x21
82 #define SDLA_ACTIVATE_DLCI 0x22
83 #define SDLA_DEACTIVATE_DLCI 0x23
84 #define SDLA_READ_MODEM_STATUS 0x30
85 #define SDLA_SET_MODEM_STATUS 0x31
86 #define SDLA_READ_COMMS_ERR_STATS 0x32
87 #define SDLA_FLUSH_COMMS_ERR_STATS 0x33
88 #define SDLA_READ_CODE_VERSION 0x40
89 #define SDLA_SET_IRQ_TRIGGER 0x50
90 #define SDLA_GET_IRQ_TRIGGER 0x51
93 #define SDLA_ICS_LINK_VERIFY 0x02
94 #define SDLA_ICS_STATUS_ENQ 0x03
97 #define SDLA_MODEM_DTR_HIGH 0x01
98 #define SDLA_MODEM_RTS_HIGH 0x02
99 #define SDLA_MODEM_DCD_HIGH 0x08
100 #define SDLA_MODEM_CTS_HIGH 0x20
103 #define SDLA_MODEM_DCD_LOW 0x01
104 #define SDLA_MODEM_CTS_LOW 0x02
107 #define SDLA_RET_OK 0x00
108 #define SDLA_RET_COMMUNICATIONS 0x01
109 #define SDLA_RET_CHANNEL_INACTIVE 0x02
110 #define SDLA_RET_DLCI_INACTIVE 0x03
111 #define SDLA_RET_DLCI_CONFIG 0x04
112 #define SDLA_RET_BUF_TOO_BIG 0x05
113 #define SDLA_RET_NO_DATA 0x05
114 #define SDLA_RET_BUF_OVERSIZE 0x06
115 #define SDLA_RET_CIR_OVERFLOW 0x07
116 #define SDLA_RET_NO_BUFS 0x08
117 #define SDLA_RET_TIMEOUT 0x0A
118 #define SDLA_RET_MODEM 0x10
119 #define SDLA_RET_CHANNEL_OFF 0x11
120 #define SDLA_RET_CHANNEL_ON 0x12
121 #define SDLA_RET_DLCI_STATUS 0x13
122 #define SDLA_RET_DLCI_UNKNOWN 0x14
123 #define SDLA_RET_COMMAND_INVALID 0x1F
126 #define SDLA_DIRECT_RECV 0x0080
127 #define SDLA_TX_NO_EXCEPT 0x0020
128 #define SDLA_NO_ICF_MSGS 0x1000
129 #define SDLA_TX50_RX50 0x0000
130 #define SDLA_TX70_RX30 0x2000
131 #define SDLA_TX30_RX70 0x4000
134 #define SDLA_IRQ_RECEIVE 0x01
135 #define SDLA_IRQ_TRANSMIT 0x02
136 #define SDLA_IRQ_MODEM_STAT 0x04
137 #define SDLA_IRQ_COMMAND 0x08
138 #define SDLA_IRQ_CHANNEL 0x10
139 #define SDLA_IRQ_TIMER 0x20
142 #define SDLA_8K_WINDOW 0x01
143 #define SDLA_S502_SEG_A 0x10
144 #define SDLA_S502_SEG_C 0x20
145 #define SDLA_S502_SEG_D 0x00
146 #define SDLA_S502_SEG_E 0x30
147 #define SDLA_S507_SEG_A 0x00
148 #define SDLA_S507_SEG_B 0x40
149 #define SDLA_S507_SEG_C 0x80
150 #define SDLA_S507_SEG_E 0xC0
151 #define SDLA_S508_SEG_A 0x00
152 #define SDLA_S508_SEG_C 0x10
153 #define SDLA_S508_SEG_D 0x08
154 #define SDLA_S508_SEG_E 0x18
157 #define SDLA_IO_EXTENTS 0x04
159 #define SDLA_REG_CONTROL 0x00
160 #define SDLA_REG_PC_WINDOW 0x01 /* offset for PC window select latch */
161 #define SDLA_REG_Z80_WINDOW 0x02 /* offset for Z80 window select latch */
162 #define SDLA_REG_Z80_CONTROL 0x03 /* offset for Z80 control latch */
164 #define SDLA_S502_STS 0x00 /* status reg for 502, 502E, 507 */
165 #define SDLA_S508_GNRL 0x00 /* general purp. reg for 508 */
166 #define SDLA_S508_STS 0x01 /* status reg for 508 */
167 #define SDLA_S508_IDR 0x02 /* ID reg for 508 */
170 #define SDLA_S502A_START 0x00 /* start the CPU */
171 #define SDLA_S502A_INTREQ 0x02
172 #define SDLA_S502A_INTEN 0x04
173 #define SDLA_S502A_HALT 0x08 /* halt the CPU */
174 #define SDLA_S502A_NMI 0x10 /* issue an NMI to the CPU */
176 #define SDLA_S502E_CPUEN 0x01
177 #define SDLA_S502E_ENABLE 0x02
178 #define SDLA_S502E_INTACK 0x04
180 #define SDLA_S507_ENABLE 0x01
181 #define SDLA_S507_IRQ3 0x00
182 #define SDLA_S507_IRQ4 0x20
183 #define SDLA_S507_IRQ5 0x40
184 #define SDLA_S507_IRQ7 0x60
185 #define SDLA_S507_IRQ10 0x80
186 #define SDLA_S507_IRQ11 0xA0
187 #define SDLA_S507_IRQ12 0xC0
188 #define SDLA_S507_IRQ15 0xE0
190 #define SDLA_HALT 0x00
191 #define SDLA_CPUEN 0x02
192 #define SDLA_MEMEN 0x04
193 #define SDLA_S507_EPROMWR 0x08
194 #define SDLA_S507_EPROMCLK 0x10
195 #define SDLA_S508_INTRQ 0x08
196 #define SDLA_S508_INTEN 0x10