Lines Matching full:ssp
5 * This driver supports the following PXA CPU/SSP ports:-
7 * PXA250 SSP
8 * PXA255 SSP, NSSP
9 * PXA26x SSP, NSSP, ASSP
29 * SSP Serial Port Registers
30 * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
34 #define SSCR0 (0x00) /* SSP Control Register 0 */
35 #define SSCR1 (0x04) /* SSP Control Register 1 */
36 #define SSSR (0x08) /* SSP Status Register */
37 #define SSITR (0x0C) /* SSP Interrupt Test Register */
38 #define SSDR (0x10) /* SSP Data Write/Data Read Register */
40 #define SSTO (0x28) /* SSP Time Out Register */
41 #define DDS_RATE (0x28) /* SSP DDS Clock Rate Register (Intel Quark) */
42 #define SSPSP (0x2C) /* SSP Programmable Serial Protocol */
43 #define SSTSA (0x30) /* SSP Tx Timeslot Active */
44 #define SSRSA (0x34) /* SSP Rx Timeslot Active */
45 #define SSTSS (0x38) /* SSP Timeslot Status */
46 #define SSACD (0x3C) /* SSP Audio Clock Divider */
47 #define SSACDD (0x40) /* SSP Audio Clock Dither Divider */
54 #define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
81 #define SSSR_BSY BIT(4) /* SSP Busy */
127 /* extra bits in PXA255, PXA26x and PXA27x SSP ports */
184 /* LPSS SSP */
192 /* LPT/WPT SSP */
193 #define SSCR2 (0x40) /* SSP Command / Status 2 */
194 #define SSPSP2 (0x44) /* SSP Programmable Serial Protocol 2 */
233 * pxa_ssp_write_reg - Write to a SSP register
235 * @dev: SSP device to access
245 * pxa_ssp_read_reg - Read from a SSP register
247 * @dev: SSP device to access
270 static inline void pxa_ssp_free(struct ssp_device *ssp) {} in pxa_ssp_free() argument