Lines Matching +full:0 +full:- +full:indexed
1 /* SPDX-License-Identifier: GPL-2.0 */
21 #define OMAP1_DMA_TOUT_IRQ (1 << 0)
40 #define OMAP_DMA_DATA_TYPE_S8 0x00
41 #define OMAP_DMA_DATA_TYPE_S16 0x01
42 #define OMAP_DMA_DATA_TYPE_S32 0x02
44 #define OMAP_DMA_SYNC_ELEMENT 0x00
45 #define OMAP_DMA_SYNC_FRAME 0x01
46 #define OMAP_DMA_SYNC_BLOCK 0x02
47 #define OMAP_DMA_SYNC_PACKET 0x03
49 #define OMAP_DMA_DST_SYNC_PREFETCH 0x02
50 #define OMAP_DMA_SRC_SYNC 0x01
51 #define OMAP_DMA_DST_SYNC 0x00
53 #define OMAP_DMA_PORT_EMIFF 0x00
54 #define OMAP_DMA_PORT_EMIFS 0x01
55 #define OMAP_DMA_PORT_OCP_T1 0x02
56 #define OMAP_DMA_PORT_TIPB 0x03
57 #define OMAP_DMA_PORT_OCP_T2 0x04
58 #define OMAP_DMA_PORT_MPUI 0x05
60 #define OMAP_DMA_AMODE_CONSTANT 0x00
61 #define OMAP_DMA_AMODE_POST_INC 0x01
62 #define OMAP_DMA_AMODE_SINGLE_IDX 0x02
63 #define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
65 #define DMA_DEFAULT_FIFO_DEPTH 0x10
66 #define DMA_DEFAULT_ARB_RATE 0x01
68 #define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */
69 #define DMA_THREAD_RESERVE_ONET (0x01 << 12)
70 #define DMA_THREAD_RESERVE_TWOT (0x02 << 12)
71 #define DMA_THREAD_RESERVE_THREET (0x03 << 12)
72 #define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */
73 #define DMA_THREAD_FIFO_75 (0x01 << 14)
74 #define DMA_THREAD_FIFO_25 (0x02 << 14)
75 #define DMA_THREAD_FIFO_50 (0x03 << 14)
83 #define DMA_SYSCONFIG_AUTOIDLE (1 << 0)
88 #define DMA_IDLEMODE_SMARTIDLE 0x2
89 #define DMA_IDLEMODE_NO_IDLE 0x1
90 #define DMA_IDLEMODE_FORCE_IDLE 0x0
94 #define OMAP_DMA_STATIC_CHAIN 0x1
95 #define OMAP_DMA_DYNAMIC_CHAIN 0x2
96 #define OMAP_DMA_CHAIN_ACTIVE 0x1
97 #define OMAP_DMA_CHAIN_INACTIVE 0x0
100 #define DMA_CH_PRIO_HIGH 0x1
101 #define DMA_CH_PRIO_LOW 0x0 /* Def */
107 #define DMA_ERRATA_IFRAME_BUFFERING BIT(0x0)
108 #define DMA_ERRATA_PARALLEL_CHANNELS BIT(0x1)
109 #define DMA_ERRATA_i378 BIT(0x2)
110 #define DMA_ERRATA_i541 BIT(0x3)
111 #define DMA_ERRATA_i88 BIT(0x4)
112 #define DMA_ERRATA_3_3 BIT(0x5)
113 #define DMA_ROMCODE_BUG BIT(0x6)
116 #define DMA_LINKED_LCH BIT(0x0)
117 #define GLOBAL_PRIORITY BIT(0x1)
118 #define RESERVE_CHANNEL BIT(0x2)
119 #define IS_CSSA_32 BIT(0x3)
120 #define IS_CDSA_32 BIT(0x4)
121 #define IS_RW_PRIORITY BIT(0x5)
122 #define ENABLE_1510_MODE BIT(0x6)
123 #define SRC_PORT BIT(0x7)
124 #define DST_PORT BIT(0x8)
125 #define SRC_INDEX BIT(0x9)
126 #define DST_INDEX BIT(0xa)
127 #define IS_BURST_ONLY4 BIT(0xb)
128 #define CLEAR_CSR_ON_READ BIT(0xc)
129 #define IS_WORD_16 BIT(0xd)
130 #define ENABLE_16XX_MODE BIT(0xe)
131 #define HS_CHANNELS_RESERVED BIT(0xf)
134 #define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18)
135 #define DMA_HAS_CONSTANT_FILL_CAPS (0x1 << 19)
136 #define DMA_HAS_DESCRIPTOR_CAPS (0x3 << 20)
168 OMAP_DMA_DATA_BURST_DIS = 0,
175 OMAP_DMA_LITTLE_ENDIAN = 0,
180 OMAP_DMA_COLOR_DIS = 0,
186 OMAP_DMA_WRITE_NON_POSTED = 0,
192 OMAP_DMA_LCH_2D = 0,
204 int src_amode; /* constant, post increment, indexed,
205 double indexed */
211 int dst_amode; /* constant, post increment, indexed,
212 double indexed */
220 int src_or_dst_synch; /* source synch(1) or destination synch(0) */
287 #define dma_omap2plus() 0
290 #define __dma_omap15xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_1510_MODE)
291 #define __dma_omap16xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_16XX_MODE)
336 return 0; in omap_lcd_dma_running()
351 return -ENODEV; in omap_request_dma()