Lines Matching +full:nand +full:- +full:is +full:- +full:boot +full:- +full:medium
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
8 * Contains standard defines and IDs for NAND flash devices
17 #include <linux/mtd/nand.h>
21 #include <linux/mtd/nand.h>
29 /* The maximum number of NAND chips in an array */
50 * Standard NAND flash commands
73 #define NAND_CMD_NONE -1
82 #define NAND_DATA_IFACE_CHECK_ONLY -1
91 /* Enable Hardware ECC before syndrome is read back from flash */
95 * Enable generic NAND 'page erased' check. This check is only done when
96 * ecc.correct() returns -EBADMSG.
107 /* Buswidth is 16 bit */
122 * Chip requires ready check on read (for auto-incremented sequential read).
131 /* Device is one of 'new' xD cards that expose fake nand command set */
134 /* Device behaves just like nand, but is readonly */
140 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
158 * Autodetect nand buswidth with readid/onfi.
172 * In case your controller is implementing ->legacy.cmd_ctrl() and is relying
173 * on the default ->cmdfunc() implementation, you may want to let the core
174 * handle the tCCS delay which is required when a column change (RNDIN or
175 * RNDOUT) is requested.
182 * Whether the NAND chip is a boot medium. Drivers might use this information
183 * to select ECC algorithms supported by the boot ROM or similar restrictions.
188 * Do not try to tweak the timings at runtime. This is needed when the
223 * struct nand_parameters - NAND generic parameters from the parameter page
225 * @supports_set_get_features: The NAND chip supports setting/getting features
241 /* The maximum expected count of bytes in the NAND ID sequence */
245 * struct nand_id - NAND id structure
255 * struct nand_ecc_step_info - ECC step information of ECC engine
267 * struct nand_ecc_caps - capability of ECC engine
293 * struct nand_ecc_ctrl - Control structure for ECC
306 * @calc_buf: buffer for calculated ECC, size is oobsize.
307 * @code_buf: buffer for ECC read from flash, size is oobsize.
309 * be provided if an hardware ECC is available
313 * corrected bitflips, -EBADMSG if the number of bitflips exceed
314 * ECC strength, or any other error code if the error is not
316 * If -EBADMSG is returned the input buffers should be left
320 * controller and always return contiguous in-band and
321 * out-of-band data even if they're not stored
322 * contiguously on the NAND chip (e.g.
323 * NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
324 * out-of-band data).
328 * in-band and out-of-band data. ECC controller is
331 * NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
332 * out-of-band data).
335 * any single ECC step, -EIO hw error
386 * struct nand_sdr_timings - SDR NAND chip timings
388 * This struct defines the timing requirements of a SDR NAND chip.
389 * These information can be found in every NAND datasheets and the timings
407 * @tCHZ_max: CE# high to output hi-Z
416 * @tIR_min: Output hi-Z to RE# low
423 * @tRHZ_max: RE# high to output hi-Z
478 * enum nand_interface_type - NAND interface type
486 * struct nand_interface_config - NAND interface timing
490 * @timings.sdr: Use it when @type is %NAND_SDR_IFACE.
503 * nand_get_sdr_timings - get SDR timing from data interface
509 if (conf->type != NAND_SDR_IFACE) in nand_get_sdr_timings()
510 return ERR_PTR(-EINVAL); in nand_get_sdr_timings()
512 return &conf->timings.sdr; in nand_get_sdr_timings()
516 * struct nand_op_cmd_instr - Definition of a command instruction
524 * struct nand_op_addr_instr - Definition of an address instruction
534 * struct nand_op_data_instr - Definition of a data instruction
537 * @buf.in: buffer to fill when reading from the NAND chip
538 * @buf.out: buffer to read from when writing to the NAND chip
539 * @force_8bit: force 8-bit access
542 * and are from the controller perspective, so a "in" is a read from the NAND
543 * chip while a "out" is a write to the NAND chip.
555 * struct nand_op_waitrdy_instr - Definition of a wait ready instruction
563 * enum nand_op_instr_type - Definition of all instruction types
579 * struct nand_op_instr - Instruction object
583 * @ctx.cmd: use it if @type is %NAND_OP_CMD_INSTR
584 * @ctx.addr: use it if @type is %NAND_OP_ADDR_INSTR
585 * @ctx.data: use it if @type is %NAND_OP_DATA_IN_INSTR
587 * @ctx.waitrdy: use it if @type is %NAND_OP_WAITRDY_INSTR
606 * is either tPROG (after a prog), tR (before a read), tRST (during a reset) or
611 * Cast to type of dividend is needed here to guarantee that the result won't
612 * be an unsigned long long when the dividend is an unsigned long (or smaller),
613 * which is what the compiler does when it sees ternary operator with 2
694 * struct nand_subop - a sub operation
695 * @cs: the CS line to select for this NAND sub-operation
699 * of the sub-operation
701 * of the sub-operation
706 * When an operation cannot be handled as is by the NAND controller, it will
707 * be split by the parser into sub-operations which will be passed to the
728 * struct nand_op_parser_addr_constraints - Constraints for address instructions
737 * struct nand_op_parser_data_constraints - Constraints for data instructions
745 * struct nand_op_parser_pattern_elem - One element of a pattern
747 * @optional: whether this element of the pattern is optional or mandatory
795 * struct nand_op_parser_pattern - NAND sub-operation pattern descriptor
798 * @exec: the function that will issue a sub-operation
800 * A pattern is a list of elements, each element reprensenting one instruction
801 * with its constraints. The pattern itself is used by the core to match NAND
802 * chip operation with NAND controller operations.
803 * Once a match between a NAND controller operation pattern and a NAND chip
804 * operation (or a sub-set of a NAND operation) is found, the pattern ->exec()
805 * hook is called so that the controller driver can issue the operation on the
827 * struct nand_op_parser - NAND controller operation parser descriptor
831 * The parser descriptor is just an array of supported patterns which will be
833 * NAND operation (or tries to determine if a specific operation is supported).
835 * It is worth mentioning that patterns will be tested in their declaration
838 * the list. Usually, this is where you put single instruction patterns.
853 * struct nand_operation - NAND operation descriptor
854 * @cs: the CS line to select for this NAND operation
858 * The actual operation structure that will be passed to chip->exec_op().
881 switch (instr->type) { in nand_op_trace()
884 instr->ctx.cmd.opcode); in nand_op_trace()
888 instr->ctx.addr.naddrs, in nand_op_trace()
889 instr->ctx.addr.naddrs < 64 ? in nand_op_trace()
890 instr->ctx.addr.naddrs : 64, in nand_op_trace()
891 instr->ctx.addr.addrs); in nand_op_trace()
895 instr->ctx.data.len, in nand_op_trace()
896 instr->ctx.data.force_8bit ? in nand_op_trace()
897 ", force 8-bit" : ""); in nand_op_trace()
901 instr->ctx.data.len, in nand_op_trace()
902 instr->ctx.data.force_8bit ? in nand_op_trace()
903 ", force 8-bit" : ""); in nand_op_trace()
907 instr->ctx.waitrdy.timeout_ms); in nand_op_trace()
914 * struct nand_controller_ops - Controller operations
916 * @attach_chip: this method is called after the NAND detection phase after
919 * provided by the NAND chip or device tree. Typically used to
922 * This hook is optional.
924 * nand_controller_ops->attach_chip().
925 * This hook is optional.
926 * @exec_op: controller specific method to execute NAND operations.
927 * This method replaces chip->legacy.cmdfunc(),
928 * chip->legacy.{read,write}_{buf,byte,word}(),
929 * chip->legacy.dev_ready() and chip->legacy.waifunc().
930 * @setup_interface: setup the data interface and timing. If chipnr is set to
933 * This hook is optional.
946 * struct nand_controller - Structure used to describe a NAND controller
948 * @lock: lock used to serialize accesses to the NAND controller
949 * @ops: NAND controller operations.
958 mutex_init(&nfc->lock); in nand_controller_init()
962 * struct nand_legacy - NAND chip legacy fields/hooks
974 * If set to NULL no access to ready/busy is available and the
975 * ready/busy information is read from the chip status register.
977 * @block_bad: check if a block is bad, using OOB markers
979 * @set_features: set the NAND chip features
980 * @get_features: get the NAND chip features
1013 * struct nand_chip_ops - NAND chip operations
1018 * @setup_read_retry: Set the read-retry mode (mostly needed for MLC NANDs)
1032 * struct nand_manufacturer - NAND manufacturer structure
1042 * struct nand_chip - NAND Private Flash Chip Data
1043 * @base: Inherit from the generic NAND device
1044 * @id: Holds NAND ID
1047 * @ops: NAND chip operations
1050 * existing driver that is using those fields/hooks, you should
1055 * @current_interface_config: The currently used NAND interface configuration
1056 * @best_interface_config: The best NAND interface configuration which fits both
1057 * the NAND chip and NAND controller constraints. If
1066 * position; i.e., BBM = 11110111b is good when badblockbits = 7
1074 * @pagemask: Page number mask = number of (pages / chip) - 1
1076 * @data_buf: Buffer for data, size is (page size + oobsize)
1080 * @pagecache.page: Page number currently in the cache. -1 means no page is
1084 * to the NAND device
1085 * @suspended: Set to 1 when the device is suspended, 0 when it's not
1086 * @cur_cs: Currently selected target. -1 means no target selected, otherwise we
1088 * NAND Controller drivers should not modify this value, but they're
1091 * @controller: The hardware controller structure which is shared among multiple
1154 return &chip->base.mtd; in nand_to_mtd()
1159 return chip->priv; in nand_get_controller_data()
1164 chip->priv = priv; in nand_set_controller_data()
1170 chip->manufacturer.priv = priv; in nand_set_manufacturer_data()
1175 return chip->manufacturer.priv; in nand_get_manufacturer_data()
1190 * nand_get_interface_config - Retrieve the current interface configuration
1191 * of a NAND chip
1192 * @chip: The NAND chip
1197 return chip->current_interface_config; in nand_get_interface_config()
1201 * A helper for defining older NAND chips where the second ID byte fully
1203 * size). All these chips have 512 bytes NAND page size.
1213 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
1225 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
1226 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
1229 * struct nand_flash_dev - NAND Flash Device ID Structure
1230 * @name: a human-readable name of the NAND chip
1237 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1238 * well as the eraseblock size) is determined from the extended NAND
1277 * Check if it is a SLC nand.
1278 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1283 WARN(nanddev_bits_per_cell(&chip->base) == 0, in nand_is_slc()
1284 "chip->bits_per_cell is used uninitialized\n"); in nand_is_slc()
1285 return nanddev_bits_per_cell(&chip->base) == 1; in nand_is_slc()
1336 /* Reset and initialize a NAND device */
1339 /* NAND operation helpers */
1367 /* Scan and identify a NAND device */
1380 * Free resources held by the NAND device, must be called on error after a
1394 /* Select/deselect a NAND target. */
1403 * nand_get_data_buf() - Get the internal page buffer
1404 * @chip: NAND chip object
1406 * Returns the pre-allocated page buffer after invalidating the cache. This
1418 chip->pagecache.page = -1; in nand_get_data_buf()
1420 return chip->data_buf; in nand_get_data_buf()