1157 	/* NUM OF CAP Types */
1189 #define MLX5_CAP_GEN(mdev, cap) \  argument
1190 	MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
1192 #define MLX5_CAP_GEN_64(mdev, cap) \  argument
1193 	MLX5_GET64(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
1195 #define MLX5_CAP_GEN_MAX(mdev, cap) \  argument
1196 	MLX5_GET(cmd_hca_cap, mdev->caps.hca_max[MLX5_CAP_GENERAL], cap)
1198 #define MLX5_CAP_ETH(mdev, cap) \  argument
1200 		 mdev->caps.hca_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1202 #define MLX5_CAP_ETH_MAX(mdev, cap) \  argument
1204 		 mdev->caps.hca_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1206 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \  argument
1208 		 mdev->caps.hca_cur[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS], cap)
1210 #define MLX5_CAP_ROCE(mdev, cap) \  argument
1211 	MLX5_GET(roce_cap, mdev->caps.hca_cur[MLX5_CAP_ROCE], cap)
1213 #define MLX5_CAP_ROCE_MAX(mdev, cap) \  argument
1214 	MLX5_GET(roce_cap, mdev->caps.hca_max[MLX5_CAP_ROCE], cap)
1216 #define MLX5_CAP_ATOMIC(mdev, cap) \  argument
1217 	MLX5_GET(atomic_caps, mdev->caps.hca_cur[MLX5_CAP_ATOMIC], cap)
1219 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \  argument
1220 	MLX5_GET(atomic_caps, mdev->caps.hca_max[MLX5_CAP_ATOMIC], cap)
1222 #define MLX5_CAP_FLOWTABLE(mdev, cap) \  argument
1223 	MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
1225 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \  argument
1226 	MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
1228 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \  argument
1229 	MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap)
1231 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \  argument
1232 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1234 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \  argument
1235 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1237 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \  argument
1238 		MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap)
1240 #define MLX5_CAP_FLOWTABLE_NIC_TX_MAX(mdev, cap) \  argument
1241 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit.cap)
1243 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \  argument
1244 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1246 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \  argument
1247 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
1249 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \  argument
1250 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1252 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \  argument
1253 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1255 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \  argument
1256 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap)
1258 #define MLX5_CAP_FLOWTABLE_RDMA_RX_MAX(mdev, cap) \  argument
1259 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_rdma.cap)
1261 #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \  argument
1262 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap)
1264 #define MLX5_CAP_FLOWTABLE_RDMA_TX_MAX(mdev, cap) \  argument
1265 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_rdma.cap)
1267 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \  argument
1269 		 mdev->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1271 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \  argument
1273 		 mdev->caps.hca_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1275 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \  argument
1276 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1278 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \  argument
1279 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1281 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \  argument
1282 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1284 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \  argument
1285 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1287 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \  argument
1288 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1290 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \  argument
1291 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1293 #define MLX5_CAP_ESW(mdev, cap) \  argument
1295 		 mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap)
1297 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \  argument
1299 		(mdev)->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1301 #define MLX5_CAP_ESW_MAX(mdev, cap) \  argument
1303 		 mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap)
1305 #define MLX5_CAP_ODP(mdev, cap)\  argument
1306 	MLX5_GET(odp_cap, mdev->caps.hca_cur[MLX5_CAP_ODP], cap)
1308 #define MLX5_CAP_ODP_MAX(mdev, cap)\  argument
1309 	MLX5_GET(odp_cap, mdev->caps.hca_max[MLX5_CAP_ODP], cap)
1311 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \  argument
1313 		 mdev->caps.hca_cur[MLX5_CAP_VECTOR_CALC], cap)
1315 #define MLX5_CAP_QOS(mdev, cap)\  argument
1316 	MLX5_GET(qos_cap, mdev->caps.hca_cur[MLX5_CAP_QOS], cap)
1318 #define MLX5_CAP_DEBUG(mdev, cap)\  argument
1319 	MLX5_GET(debug_cap, mdev->caps.hca_cur[MLX5_CAP_DEBUG], cap)
1348 #define MLX5_CAP_FPGA(mdev, cap) \  argument
1349 	MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1351 #define MLX5_CAP64_FPGA(mdev, cap) \  argument
1352 	MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1354 #define MLX5_CAP_DEV_MEM(mdev, cap)\  argument
1355 	MLX5_GET(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
1357 #define MLX5_CAP64_DEV_MEM(mdev, cap)\  argument
1358 	MLX5_GET64(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
1360 #define MLX5_CAP_TLS(mdev, cap) \  argument
1361 	MLX5_GET(tls_cap, (mdev)->caps.hca_cur[MLX5_CAP_TLS], cap)
1363 #define MLX5_CAP_DEV_EVENT(mdev, cap)\  argument
1364 	MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca_cur[MLX5_CAP_DEV_EVENT], cap)
1366 #define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\  argument
1368 		(mdev)->caps.hca_cur[MLX5_CAP_VDPA_EMULATION], cap)
1370 #define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\  argument
1372 		(mdev)->caps.hca_cur[MLX5_CAP_VDPA_EMULATION], cap)
1374 #define MLX5_CAP_IPSEC(mdev, cap)\  argument
1375 	MLX5_GET(ipsec_cap, (mdev)->caps.hca_cur[MLX5_CAP_IPSEC], cap)