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1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/dma-mapping.h>
26 #define TIM_ARR 0x2c /* Auto-Reload Register */
31 #define TIM_BDTR 0x44 /* Break and Dead-Time Reg */
35 #define TIM_CR1_CEN BIT(0) /* Counter Enable */
36 #define TIM_CR1_DIR BIT(4) /* Counter Direction */
37 #define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */
38 #define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */
40 #define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */
41 #define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */
42 #define TIM_DIER_UIE BIT(0) /* Update interrupt */
43 #define TIM_DIER_UDE BIT(8) /* Update DMA request Enable */
44 #define TIM_DIER_CC1DE BIT(9) /* CC1 DMA request Enable */
45 #define TIM_DIER_CC2DE BIT(10) /* CC2 DMA request Enable */
46 #define TIM_DIER_CC3DE BIT(11) /* CC3 DMA request Enable */
47 #define TIM_DIER_CC4DE BIT(12) /* CC4 DMA request Enable */
48 #define TIM_DIER_COMDE BIT(13) /* COM DMA request Enable */
49 #define TIM_DIER_TDE BIT(14) /* Trigger DMA request Enable */
50 #define TIM_SR_UIF BIT(0) /* Update interrupt flag */
51 #define TIM_EGR_UG BIT(0) /* Update Generation */
52 #define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */
53 #define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */
54 #define TIM_CCMR_CC1S (BIT(0) | BIT(1)) /* Capture/compare 1 sel */
56 #define TIM_CCMR_CC2S (BIT(8) | BIT(9)) /* Capture/compare 2 sel */
58 #define TIM_CCMR_CC1S_TI1 BIT(0) /* IC1/IC3 selects TI1/TI3 */
59 #define TIM_CCMR_CC1S_TI2 BIT(1) /* IC1/IC3 selects TI2/TI4 */
60 #define TIM_CCMR_CC2S_TI2 BIT(8) /* IC2/IC4 selects TI2/TI4 */
61 #define TIM_CCMR_CC2S_TI1 BIT(9) /* IC2/IC4 selects TI1/TI3 */
62 #define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */
63 #define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */
64 #define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */
65 #define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */
66 #define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */
67 #define TIM_CCER_CC2P BIT(5) /* Capt/Comp 2 Polarity */
68 #define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */
69 #define TIM_CCER_CC3P BIT(9) /* Capt/Comp 3 Polarity */
70 #define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */
71 #define TIM_CCER_CC4P BIT(13) /* Capt/Comp 4 Polarity */
72 #define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12))
73 #define TIM_BDTR_BKE(x) BIT(12 + (x) * 12) /* Break input enable */
74 #define TIM_BDTR_BKP(x) BIT(13 + (x) * 12) /* Break input polarity */
75 #define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */
76 #define TIM_BDTR_MOE BIT(15) /* Main Output Enable */
79 #define TIM_DCR_DBL GENMASK(12, 8) /* DMA burst len */
101 * struct stm32_timers_dma - STM32 timer DMA handling.
136 return -ENODEV; in stm32_timers_dma_burst_read()