Lines Matching +full:6 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Defining registers address and its bit definitions of MAX77620 and MAX20024
74 #define MAX77620_TRACK4_MASK BIT(5)
118 #define MAX77620_FPS_SRC_SHIFT 6
157 #define MAX77620_SD_CNF2_ROVS_EN_SD1 BIT(1)
158 #define MAX77620_SD_CNF2_ROVS_EN_SD0 BIT(2)
167 #define MAX77620_SD_SR_SHIFT 6
170 #define MAX77620_SD_CFG1_ADE_MASK BIT(3)
172 #define MAX77620_SD_CFG1_ADE_ENABLE BIT(3)
177 #define MAX77620_SD_CFG1_FPWM_SD_MASK BIT(2)
179 #define MAX77620_SD_CFG1_FPWM_SD_FPWM BIT(2)
180 #define MAX20024_SD_CFG1_MPOK_MASK BIT(1)
181 #define MAX77620_SD_CFG1_FSRADE_SD_MASK BIT(0)
183 #define MAX77620_SD_CFG1_FSRADE_SD_ENABLE BIT(0)
187 #define MAX77620_LDO_POWER_MODE_SHIFT 6
188 #define MAX20024_LDO_CFG2_MPOK_MASK BIT(2)
189 #define MAX77620_LDO_CFG2_ADE_MASK BIT(1)
191 #define MAX77620_LDO_CFG2_ADE_ENABLE BIT(1)
192 #define MAX77620_LDO_CFG2_SS_MASK BIT(0)
193 #define MAX77620_LDO_CFG2_SS_FAST BIT(0)
196 #define MAX77620_IRQ_TOP_GLBL_MASK BIT(7)
197 #define MAX77620_IRQ_TOP_SD_MASK BIT(6)
198 #define MAX77620_IRQ_TOP_LDO_MASK BIT(5)
199 #define MAX77620_IRQ_TOP_GPIO_MASK BIT(4)
200 #define MAX77620_IRQ_TOP_RTC_MASK BIT(3)
201 #define MAX77620_IRQ_TOP_32K_MASK BIT(2)
202 #define MAX77620_IRQ_TOP_ONOFF_MASK BIT(1)
204 #define MAX77620_IRQ_LBM_MASK BIT(3)
205 #define MAX77620_IRQ_TJALRM1_MASK BIT(2)
206 #define MAX77620_IRQ_TJALRM2_MASK BIT(1)
211 #define MAX77620_CNFG_GPIO_DRV_MASK BIT(0)
212 #define MAX77620_CNFG_GPIO_DRV_PUSHPULL BIT(0)
214 #define MAX77620_CNFG_GPIO_DIR_MASK BIT(1)
215 #define MAX77620_CNFG_GPIO_DIR_INPUT BIT(1)
217 #define MAX77620_CNFG_GPIO_INPUT_VAL_MASK BIT(2)
218 #define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK BIT(3)
219 #define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH BIT(3)
222 #define MAX77620_CNFG_GPIO_INT_FALLING BIT(4)
223 #define MAX77620_CNFG_GPIO_INT_RISING BIT(5)
224 #define MAX77620_CNFG_GPIO_DBNC_MASK (0x3 << 6)
225 #define MAX77620_CNFG_GPIO_DBNC_None (0x0 << 6)
226 #define MAX77620_CNFG_GPIO_DBNC_8ms (0x1 << 6)
227 #define MAX77620_CNFG_GPIO_DBNC_16ms (0x2 << 6)
228 #define MAX77620_CNFG_GPIO_DBNC_32ms (0x3 << 6)
230 #define MAX77620_IRQ_LVL2_GPIO_EDGE0 BIT(0)
231 #define MAX77620_IRQ_LVL2_GPIO_EDGE1 BIT(1)
232 #define MAX77620_IRQ_LVL2_GPIO_EDGE2 BIT(2)
233 #define MAX77620_IRQ_LVL2_GPIO_EDGE3 BIT(3)
234 #define MAX77620_IRQ_LVL2_GPIO_EDGE4 BIT(4)
235 #define MAX77620_IRQ_LVL2_GPIO_EDGE5 BIT(5)
236 #define MAX77620_IRQ_LVL2_GPIO_EDGE6 BIT(6)
237 #define MAX77620_IRQ_LVL2_GPIO_EDGE7 BIT(7)
239 #define MAX77620_CNFG1_32K_OUT0_EN BIT(2)
241 #define MAX77620_ONOFFCNFG1_SFT_RST BIT(7)
244 #define MAX77620_ONOFFCNFG1_SLPEN BIT(2)
245 #define MAX77620_ONOFFCNFG1_PWR_OFF BIT(1)
248 #define MAX77620_ONOFFCNFG2_SFT_RST_WK BIT(7)
249 #define MAX77620_ONOFFCNFG2_WD_RST_WK BIT(6)
250 #define MAX77620_ONOFFCNFG2_SLP_LPM_MSK BIT(5)
251 #define MAX77620_ONOFFCNFG2_WK_ALARM1 BIT(2)
252 #define MAX77620_ONOFFCNFG2_WK_EN0 BIT(0)
254 #define MAX77620_GLBLM_MASK BIT(0)
257 #define MAX77620_WDTOFFC BIT(4)
258 #define MAX77620_WDTSLPC BIT(3)
259 #define MAX77620_WDTEN BIT(2)
267 #define MAX77620_CNFGGLBL1_LBDAC_EN BIT(7)
268 #define MAX77620_CNFGGLBL1_MPPLD BIT(6)
269 #define MAX77620_CNFGGLBL1_LBHYST (BIT(5) | BIT(4))
271 #define MAX77620_CNFGGLBL1_LBRSTEN BIT(0)
274 #define MAX77620_CNFGBBC_ENABLE BIT(0)
279 #define MAX77620_CNFGBBC_LOW_CURRENT_DISABLE BIT(5)
281 #define MAX77620_CNFGBBC_RESISTOR_SHIFT 6
287 MAX77620_IRQ_TOP_GLBL, /* Low-Battery */