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11 #define BLOCK_XG_MDIO_CSR_OFFSET 0x5000
12 #define BLOCK_DIAG_CSR_OFFSET 0xd000
13 #define XGENET_CONFIG_REG_ADDR 0x20
15 #define MAC_ADDR_REG_OFFSET 0x00
16 #define MAC_COMMAND_REG_OFFSET 0x04
17 #define MAC_WRITE_REG_OFFSET 0x08
18 #define MAC_READ_REG_OFFSET 0x0c
19 #define MAC_COMMAND_DONE_REG_OFFSET 0x10
21 #define CLKEN_OFFSET 0x08
22 #define SRST_OFFSET 0x00
24 #define MENET_CFG_MEM_RAM_SHUTDOWN_ADDR 0x70
25 #define MENET_BLOCK_MEM_RDY_ADDR 0x74
27 #define MAC_CONFIG_1_ADDR 0x00
28 #define MII_MGMT_COMMAND_ADDR 0x24
29 #define MII_MGMT_ADDRESS_ADDR 0x28
30 #define MII_MGMT_CONTROL_ADDR 0x2c
31 #define MII_MGMT_STATUS_ADDR 0x30
32 #define MII_MGMT_INDICATORS_ADDR 0x34
35 #define MII_MGMT_CONFIG_ADDR 0x20
36 #define MII_MGMT_COMMAND_ADDR 0x24
37 #define MII_MGMT_ADDRESS_ADDR 0x28
38 #define MII_MGMT_CONTROL_ADDR 0x2c
39 #define MII_MGMT_STATUS_ADDR 0x30
40 #define MII_MGMT_INDICATORS_ADDR 0x34
42 #define MIIM_COMMAND_ADDR 0x20
43 #define MIIM_FIELD_ADDR 0x24
44 #define MIIM_CONFIGURATION_ADDR 0x28
45 #define MIIM_LINKFAILVECTOR_ADDR 0x2c
46 #define MIIM_INDICATOR_ADDR 0x30
47 #define MIIMRD_FIELD_ADDR 0x34
49 #define MDIO_CSR_OFFSET 0x5000
51 #define REG_ADDR_POS 0
56 #define HSTMIIMWRDAT_POS 0
63 #define HSTMIIMCMD_POS 0
66 #define BUSY_MASK BIT(0)
67 #define READ_CYCLE_MASK BIT(0)