Lines Matching full:divider

44  * @use_alt_clock_src: Channel divider uses alternative clk source.
47  * @divider_phase: Divider initial phase after a SYNC. Range 0..63
48 		   LSB = 1/2 of a period of the divider input clock.
49  * @channel_divider: 10-bit channel divider.
117  * @refa_r_div: PLL1 10-bit REFA R divider.
118  * @refb_r_div: PLL1 10-bit REFB R divider.
119  * @pll1_feedback_div: PLL1 10-bit Feedback N divider.
127  * @pll2_ndiv_a_cnt: PLL2 Feedback N-divider, A Counter, range 0..4.
128  * @pll2_ndiv_b_cnt: PLL2 Feedback N-divider, B Counter, range 0..63.
130  * @pll2_r2_div: PLL2 R2 divider, range 0..31.
131  * @pll2_vco_div_m1: VCO1 divider, range 3..5.
132  * @pll2_vco_div_m2: VCO2 divider, range 3..5.